]> git.openfabrics.org - ~shefty/rdma-dev.git/commitdiff
Merge branch 'next/soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux...
authorLinus Torvalds <torvalds@linux-foundation.org>
Wed, 27 Jul 2011 00:09:31 +0000 (17:09 -0700)
committerLinus Torvalds <torvalds@linux-foundation.org>
Wed, 27 Jul 2011 00:09:31 +0000 (17:09 -0700)
* 'next/soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc:
  MAINTAINERS: add maintainer of CSR SiRFprimaII machine
  ARM: CSR: initializing L2 cache
  ARM: CSR: mapping early DEBUG_LL uart
  ARM: CSR: Adding CSR SiRFprimaII board support
  OMAP4: clocks: Update the clock tree with 4460 clock nodes
  OMAP4: PRCM: OMAP4460 specific PRM and CM register bitshifts
  OMAP4: ID: add omap_has_feature for max freq supported
  OMAP: ID: introduce chip detection for OMAP4460
  ARM: Xilinx: merge board file into main platform code
  ARM: Xilinx: Adding Xilinx board support

Fix up conflicts in arch/arm/mach-omap2/cm-regbits-44xx.h

1  2 
MAINTAINERS
arch/arm/Kconfig
arch/arm/Makefile
arch/arm/mach-omap2/clock44xx_data.c
arch/arm/mach-omap2/cm-regbits-44xx.h
arch/arm/plat-omap/include/plat/clock.h

diff --combined MAINTAINERS
index bf99d93c63662ddd639fb1bb222bc3f8f575609b,09cbbbb40cd1e9dc9060fef179bb7ce2853408b9..7b2e9e85e427e50d77d41ddad93281461134f47c
@@@ -1,5 -1,4 +1,5 @@@
  
 +
        List of maintainers and how to submit kernel changes
  
  Please try to follow the guidelines below.  This will make things
@@@ -534,8 -533,6 +534,8 @@@ L: device-drivers-devel@blackfin.uclinu
  L:    alsa-devel@alsa-project.org (moderated for non-subscribers)
  W:    http://wiki.analog.com/
  S:    Supported
 +F:    sound/soc/codecs/adau*
 +F:    sound/soc/codecs/adav*
  F:    sound/soc/codecs/ad1*
  F:    sound/soc/codecs/ssm*
  
@@@ -597,16 -594,6 +597,16 @@@ S:       Maintaine
  F:    arch/arm/lib/floppydma.S
  F:    arch/arm/include/asm/floppy.h
  
 +ARM PMU PROFILING AND DEBUGGING
 +M:    Will Deacon <will.deacon@arm.com>
 +S:    Maintained
 +F:    arch/arm/kernel/perf_event*
 +F:    arch/arm/oprofile/common.c
 +F:    arch/arm/kernel/pmu.c
 +F:    arch/arm/include/asm/pmu.h
 +F:    arch/arm/kernel/hw_breakpoint.c
 +F:    arch/arm/include/asm/hw_breakpoint.h
 +
  ARM PORT
  M:    Russell King <linux@arm.linux.org.uk>
  L:    linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@@ -696,7 -683,7 +696,7 @@@ T: git git://git.infradead.org/users/cb
  
  ARM/CIRRUS LOGIC EP93XX ARM ARCHITECTURE
  M:    Hartley Sweeten <hsweeten@visionengravers.com>
 -M:    Ryan Mallon <ryan@bluewatersys.com>
 +M:    Ryan Mallon <rmallon@gmail.com>
  L:    linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
  S:    Maintained
  F:    arch/arm/mach-ep93xx/
@@@ -734,6 -721,12 +734,12 @@@ T:       git git://git.berlios.de/gemini-boar
  S:    Maintained
  F:    arch/arm/mach-gemini/
  
+ ARM/CSR SIRFPRIMA2 MACHINE SUPPORT
+ M:    Barry Song <baohua.song@csr.com>
+ L:    linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+ S:    Maintained
+ F:    arch/arm/mach-prima2/
  ARM/EBSA110 MACHINE SUPPORT
  M:    Russell King <linux@arm.linux.org.uk>
  L:    linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@@ -1546,20 -1539,13 +1552,20 @@@ F:   drivers/net/tg3.
  BROADCOM BRCM80211 IEEE802.11n WIRELESS DRIVER
  M:    Brett Rudley <brudley@broadcom.com>
  M:    Henry Ptasinski <henryp@broadcom.com>
 -M:    Dowan Kim <dowan@broadcom.com>
  M:    Roland Vossen <rvossen@broadcom.com>
  M:    Arend van Spriel <arend@broadcom.com>
 +M:    Franky (Zhenhui) Lin <frankyl@broadcom.com>
 +M:    Kan Yan <kanyan@broadcom.com>
  L:    linux-wireless@vger.kernel.org
  S:    Supported
  F:    drivers/staging/brcm80211/
  
 +BROADCOM BNX2FC 10 GIGABIT FCOE DRIVER
 +M:    Bhanu Prakash Gollapudi <bprakash@broadcom.com>
 +L:    linux-scsi@vger.kernel.org
 +S:    Supported
 +F:    drivers/scsi/bnx2fc/
 +
  BROCADE BFA FC SCSI DRIVER
  M:    Jing Huang <huangj@brocade.com>
  L:    linux-scsi@vger.kernel.org
@@@ -1589,7 -1575,7 +1595,7 @@@ F:      Documentation/sound/alsa/Bt87x.tx
  F:    sound/pci/bt87x.c
  
  BT8XXGPIO DRIVER
 -M:    Michael Buesch <mb@bu3sch.de>
 +M:    Michael Buesch <m@bues.ch>
  W:    http://bu3sch.de/btgpio.php
  S:    Maintained
  F:    drivers/gpio/bt8xxgpio.c
@@@ -1782,8 -1768,7 +1788,8 @@@ F:      include/linux/clk.
  
  CISCO FCOE HBA DRIVER
  M:    Abhijeet Joglekar <abjoglek@cisco.com>
 -M:    Joe Eykholt <jeykholt@cisco.com>
 +M:    Venkata Siva Vijayendra Bhamidipati <vbhamidi@cisco.com>
 +M:    Brian Uchino <buchino@cisco.com>
  L:    linux-scsi@vger.kernel.org
  S:    Supported
  F:    drivers/scsi/fnic/
@@@ -3013,7 -2998,7 +3019,7 @@@ F:      kernel/hrtimer.
  F:    kernel/time/clockevents.c
  F:    kernel/time/tick*.*
  F:    kernel/time/timer_*.c
 -F:    include/linux/clockevents.h
 +F:    include/linux/clockchips.h
  F:    include/linux/hrtimer.h
  
  HIGH-SPEED SCC DRIVER FOR AX.25
@@@ -3436,9 -3421,10 +3442,9 @@@ S:     Maintaine
  F:    drivers/net/ipg.*
  
  IPATH DRIVER
 -M:    Ralph Campbell <infinipath@qlogic.com>
 +M:    Mike Marciniszyn <infinipath@qlogic.com>
  L:    linux-rdma@vger.kernel.org
 -T:    git git://git.qlogic.com/ipath-linux-2.6
 -S:    Supported
 +S:    Maintained
  F:    drivers/infiniband/hw/ipath/
  
  IPMI SUBSYSTEM
@@@ -3896,7 -3882,7 +3902,7 @@@ F:      arch/powerpc/platforms/512x
  F:    arch/powerpc/platforms/52xx/
  
  LINUX FOR POWERPC EMBEDDED PPC4XX
 -M:    Josh Boyer <jwboyer@linux.vnet.ibm.com>
 +M:    Josh Boyer <jwboyer@gmail.com>
  M:    Matt Porter <mporter@kernel.crashing.org>
  W:    http://www.penguinppc.org/
  L:    linuxppc-dev@lists.ozlabs.org
@@@ -3928,7 -3914,6 +3934,7 @@@ W:      http://www.penguinppc.org
  L:    linuxppc-dev@lists.ozlabs.org
  S:    Maintained
  F:    arch/powerpc/platforms/83xx/
 +F:    arch/powerpc/platforms/85xx/
  
  LINUX FOR POWERPC PA SEMI PWRFICIENT
  M:    Olof Johansson <olof@lixom.net>
@@@ -3962,13 -3947,6 +3968,13 @@@ L:    lm-sensors@lm-sensors.or
  S:    Maintained
  F:    drivers/hwmon/lm73.c
  
 +LM78 HARDWARE MONITOR DRIVER
 +M:    Jean Delvare <khali@linux-fr.org>
 +L:    lm-sensors@lm-sensors.org
 +S:    Maintained
 +F:    Documentation/hwmon/lm78
 +F:    drivers/hwmon/lm78.c
 +
  LM83 HARDWARE MONITOR DRIVER
  M:    Jean Delvare <khali@linux-fr.org>
  L:    lm-sensors@lm-sensors.org
@@@ -4115,12 -4093,6 +4121,12 @@@ S:    Maintaine
  F:    drivers/net/mv643xx_eth.*
  F:    include/linux/mv643xx.h
  
 +MARVELL MWIFIEX WIRELESS DRIVER
 +M:    Bing Zhao <bzhao@marvell.com>
 +L:    linux-wireless@vger.kernel.org
 +S:    Maintained
 +F:    drivers/net/wireless/mwifiex/
 +
  MARVELL MWL8K WIRELESS DRIVER
  M:    Lennert Buytenhek <buytenh@wantstofly.org>
  L:    linux-wireless@vger.kernel.org
@@@ -4217,10 -4189,9 +4223,10 @@@ F:    drivers/usb/image/microtek.
  
  MIPS
  M:    Ralf Baechle <ralf@linux-mips.org>
 -W:    http://www.linux-mips.org/
  L:    linux-mips@linux-mips.org
 +W:    http://www.linux-mips.org/
  T:    git git://git.linux-mips.org/pub/scm/linux.git
 +Q:    http://patchwork.linux-mips.org/project/linux-mips/list/
  S:    Supported
  F:    Documentation/mips/
  F:    arch/mips/
@@@ -4314,8 -4285,8 +4320,8 @@@ S:      Maintaine
  F:    drivers/usb/musb/
  
  MYRICOM MYRI-10G 10GbE DRIVER (MYRI10GE)
 +M:    Jon Mason <mason@myri.com>
  M:    Andrew Gallatin <gallatin@myri.com>
 -M:    Brice Goglin <brice@myri.com>
  L:    netdev@vger.kernel.org
  W:    http://www.myri.com/scs/download-Myri10GE.html
  S:    Supported
@@@ -4609,8 -4580,9 +4615,8 @@@ S:      Maintaine
  F:    drivers/mmc/host/omap.c
  
  OMAP HS MMC SUPPORT
 -M:    Madhusudhan Chikkature <madhu.cr@ti.com>
  L:    linux-omap@vger.kernel.org
 -S:    Maintained
 +S:    Orphan
  F:    drivers/mmc/host/omap_hsmmc.c
  
  OMAP RANDOM NUMBER GENERATOR SUPPORT
@@@ -4704,14 -4676,6 +4710,14 @@@ F:    drivers/o
  F:    include/linux/of*.h
  K:    of_get_property
  
 +OPENRISC ARCHITECTURE
 +M:    Jonas Bonn <jonas@southpole.se>
 +W:    http://openrisc.net
 +L:    linux@lists.openrisc.net
 +S:    Maintained
 +T:    git git://openrisc.net/~jonas/linux
 +F:    arch/openrisc
 +
  OPL4 DRIVER
  M:    Clemens Ladisch <clemens@ladisch.de>
  L:    alsa-devel@alsa-project.org (moderated for non-subscribers)
@@@ -5024,7 -4988,7 +5030,7 @@@ F:      drivers/power/power_supply
  
  PNP SUPPORT
  M:    Adam Belay <abelay@mit.edu>
 -M:    Bjorn Helgaas <bjorn.helgaas@hp.com>
 +M:    Bjorn Helgaas <bhelgaas@google.com>
  S:    Maintained
  F:    drivers/pnp/
  
@@@ -5184,12 -5148,6 +5190,12 @@@ M:    Robert Jarzmik <robert.jarzmik@free.
  L:    rtc-linux@googlegroups.com
  S:    Maintained
  
 +QIB DRIVER
 +M:    Mike Marciniszyn <infinipath@qlogic.com>
 +L:    linux-rdma@vger.kernel.org
 +S:    Supported
 +F:    drivers/infiniband/hw/qib/
 +
  QLOGIC QLA1280 SCSI DRIVER
  M:    Michael Reed <mdr@sgi.com>
  L:    linux-scsi@vger.kernel.org
@@@ -5351,13 -5309,6 +5357,13 @@@ L:    reiserfs-devel@vger.kernel.or
  S:    Supported
  F:    fs/reiserfs/
  
 +REGISTER MAP ABSTRACTION
 +M:    Mark Brown <broonie@opensource.wolfsonmicro.com>
 +T:    git git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap.git
 +S:    Supported
 +F:    drivers/base/regmap/
 +F:    include/linux/regmap.h
 +
  RFKILL
  M:    Johannes Berg <johannes@sipsolutions.net>
  L:    linux-wireless@vger.kernel.org
@@@ -5920,7 -5871,7 +5926,7 @@@ S:      Maintaine
  F:    drivers/net/sonic.*
  
  SONICS SILICON BACKPLANE DRIVER (SSB)
 -M:    Michael Buesch <mb@bu3sch.de>
 +M:    Michael Buesch <m@bues.ch>
  L:    netdev@vger.kernel.org
  S:    Maintained
  F:    drivers/ssb/
@@@ -6094,145 -6045,6 +6100,145 @@@ L:  devel@driverdev.osuosl.or
  S:    Maintained
  F:    drivers/staging/
  
 +STAGING - AGERE HERMES II and II.5 WIRELESS DRIVERS
 +M:    Henk de Groot <pe1dnn@amsat.org>
 +S:    Odd Fixes
 +F:    drivers/staging/wlags49_h2/
 +F:    drivers/staging/wlags49_h25/
 +
 +STAGING - ASUS OLED
 +M:    Jakub Schmidtke <sjakub@gmail.com>
 +S:    Odd Fixes
 +F:    drivers/staging/asus_oled/
 +
 +STAGING - ATHEROS ATH6KL WIRELESS DRIVER
 +M:    Luis R. Rodriguez <mcgrof@gmail.com>
 +M:    Naveen Singh <nsingh@atheros.com>
 +S:    Odd Fixes
 +F:    drivers/staging/ath6kl/
 +
 +STAGING - COMEDI
 +M:    Ian Abbott <abbotti@mev.co.uk>
 +M:    Mori Hess <fmhess@users.sourceforge.net>
 +S:    Odd Fixes
 +F:    drivers/staging/comedi/
 +
 +STAGING - CRYSTAL HD VIDEO DECODER
 +M:    Naren Sankar <nsankar@broadcom.com>
 +M:    Jarod Wilson <jarod@wilsonet.com>
 +M:    Scott Davilla <davilla@4pi.com>
 +M:    Manu Abraham <abraham.manu@gmail.com>
 +S:    Odd Fixes
 +F:    drivers/staging/crystalhd/
 +
 +STAGING - CYPRESS WESTBRIDGE SUPPORT
 +M:    David Cross <david.cross@cypress.com>
 +S:    Odd Fixes
 +F:    drivers/staging/westbridge/
 +
 +STAGING - ECHO CANCELLER
 +M:    Steve Underwood <steveu@coppice.org>
 +M:    David Rowe <david@rowetel.com>
 +S:    Odd Fixes
 +F:    drivers/staging/echo/
 +
 +STAGING - FLARION FT1000 DRIVERS
 +M:    Marek Belisko <marek.belisko@gmail.com>
 +S:    Odd Fixes
 +F:    drivers/staging/ft1000/
 +
 +STAGING - FRONTIER TRANZPORT AND ALPHATRACK
 +M:    David Täht <d@teklibre.com>
 +S:    Odd Fixes
 +F:    drivers/staging/frontier/
 +
 +STAGING - HYPER-V (MICROSOFT)
 +M:    Hank Janssen <hjanssen@microsoft.com>
 +M:    Haiyang Zhang <haiyangz@microsoft.com>
 +S:    Odd Fixes
 +F:    drivers/staging/hv/
 +
 +STAGING - INDUSTRIAL IO
 +M:    Jonathan Cameron <jic23@cam.ac.uk>
 +L:    linux-iio@vger.kernel.org
 +S:    Odd Fixes
 +F:    drivers/staging/iio/
 +
 +STAGING - LIRC (LINUX INFRARED REMOTE CONTROL) DRIVERS
 +M:    Jarod Wilson <jarod@wilsonet.com>
 +W:    http://www.lirc.org/
 +S:    Odd Fixes
 +F:    drivers/staging/lirc/
 +
 +STAGING - OLPC SECONDARY DISPLAY CONTROLLER (DCON)
 +M:    Andres Salomon <dilinger@queued.net>
 +M:    Chris Ball <cjb@laptop.org>
 +M:    Jon Nettleton <jon.nettleton@gmail.com>
 +W:    http://wiki.laptop.org/go/DCON
 +S:    Odd Fixes
 +F:    drivers/staging/olpc_dcon/
 +
 +STAGING - PARALLEL LCD/KEYPAD PANEL DRIVER
 +M:    Willy Tarreau <willy@meta-x.org>
 +S:    Odd Fixes
 +F:    drivers/staging/panel/
 +
 +STAGING - REALTEK RTL8712U DRIVERS
 +M:    Larry Finger <Larry.Finger@lwfinger.net>
 +M:    Florian Schilhabel <florian.c.schilhabel@googlemail.com>.
 +S:    Odd Fixes
 +F:    drivers/staging/rtl8712/
 +
 +STAGING - SILICON MOTION SM7XX FRAME BUFFER DRIVER
 +M:    Teddy Wang <teddy.wang@siliconmotion.com.cn>
 +S:    Odd Fixes
 +F:    drivers/staging/sm7xx/
 +
 +STAGING - SOFTLOGIC 6x10 MPEG CODEC
 +M:    Ben Collins <bcollins@bluecherry.net>
 +S:    Odd Fixes
 +F:    drivers/staging/solo6x10/
 +
 +STAGING - SPEAKUP CONSOLE SPEECH DRIVER
 +M:    William Hubbs <w.d.hubbs@gmail.com>
 +M:    Chris Brannon <chris@the-brannons.com>
 +M:    Kirk Reiser <kirk@braille.uwo.ca>
 +M:    Samuel Thibault <samuel.thibault@ens-lyon.org>
 +L:    speakup@braille.uwo.ca
 +W:    http://www.linux-speakup.org/
 +S:    Odd Fixes
 +F:    drivers/staging/speakup/
 +
 +STAGING - TI DSP BRIDGE DRIVERS
 +M:    Omar Ramirez Luna <omar.ramirez@ti.com>
 +S:    Odd Fixes
 +F:    drivers/staging/tidspbridge/
 +
 +STAGING - TRIDENT TVMASTER TMxxxx USB VIDEO CAPTURE DRIVERS
 +L:    linux-media@vger.kernel.org
 +S:    Odd Fixes
 +F:    drivers/staging/tm6000/
 +
 +STAGING - USB ENE SM/MS CARD READER DRIVER
 +M:    Al Cho <acho@novell.com>
 +S:    Odd Fixes
 +F:    drivers/staging/keucr/
 +
 +STAGING - VIA VT665X DRIVERS
 +M:    Forest Bond <forest@alittletooquiet.net>
 +S:    Odd Fixes
 +F:    drivers/staging/vt665?/
 +
 +STAGING - WINBOND IS89C35 WLAN USB DRIVER
 +M:    Pavel Machek <pavel@ucw.cz>
 +S:    Odd Fixes
 +F:    drivers/staging/winbond/
 +
 +STAGING - XGI Z7,Z9,Z11 PCI DISPLAY DRIVER
 +M:    Arnaud Patard <apatard@mandriva.com>
 +S:    Odd Fixes
 +F:    drivers/staging/xgifb/
 +
  STARFIRE/DURALAN NETWORK DRIVER
  M:    Ion Badulescu <ionut@badula.org>
  S:    Odd Fixes
@@@ -6426,14 -6238,9 +6432,14 @@@ F:    drivers/char/toshiba.
  F:    include/linux/toshiba.h
  
  TMIO MMC DRIVER
 +M:    Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  M:    Ian Molton <ian@mnementh.co.uk>
 +L:    linux-mmc@vger.kernel.org
  S:    Maintained
 -F:    drivers/mmc/host/tmio_mmc.*
 +F:    drivers/mmc/host/tmio_mmc*
 +F:    drivers/mmc/host/sh_mobile_sdhi.c
 +F:    include/linux/mmc/tmio.h
 +F:    include/linux/mmc/sh_mobile_sdhi.h
  
  TMPFS (SHMEM FILESYSTEM)
  M:    Hugh Dickins <hughd@google.com>
@@@ -6510,7 -6317,7 +6516,7 @@@ F:      drivers/scsi/u14-34f.
  
  UBI FILE SYSTEM (UBIFS)
  M:    Artem Bityutskiy <dedekind1@gmail.com>
 -M:    Adrian Hunter <adrian.hunter@nokia.com>
 +M:    Adrian Hunter <adrian.hunter@intel.com>
  L:    linux-mtd@lists.infradead.org
  T:    git git://git.infradead.org/ubifs-2.6.git
  W:    http://www.linux-mtd.infradead.org/doc/ubifs.html
@@@ -6735,6 -6542,13 +6741,6 @@@ W:     http://pegasus2.sourceforge.net
  S:    Maintained
  F:    drivers/net/usb/rtl8150.c
  
 -USB SE401 DRIVER
 -L:    linux-usb@vger.kernel.org
 -W:    http://www.chello.nl/~j.vreeken/se401/
 -S:    Orphan
 -F:    Documentation/video4linux/se401.txt
 -F:    drivers/staging/se401/
 -
  USB SERIAL BELKIN F5U103 DRIVER
  M:    William Greathouse <wgreathouse@smva.com>
  L:    linux-usb@vger.kernel.org
@@@ -7120,9 -6934,9 +7126,9 @@@ S:      Maintaine
  F:    drivers/input/misc/wistron_btns.c
  
  WL1251 WIRELESS DRIVER
 -M:    Kalle Valo <kvalo@adurom.com>
 +M:    Luciano Coelho <coelho@ti.com>
  L:    linux-wireless@vger.kernel.org
 -W:    http://wireless.kernel.org
 +W:    http://wireless.kernel.org/en/users/Drivers/wl1251
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-testing.git
  S:    Maintained
  F:    drivers/net/wireless/wl1251/*
diff --combined arch/arm/Kconfig
index 9cb1f4bd7618ac30723f55b9b89889afc3bfac24,7dc5986069cafffc95b8b96d7ba60660300c1545..1f6921172b1ce9bacd758b974197cad1e822faeb
@@@ -10,7 -10,7 +10,7 @@@ config AR
        select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
        select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
        select HAVE_ARCH_KGDB
 -      select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
 +      select HAVE_KPROBES if !XIP_KERNEL
        select HAVE_KRETPROBES if (HAVE_KPROBES)
        select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
        select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
@@@ -37,9 -37,6 +37,9 @@@
          Europe.  There is an ARM Linux project with a web page at
          <http://www.arm.linux.org.uk/>.
  
 +config ARM_HAS_SG_CHAIN
 +      bool
 +
  config HAVE_PWM
        bool
  
@@@ -340,6 -337,19 +340,19 @@@ config ARCH_GEMIN
        help
          Support for the Cortina Systems Gemini family SoCs
  
+ config ARCH_PRIMA2
+       bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
+       select CPU_V7
+       select GENERIC_TIME
+       select NO_IOPORT
+       select GENERIC_CLOCKEVENTS
+       select CLKDEV_LOOKUP
+       select GENERIC_IRQ_CHIP
+       select USE_OF
+       select ZONE_DMA
+       help
+           Support for CSR SiRFSoC ARM Cortex A9 Platform
  config ARCH_EBSA110
        bool "EBSA-110"
        select CPU_SA110
@@@ -493,6 -503,14 +506,6 @@@ config ARCH_KIRKWOO
          Support for the following Marvell Kirkwood series SoCs:
          88F6180, 88F6192 and 88F6281.
  
 -config ARCH_LOKI
 -      bool "Marvell Loki (88RC8480)"
 -      select CPU_FEROCEON
 -      select GENERIC_CLOCKEVENTS
 -      select PLAT_ORION
 -      help
 -        Support for the Marvell Loki (88RC8480) SoC.
 -
  config ARCH_LPC32XX
        bool "NXP LPC32XX"
        select CLKSRC_MMIO
@@@ -637,7 -655,6 +650,7 @@@ config ARCH_SHMOBIL
        select NO_IOPORT
        select SPARSE_IRQ
        select MULTI_IRQ_HANDLER
 +      select PM_GENERIC_DOMAINS if PM
        help
          Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
  
@@@ -678,7 -695,6 +691,7 @@@ config ARCH_S3C241
        select GENERIC_GPIO
        select ARCH_HAS_CPUFREQ
        select HAVE_CLK
 +      select CLKDEV_LOOKUP
        select ARCH_USES_GETTIMEOFFSET
        select HAVE_S3C2410_I2C if I2C
        help
@@@ -696,7 -712,6 +709,7 @@@ config ARCH_S3C64X
        select CPU_V6
        select ARM_VIC
        select HAVE_CLK
 +      select CLKDEV_LOOKUP
        select NO_IOPORT
        select ARCH_USES_GETTIMEOFFSET
        select ARCH_HAS_CPUFREQ
@@@ -721,8 -736,6 +734,8 @@@ config ARCH_S5P64X
        select CPU_V6
        select GENERIC_GPIO
        select HAVE_CLK
 +      select CLKDEV_LOOKUP
 +      select CLKSRC_MMIO
        select HAVE_S3C2410_WATCHDOG if WATCHDOG
        select GENERIC_CLOCKEVENTS
        select HAVE_SCHED_CLOCK
@@@ -736,7 -749,6 +749,7 @@@ config ARCH_S5PC10
        bool "Samsung S5PC100"
        select GENERIC_GPIO
        select HAVE_CLK
 +      select CLKDEV_LOOKUP
        select CPU_V7
        select ARM_L1_CACHE_SHIFT_6
        select ARCH_USES_GETTIMEOFFSET
@@@ -752,8 -764,6 +765,8 @@@ config ARCH_S5PV21
        select ARCH_SPARSEMEM_ENABLE
        select GENERIC_GPIO
        select HAVE_CLK
 +      select CLKDEV_LOOKUP
 +      select CLKSRC_MMIO
        select ARM_L1_CACHE_SHIFT_6
        select ARCH_HAS_CPUFREQ
        select GENERIC_CLOCKEVENTS
@@@ -770,7 -780,6 +783,7 @@@ config ARCH_EXYNOS
        select ARCH_SPARSEMEM_ENABLE
        select GENERIC_GPIO
        select HAVE_CLK
 +      select CLKDEV_LOOKUP
        select ARCH_HAS_CPUFREQ
        select GENERIC_CLOCKEVENTS
        select HAVE_S3C_RTC if RTC_CLASS
@@@ -856,7 -865,6 +869,7 @@@ config ARCH_OMA
        select HAVE_CLK
        select ARCH_REQUIRE_GPIOLIB
        select ARCH_HAS_CPUFREQ
 +      select CLKSRC_MMIO
        select GENERIC_CLOCKEVENTS
        select HAVE_SCHED_CLOCK
        select ARCH_HAS_HOLES_MEMORYMODEL
@@@ -884,6 -892,19 +897,19 @@@ config ARCH_VT850
        select HAVE_PWM
        help
          Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
+ config ARCH_ZYNQ
+       bool "Xilinx Zynq ARM Cortex A9 Platform"
+       select CPU_V7
+       select GENERIC_TIME
+       select GENERIC_CLOCKEVENTS
+       select CLKDEV_LOOKUP
+       select ARM_GIC
+       select ARM_AMBA
+       select ICST
+       select USE_OF
+       help
+         Support for Xilinx Zynq ARM Cortex A9 Platform
  endchoice
  
  #
@@@ -929,6 -950,8 +955,6 @@@ source "arch/arm/mach-kirkwood/Kconfig
  
  source "arch/arm/mach-ks8695/Kconfig"
  
 -source "arch/arm/mach-loki/Kconfig"
 -
  source "arch/arm/mach-lpc32xx/Kconfig"
  
  source "arch/arm/mach-msm/Kconfig"
@@@ -972,6 -995,7 +998,6 @@@ source "arch/arm/plat-spear/Kconfig
  source "arch/arm/plat-tcc/Kconfig"
  
  if ARCH_S3C2410
 -source "arch/arm/mach-s3c2400/Kconfig"
  source "arch/arm/mach-s3c2410/Kconfig"
  source "arch/arm/mach-s3c2412/Kconfig"
  source "arch/arm/mach-s3c2416/Kconfig"
@@@ -1348,6 -1372,7 +1374,6 @@@ config SMP_ON_U
  
  config HAVE_ARM_SCU
        bool
 -      depends on SMP
        help
          This option enables support for the ARM system coherency unit
  
@@@ -1716,34 -1741,17 +1742,34 @@@ config ZBOOT_RO
          Say Y here if you intend to execute your compressed kernel image
          (zImage) directly from ROM or flash.  If unsure, say N.
  
 +choice
 +      prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
 +      depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
 +      default ZBOOT_ROM_NONE
 +      help
 +        Include experimental SD/MMC loading code in the ROM-able zImage.
 +        With this enabled it is possible to write the the ROM-able zImage
 +        kernel image to an MMC or SD card and boot the kernel straight
 +        from the reset vector. At reset the processor Mask ROM will load
 +        the first part of the the ROM-able zImage which in turn loads the
 +        rest the kernel image to RAM.
 +
 +config ZBOOT_ROM_NONE
 +      bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
 +      help
 +        Do not load image from SD or MMC
 +
  config ZBOOT_ROM_MMCIF
        bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
 -      depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
        help
 -        Say Y here to include experimental MMCIF loading code in the
 -        ROM-able zImage. With this enabled it is possible to write the
 -        the ROM-able zImage kernel image to an MMC card and boot the
 -        kernel straight from the reset vector. At reset the processor
 -        Mask ROM will load the first part of the the ROM-able zImage
 -        which in turn loads the rest the kernel image to RAM using the
 -        MMCIF hardware block.
 +        Load image from MMCIF hardware block.
 +
 +config ZBOOT_ROM_SH_MOBILE_SDHI
 +      bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
 +      help
 +        Load image from SDHI hardware block
 +
 +endchoice
  
  config CMDLINE
        string "Default kernel command string"
@@@ -1893,6 -1901,10 +1919,6 @@@ config CPU_FREQ_PX
        default y
        select CPU_FREQ_DEFAULT_GOV_USERSPACE
  
 -config CPU_FREQ_S3C64XX
 -      bool "CPUfreq support for Samsung S3C64XX CPUs"
 -      depends on CPU_FREQ && CPU_S3C6410
 -
  config CPU_FREQ_S3C
        bool
        help
diff --combined arch/arm/Makefile
index 206c34ecb9e35fdc5fa6d2ac8d62144b68d0c84b,054a876678409a5b390770cdbf932a422c0a3d5c..3a4a04b33d0f7761ca4963e28bac99ff64960238
@@@ -150,6 -150,7 +150,6 @@@ machine-$(CONFIG_ARCH_IXP23XX)             := ixp2
  machine-$(CONFIG_ARCH_IXP4XX)         := ixp4xx
  machine-$(CONFIG_ARCH_KIRKWOOD)               := kirkwood
  machine-$(CONFIG_ARCH_KS8695)         := ks8695
 -machine-$(CONFIG_ARCH_LOKI)           := loki
  machine-$(CONFIG_ARCH_LPC32XX)                := lpc32xx
  machine-$(CONFIG_ARCH_MMP)            := mmp
  machine-$(CONFIG_ARCH_MSM)            := msm
@@@ -168,10 -169,12 +168,11 @@@ machine-$(CONFIG_ARCH_OMAP3)            := omap
  machine-$(CONFIG_ARCH_OMAP4)          := omap2
  machine-$(CONFIG_ARCH_ORION5X)                := orion5x
  machine-$(CONFIG_ARCH_PNX4008)                := pnx4008
+ machine-$(CONFIG_ARCH_PRIMA2)         := prima2
  machine-$(CONFIG_ARCH_PXA)            := pxa
  machine-$(CONFIG_ARCH_REALVIEW)               := realview
  machine-$(CONFIG_ARCH_RPC)            := rpc
 -machine-$(CONFIG_ARCH_S3C2410)                := s3c2410 s3c2400 s3c2412 s3c2416 s3c2440 s3c2443
 -machine-$(CONFIG_ARCH_S3C24A0)                := s3c24a0
 +machine-$(CONFIG_ARCH_S3C2410)                := s3c2410 s3c2412 s3c2416 s3c2440 s3c2443
  machine-$(CONFIG_ARCH_S3C64XX)                := s3c64xx
  machine-$(CONFIG_ARCH_S5P64X0)                := s5p64x0
  machine-$(CONFIG_ARCH_S5PC100)                := s5pc100
@@@ -194,6 -197,7 +195,7 @@@ machine-$(CONFIG_MACH_SPEAR300)            := spe
  machine-$(CONFIG_MACH_SPEAR310)               := spear3xx
  machine-$(CONFIG_MACH_SPEAR320)               := spear3xx
  machine-$(CONFIG_MACH_SPEAR600)               := spear6xx
+ machine-$(CONFIG_ARCH_ZYNQ)           := zynq
  
  # Platform directory name.  This list is sorted alphanumerically
  # by CONFIG_* macro name.
@@@ -201,6 -205,7 +203,7 @@@ plat-$(CONFIG_ARCH_MXC)            := mx
  plat-$(CONFIG_ARCH_OMAP)      := omap
  plat-$(CONFIG_ARCH_S3C64XX)   := samsung
  plat-$(CONFIG_ARCH_TCC_926)   := tcc
+ plat-$(CONFIG_ARCH_ZYNQ)      := versatile
  plat-$(CONFIG_PLAT_IOP)               := iop
  plat-$(CONFIG_PLAT_NOMADIK)   := nomadik
  plat-$(CONFIG_PLAT_ORION)     := orion
index 044df38f65ce951c01a11729b09030023b0ee465,639e00e0eac272b71b31be8d32d17c60f84ffeff..5b7cab794fb92f67664212120f669314deb9789e
@@@ -53,9 -53,9 +53,9 @@@ static struct clk extalt_clkin_ck = 
  static struct clk pad_clks_ck = {
        .name           = "pad_clks_ck",
        .rate           = 12000000,
 -      .ops            = &clkops_omap2_dflt,
 -      .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
 -      .enable_bit     = OMAP4430_PAD_CLKS_GATE_SHIFT,
 +      .ops            = &clkops_omap2_dflt,
 +      .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
 +      .enable_bit     = OMAP4430_PAD_CLKS_GATE_SHIFT,
  };
  
  static struct clk pad_slimbus_core_clks_ck = {
@@@ -73,9 -73,9 +73,9 @@@ static struct clk secure_32k_clk_src_c
  static struct clk slimbus_clk = {
        .name           = "slimbus_clk",
        .rate           = 12000000,
 -      .ops            = &clkops_omap2_dflt,
 -      .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
 -      .enable_bit     = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
 +      .ops            = &clkops_omap2_dflt,
 +      .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
 +      .enable_bit     = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
  };
  
  static struct clk sys_32k_ck = {
@@@ -258,8 -258,8 +258,8 @@@ static struct dpll_data dpll_abe_dd = 
        .enable_mask    = OMAP4430_DPLL_EN_MASK,
        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 -      .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 -      .max_divider    = OMAP4430_MAX_DPLL_DIV,
 +      .max_multiplier = 2047,
 +      .max_divider    = 128,
        .min_divider    = 1,
  };
  
@@@ -278,10 -278,10 +278,10 @@@ static struct clk dpll_abe_ck = 
  static struct clk dpll_abe_x2_ck = {
        .name           = "dpll_abe_x2_ck",
        .parent         = &dpll_abe_ck,
 +      .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
        .flags          = CLOCK_CLKOUTX2,
        .ops            = &clkops_omap4_dpllmx_ops,
        .recalc         = &omap3_clkoutx2_recalc,
 -      .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
  };
  
  static const struct clksel_rate div31_1to31_rates[] = {
@@@ -434,8 -434,8 +434,8 @@@ static struct dpll_data dpll_core_dd = 
        .enable_mask    = OMAP4430_DPLL_EN_MASK,
        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 -      .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 -      .max_divider    = OMAP4430_MAX_DPLL_DIV,
 +      .max_multiplier = 2047,
 +      .max_divider    = 128,
        .min_divider    = 1,
  };
  
@@@ -622,11 -622,11 +622,11 @@@ static struct clk dpll_core_m3x2_ck = 
        .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
        .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
        .ops            = &clkops_omap2_dflt,
 -      .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
 -      .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
        .recalc         = &omap2_clksel_recalc,
        .round_rate     = &omap2_clksel_round_rate,
        .set_rate       = &omap2_clksel_set_rate,
 +      .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
 +      .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
  };
  
  static struct clk dpll_core_m7x2_ck = {
@@@ -672,8 -672,8 +672,8 @@@ static struct dpll_data dpll_iva_dd = 
        .enable_mask    = OMAP4430_DPLL_EN_MASK,
        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 -      .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 -      .max_divider    = OMAP4430_MAX_DPLL_DIV,
 +      .max_multiplier = 2047,
 +      .max_divider    = 128,
        .min_divider    = 1,
  };
  
@@@ -740,8 -740,8 +740,8 @@@ static struct dpll_data dpll_mpu_dd = 
        .enable_mask    = OMAP4430_DPLL_EN_MASK,
        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 -      .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 -      .max_divider    = OMAP4430_MAX_DPLL_DIV,
 +      .max_multiplier = 2047,
 +      .max_divider    = 128,
        .min_divider    = 1,
  };
  
@@@ -813,8 -813,8 +813,8 @@@ static struct dpll_data dpll_per_dd = 
        .enable_mask    = OMAP4430_DPLL_EN_MASK,
        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 -      .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 -      .max_divider    = OMAP4430_MAX_DPLL_DIV,
 +      .max_multiplier = 2047,
 +      .max_divider    = 128,
        .min_divider    = 1,
  };
  
@@@ -850,10 -850,10 +850,10 @@@ static struct clk dpll_per_m2_ck = 
  static struct clk dpll_per_x2_ck = {
        .name           = "dpll_per_x2_ck",
        .parent         = &dpll_per_ck,
 +      .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
        .flags          = CLOCK_CLKOUTX2,
        .ops            = &clkops_omap4_dpllmx_ops,
        .recalc         = &omap3_clkoutx2_recalc,
 -      .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
  };
  
  static const struct clksel dpll_per_m2x2_div[] = {
@@@ -880,11 -880,11 +880,11 @@@ static struct clk dpll_per_m3x2_ck = 
        .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
        .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
        .ops            = &clkops_omap2_dflt,
 -      .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
 -      .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
        .recalc         = &omap2_clksel_recalc,
        .round_rate     = &omap2_clksel_round_rate,
        .set_rate       = &omap2_clksel_set_rate,
 +      .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
 +      .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
  };
  
  static struct clk dpll_per_m4x2_ck = {
@@@ -935,6 -935,63 +935,6 @@@ static struct clk dpll_per_m7x2_ck = 
        .set_rate       = &omap2_clksel_set_rate,
  };
  
 -/* DPLL_UNIPRO */
 -static struct dpll_data dpll_unipro_dd = {
 -      .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
 -      .clk_bypass     = &sys_clkin_ck,
 -      .clk_ref        = &sys_clkin_ck,
 -      .control_reg    = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
 -      .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 -      .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
 -      .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_UNIPRO,
 -      .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 -      .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 -      .enable_mask    = OMAP4430_DPLL_EN_MASK,
 -      .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 -      .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 -      .sddiv_mask     = OMAP4430_DPLL_SD_DIV_MASK,
 -      .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 -      .max_divider    = OMAP4430_MAX_DPLL_DIV,
 -      .min_divider    = 1,
 -};
 -
 -
 -static struct clk dpll_unipro_ck = {
 -      .name           = "dpll_unipro_ck",
 -      .parent         = &sys_clkin_ck,
 -      .dpll_data      = &dpll_unipro_dd,
 -      .init           = &omap2_init_dpll_parent,
 -      .ops            = &clkops_omap3_noncore_dpll_ops,
 -      .recalc         = &omap3_dpll_recalc,
 -      .round_rate     = &omap2_dpll_round_rate,
 -      .set_rate       = &omap3_noncore_dpll_set_rate,
 -};
 -
 -static struct clk dpll_unipro_x2_ck = {
 -      .name           = "dpll_unipro_x2_ck",
 -      .parent         = &dpll_unipro_ck,
 -      .flags          = CLOCK_CLKOUTX2,
 -      .ops            = &clkops_null,
 -      .recalc         = &omap3_clkoutx2_recalc,
 -};
 -
 -static const struct clksel dpll_unipro_m2x2_div[] = {
 -      { .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates },
 -      { .parent = NULL },
 -};
 -
 -static struct clk dpll_unipro_m2x2_ck = {
 -      .name           = "dpll_unipro_m2x2_ck",
 -      .parent         = &dpll_unipro_x2_ck,
 -      .clksel         = dpll_unipro_m2x2_div,
 -      .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
 -      .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 -      .ops            = &clkops_omap4_dpllmx_ops,
 -      .recalc         = &omap2_clksel_recalc,
 -      .round_rate     = &omap2_clksel_round_rate,
 -      .set_rate       = &omap2_clksel_set_rate,
 -};
 -
  static struct clk usb_hs_clk_div_ck = {
        .name           = "usb_hs_clk_div_ck",
        .parent         = &dpll_abe_m3x2_ck,
@@@ -958,9 -1015,8 +958,9 @@@ static struct dpll_data dpll_usb_dd = 
        .enable_mask    = OMAP4430_DPLL_EN_MASK,
        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 -      .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 -      .max_divider    = OMAP4430_MAX_DPLL_DIV,
 +      .sddiv_mask     = OMAP4430_DPLL_SD_DIV_MASK,
 +      .max_multiplier = 4095,
 +      .max_divider    = 256,
        .min_divider    = 1,
  };
  
@@@ -979,8 -1035,8 +979,8 @@@ static struct clk dpll_usb_ck = 
  static struct clk dpll_usb_clkdcoldo_ck = {
        .name           = "dpll_usb_clkdcoldo_ck",
        .parent         = &dpll_usb_ck,
 -      .ops            = &clkops_omap4_dpllmx_ops,
        .clksel_reg     = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
 +      .ops            = &clkops_omap4_dpllmx_ops,
        .recalc         = &followparent_recalc,
  };
  
@@@ -1113,6 -1169,19 +1113,6 @@@ static struct clk func_96m_fclk = 
        .set_rate       = &omap2_clksel_set_rate,
  };
  
 -static const struct clksel hsmmc6_fclk_sel[] = {
 -      { .parent = &func_64m_fclk, .rates = div_1_0_rates },
 -      { .parent = &func_96m_fclk, .rates = div_1_1_rates },
 -      { .parent = NULL },
 -};
 -
 -static struct clk hsmmc6_fclk = {
 -      .name           = "hsmmc6_fclk",
 -      .parent         = &func_64m_fclk,
 -      .ops            = &clkops_null,
 -      .recalc         = &followparent_recalc,
 -};
 -
  static const struct clksel_rate div2_1to8_rates[] = {
        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
        { .div = 8, .val = 1, .flags = RATE_IN_4430 },
@@@ -1195,21 -1264,6 +1195,21 @@@ static struct clk l4_wkup_clk_mux_ck = 
        .recalc         = &omap2_clksel_recalc,
  };
  
 +static struct clk ocp_abe_iclk = {
 +      .name           = "ocp_abe_iclk",
 +      .parent         = &aess_fclk,
 +      .ops            = &clkops_null,
 +      .recalc         = &followparent_recalc,
 +};
 +
 +static struct clk per_abe_24m_fclk = {
 +      .name           = "per_abe_24m_fclk",
 +      .parent         = &dpll_abe_m2_ck,
 +      .ops            = &clkops_null,
 +      .fixed_div      = 4,
 +      .recalc         = &omap_fixed_divisor_recalc,
 +};
 +
  static const struct clksel per_abe_nc_fclk_div[] = {
        { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
        { .parent = NULL },
@@@ -1227,6 -1281,41 +1227,6 @@@ static struct clk per_abe_nc_fclk = 
        .set_rate       = &omap2_clksel_set_rate,
  };
  
 -static const struct clksel mcasp2_fclk_sel[] = {
 -      { .parent = &func_96m_fclk, .rates = div_1_0_rates },
 -      { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
 -      { .parent = NULL },
 -};
 -
 -static struct clk mcasp2_fclk = {
 -      .name           = "mcasp2_fclk",
 -      .parent         = &func_96m_fclk,
 -      .ops            = &clkops_null,
 -      .recalc         = &followparent_recalc,
 -};
 -
 -static struct clk mcasp3_fclk = {
 -      .name           = "mcasp3_fclk",
 -      .parent         = &func_96m_fclk,
 -      .ops            = &clkops_null,
 -      .recalc         = &followparent_recalc,
 -};
 -
 -static struct clk ocp_abe_iclk = {
 -      .name           = "ocp_abe_iclk",
 -      .parent         = &aess_fclk,
 -      .ops            = &clkops_null,
 -      .recalc         = &followparent_recalc,
 -};
 -
 -static struct clk per_abe_24m_fclk = {
 -      .name           = "per_abe_24m_fclk",
 -      .parent         = &dpll_abe_m2_ck,
 -      .ops            = &clkops_null,
 -      .fixed_div      = 4,
 -      .recalc         = &omap_fixed_divisor_recalc,
 -};
 -
  static const struct clksel pmd_stm_clock_mux_sel[] = {
        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
        { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
@@@ -1397,6 -1486,40 +1397,40 @@@ static struct clk dss_dss_clk = 
        .recalc         = &followparent_recalc,
  };
  
+ static const struct clksel_rate div3_8to32_rates[] = {
+       { .div = 8, .val = 0, .flags = RATE_IN_44XX },
+       { .div = 16, .val = 1, .flags = RATE_IN_44XX },
+       { .div = 32, .val = 2, .flags = RATE_IN_44XX },
+       { .div = 0 },
+ };
+ static const struct clksel div_ts_div[] = {
+       { .parent = &l4_wkup_clk_mux_ck, .rates = div3_8to32_rates },
+       { .parent = NULL },
+ };
+ static struct clk div_ts_ck = {
+       .name           = "div_ts_ck",
+       .parent         = &l4_wkup_clk_mux_ck,
+       .clksel         = div_ts_div,
+       .clksel_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
+       .clksel_mask    = OMAP4430_CLKSEL_24_25_MASK,
+       .ops            = &clkops_null,
+       .recalc         = &omap2_clksel_recalc,
+       .round_rate     = &omap2_clksel_round_rate,
+       .set_rate       = &omap2_clksel_set_rate,
+ };
+ static struct clk bandgap_ts_fclk = {
+       .name           = "bandgap_ts_fclk",
+       .ops            = &clkops_omap2_dflt,
+       .enable_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
+       .enable_bit     = OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
+       .clkdm_name     = "l4_wkup_clkdm",
+       .parent         = &div_ts_ck,
+       .recalc         = &followparent_recalc,
+ };
  static struct clk dss_48mhz_clk = {
        .name           = "dss_48mhz_clk",
        .ops            = &clkops_omap2_dflt,
@@@ -1757,8 -1880,8 +1791,8 @@@ static struct clk l3_instr_ick = 
        .ops            = &clkops_omap2_dflt,
        .enable_reg     = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
 -      .clkdm_name     = "l3_instr_clkdm",
        .flags          = ENABLE_ON_INIT,
 +      .clkdm_name     = "l3_instr_clkdm",
        .parent         = &l3_div_ck,
        .recalc         = &followparent_recalc,
  };
@@@ -1768,8 -1891,8 +1802,8 @@@ static struct clk l3_main_3_ick = 
        .ops            = &clkops_omap2_dflt,
        .enable_reg     = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
 -      .clkdm_name     = "l3_instr_clkdm",
        .flags          = ENABLE_ON_INIT,
 +      .clkdm_name     = "l3_instr_clkdm",
        .parent         = &l3_div_ck,
        .recalc         = &followparent_recalc,
  };
@@@ -1906,16 -2029,10 +1940,16 @@@ static struct clk mcbsp3_fck = 
        .clkdm_name     = "abe_clkdm",
  };
  
 +static const struct clksel mcbsp4_sync_mux_sel[] = {
 +      { .parent = &func_96m_fclk, .rates = div_1_0_rates },
 +      { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
 +      { .parent = NULL },
 +};
 +
  static struct clk mcbsp4_sync_mux_ck = {
        .name           = "mcbsp4_sync_mux_ck",
        .parent         = &func_96m_fclk,
 -      .clksel         = mcasp2_fclk_sel,
 +      .clksel         = mcbsp4_sync_mux_sel,
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
        .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
@@@ -1994,17 -2111,11 +2028,17 @@@ static struct clk mcspi4_fck = 
        .recalc         = &followparent_recalc,
  };
  
 +static const struct clksel hsmmc1_fclk_sel[] = {
 +      { .parent = &func_64m_fclk, .rates = div_1_0_rates },
 +      { .parent = &func_96m_fclk, .rates = div_1_1_rates },
 +      { .parent = NULL },
 +};
 +
  /* Merged hsmmc1_fclk into mmc1 */
  static struct clk mmc1_fck = {
        .name           = "mmc1_fck",
        .parent         = &func_64m_fclk,
 -      .clksel         = hsmmc6_fclk_sel,
 +      .clksel         = hsmmc1_fclk_sel,
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
        .clksel_mask    = OMAP4430_CLKSEL_MASK,
  static struct clk mmc2_fck = {
        .name           = "mmc2_fck",
        .parent         = &func_64m_fclk,
 -      .clksel         = hsmmc6_fclk_sel,
 +      .clksel         = hsmmc1_fclk_sel,
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
        .clksel_mask    = OMAP4430_CLKSEL_MASK,
@@@ -2085,8 -2196,8 +2119,8 @@@ static struct clk ocp_wp_noc_ick = 
        .ops            = &clkops_omap2_dflt,
        .enable_reg     = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
 -      .clkdm_name     = "l3_instr_clkdm",
        .flags          = ENABLE_ON_INIT,
 +      .clkdm_name     = "l3_instr_clkdm",
        .parent         = &l3_div_ck,
        .recalc         = &followparent_recalc,
  };
@@@ -2818,7 -2929,6 +2852,7 @@@ static struct clk auxclk2_ck = 
        .enable_reg     = OMAP4_SCRM_AUXCLK2,
        .enable_bit     = OMAP4_ENABLE_SHIFT,
  };
 +
  static struct clk auxclk3_ck = {
        .name           = "auxclk3_ck",
        .parent         = &sys_clkin_ck,
@@@ -3001,6 -3111,9 +3035,6 @@@ static struct omap_clk omap44xx_clks[] 
        CLK(NULL,       "dpll_per_m5x2_ck",             &dpll_per_m5x2_ck,      CK_443X),
        CLK(NULL,       "dpll_per_m6x2_ck",             &dpll_per_m6x2_ck,      CK_443X),
        CLK(NULL,       "dpll_per_m7x2_ck",             &dpll_per_m7x2_ck,      CK_443X),
 -      CLK(NULL,       "dpll_unipro_ck",               &dpll_unipro_ck,        CK_443X),
 -      CLK(NULL,       "dpll_unipro_x2_ck",            &dpll_unipro_x2_ck,     CK_443X),
 -      CLK(NULL,       "dpll_unipro_m2x2_ck",          &dpll_unipro_m2x2_ck,   CK_443X),
        CLK(NULL,       "usb_hs_clk_div_ck",            &usb_hs_clk_div_ck,     CK_443X),
        CLK(NULL,       "dpll_usb_ck",                  &dpll_usb_ck,   CK_443X),
        CLK(NULL,       "dpll_usb_clkdcoldo_ck",        &dpll_usb_clkdcoldo_ck, CK_443X),
        CLK(NULL,       "func_48mc_fclk",               &func_48mc_fclk,        CK_443X),
        CLK(NULL,       "func_64m_fclk",                &func_64m_fclk, CK_443X),
        CLK(NULL,       "func_96m_fclk",                &func_96m_fclk, CK_443X),
 -      CLK(NULL,       "hsmmc6_fclk",                  &hsmmc6_fclk,   CK_443X),
        CLK(NULL,       "init_60m_fclk",                &init_60m_fclk, CK_443X),
        CLK(NULL,       "l3_div_ck",                    &l3_div_ck,     CK_443X),
        CLK(NULL,       "l4_div_ck",                    &l4_div_ck,     CK_443X),
        CLK(NULL,       "lp_clk_div_ck",                &lp_clk_div_ck, CK_443X),
        CLK(NULL,       "l4_wkup_clk_mux_ck",           &l4_wkup_clk_mux_ck,    CK_443X),
 -      CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk,       CK_443X),
 -      CLK(NULL,       "mcasp2_fclk",                  &mcasp2_fclk,   CK_443X),
 -      CLK(NULL,       "mcasp3_fclk",                  &mcasp3_fclk,   CK_443X),
        CLK(NULL,       "ocp_abe_iclk",                 &ocp_abe_iclk,  CK_443X),
        CLK(NULL,       "per_abe_24m_fclk",             &per_abe_24m_fclk,      CK_443X),
 +      CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk,       CK_443X),
        CLK(NULL,       "pmd_stm_clock_mux_ck",         &pmd_stm_clock_mux_ck,  CK_443X),
        CLK(NULL,       "pmd_trace_clk_mux_ck",         &pmd_trace_clk_mux_ck,  CK_443X),
        CLK(NULL,       "syc_clk_div_ck",               &syc_clk_div_ck,        CK_443X),
        CLK(NULL,       "aes2_fck",                     &aes2_fck,      CK_443X),
        CLK(NULL,       "aess_fck",                     &aess_fck,      CK_443X),
        CLK(NULL,       "bandgap_fclk",                 &bandgap_fclk,  CK_443X),
+       CLK(NULL,       "bandgap_ts_fclk",              &bandgap_ts_fclk,       CK_446X),
        CLK(NULL,       "des3des_fck",                  &des3des_fck,   CK_443X),
+       CLK(NULL,       "div_ts_ck",                    &div_ts_ck,     CK_446X),
        CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck,      CK_443X),
        CLK(NULL,       "dmic_fck",                     &dmic_fck,      CK_443X),
        CLK(NULL,       "dsp_fck",                      &dsp_fck,       CK_443X),
        CLK(NULL,       "uart2_fck",                    &uart2_fck,     CK_443X),
        CLK(NULL,       "uart3_fck",                    &uart3_fck,     CK_443X),
        CLK(NULL,       "uart4_fck",                    &uart4_fck,     CK_443X),
 -      CLK(NULL,       "usb_host_fs_fck",              &usb_host_fs_fck,       CK_443X),
        CLK("usbhs-omap.0",     "fs_fck",               &usb_host_fs_fck,       CK_443X),
        CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk, CK_443X),
        CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk,       CK_443X),
        CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk,    CK_443X),
        CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk,   CK_443X),
        CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk,        CK_443X),
 -      CLK(NULL,       "usb_host_hs_fck",              &usb_host_hs_fck,       CK_443X),
        CLK("usbhs-omap.0",     "hs_fck",               &usb_host_hs_fck,       CK_443X),
 -      CLK("usbhs-omap.0",     "usbhost_ick",          &dummy_ck,              CK_443X),
        CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk, CK_443X),
        CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk,       CK_443X),
        CLK("musb-omap2430",    "ick",                          &usb_otg_hs_ick,        CK_443X),
        CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk,        CK_443X),
        CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk,        CK_443X),
        CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk,        CK_443X),
 -      CLK(NULL,       "usb_tll_hs_ick",               &usb_tll_hs_ick,        CK_443X),
        CLK("usbhs-omap.0",     "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
 -      CLK("usbhs-omap.0",     "usbtll_fck",           &dummy_ck,      CK_443X),
        CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
        CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
        CLK(NULL,       "usim_fck",                     &usim_fck,      CK_443X),
        CLK("omap_wdt", "fck",                          &wd_timer2_fck, CK_443X),
 -      CLK(NULL,       "mailboxes_ick",                &dummy_ck,      CK_443X),
        CLK(NULL,       "wd_timer3_fck",                &wd_timer3_fck, CK_443X),
        CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck,        CK_443X),
        CLK(NULL,       "trace_clk_div_ck",             &trace_clk_div_ck,      CK_443X),
 +      CLK(NULL,       "auxclk0_ck",                   &auxclk0_ck,    CK_443X),
 +      CLK(NULL,       "auxclk1_ck",                   &auxclk1_ck,    CK_443X),
 +      CLK(NULL,       "auxclk2_ck",                   &auxclk2_ck,    CK_443X),
 +      CLK(NULL,       "auxclk3_ck",                   &auxclk3_ck,    CK_443X),
 +      CLK(NULL,       "auxclk4_ck",                   &auxclk4_ck,    CK_443X),
 +      CLK(NULL,       "auxclk5_ck",                   &auxclk5_ck,    CK_443X),
 +      CLK(NULL,       "auxclkreq0_ck",                &auxclkreq0_ck, CK_443X),
 +      CLK(NULL,       "auxclkreq1_ck",                &auxclkreq1_ck, CK_443X),
 +      CLK(NULL,       "auxclkreq2_ck",                &auxclkreq2_ck, CK_443X),
 +      CLK(NULL,       "auxclkreq3_ck",                &auxclkreq3_ck, CK_443X),
 +      CLK(NULL,       "auxclkreq4_ck",                &auxclkreq4_ck, CK_443X),
 +      CLK(NULL,       "auxclkreq5_ck",                &auxclkreq5_ck, CK_443X),
        CLK(NULL,       "gpmc_ck",                      &dummy_ck,      CK_443X),
        CLK(NULL,       "gpt1_ick",                     &dummy_ck,      CK_443X),
        CLK(NULL,       "gpt2_ick",                     &dummy_ck,      CK_443X),
        CLK("omap_i2c.2",       "ick",                          &dummy_ck,      CK_443X),
        CLK("omap_i2c.3",       "ick",                          &dummy_ck,      CK_443X),
        CLK("omap_i2c.4",       "ick",                          &dummy_ck,      CK_443X),
 +      CLK(NULL,       "mailboxes_ick",                &dummy_ck,      CK_443X),
        CLK("omap_hsmmc.0",     "ick",                          &dummy_ck,      CK_443X),
        CLK("omap_hsmmc.1",     "ick",                          &dummy_ck,      CK_443X),
        CLK("omap_hsmmc.2",     "ick",                          &dummy_ck,      CK_443X),
        CLK(NULL,       "uart2_ick",                    &dummy_ck,      CK_443X),
        CLK(NULL,       "uart3_ick",                    &dummy_ck,      CK_443X),
        CLK(NULL,       "uart4_ick",                    &dummy_ck,      CK_443X),
 +      CLK("usbhs-omap.0",     "usbhost_ick",          &dummy_ck,              CK_443X),
 +      CLK("usbhs-omap.0",     "usbtll_fck",           &dummy_ck,      CK_443X),
        CLK("omap_wdt", "ick",                          &dummy_ck,      CK_443X),
 -      CLK(NULL,       "auxclk0_ck",                   &auxclk0_ck,    CK_443X),
 -      CLK(NULL,       "auxclk1_ck",                   &auxclk1_ck,    CK_443X),
 -      CLK(NULL,       "auxclk2_ck",                   &auxclk2_ck,    CK_443X),
 -      CLK(NULL,       "auxclk3_ck",                   &auxclk3_ck,    CK_443X),
 -      CLK(NULL,       "auxclk4_ck",                   &auxclk4_ck,    CK_443X),
 -      CLK(NULL,       "auxclk5_ck",                   &auxclk5_ck,    CK_443X),
 -      CLK(NULL,       "auxclkreq0_ck",                &auxclkreq0_ck, CK_443X),
 -      CLK(NULL,       "auxclkreq1_ck",                &auxclkreq1_ck, CK_443X),
 -      CLK(NULL,       "auxclkreq2_ck",                &auxclkreq2_ck, CK_443X),
 -      CLK(NULL,       "auxclkreq3_ck",                &auxclkreq3_ck, CK_443X),
 -      CLK(NULL,       "auxclkreq4_ck",                &auxclkreq4_ck, CK_443X),
 -      CLK(NULL,       "auxclkreq5_ck",                &auxclkreq5_ck, CK_443X),
  };
  
  int __init omap4xxx_clk_init(void)
        if (cpu_is_omap44xx()) {
                cpu_mask = RATE_IN_4430;
                cpu_clkflg = CK_443X;
+       } else if (cpu_is_omap446x()) {
+               cpu_mask = RATE_IN_4460;
+               cpu_clkflg = CK_446X;
        }
  
        clk_init(&omap2_clk_functions);
index 0e77945d26ec8c7a84fffc28869dee87f8797b8f,28e20d3a9f77a6e98828bef4f45e37a88eb65dc5..65597a7456381ce61c59e18af61dce641b05ed07
  #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
  #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
  
 -/*
 - * Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP,
 - * CM_TESLA_DYNAMICDEP
 - */
 +/* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
  #define OMAP4430_ABE_DYNDEP_SHIFT                             3
  #define OMAP4430_ABE_DYNDEP_MASK                              (1 << 3)
  
  /*
 - * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
 - * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
 - * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
 + * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
 + * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
   */
  #define OMAP4430_ABE_STATDEP_SHIFT                            3
  #define OMAP4430_ABE_STATDEP_MASK                             (1 << 3)
  
 -/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
 +/* Used by CM_L4CFG_DYNAMICDEP */
  #define OMAP4430_ALWONCORE_DYNDEP_SHIFT                               16
  #define OMAP4430_ALWONCORE_DYNDEP_MASK                                (1 << 16)
  
  
  /*
   * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE,
 - * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_DDRPHY,
 - * CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER,
 - * CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
 + * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU,
 + * CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
   */
  #define OMAP4430_AUTO_DPLL_MODE_SHIFT                         0
  #define OMAP4430_AUTO_DPLL_MODE_MASK                          (0x7 << 0)
  
 -/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
 +/* Used by CM_L4CFG_DYNAMICDEP */
  #define OMAP4430_CEFUSE_DYNDEP_SHIFT                          17
  #define OMAP4430_CEFUSE_DYNDEP_MASK                           (1 << 17)
  
  #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT                 8
  #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK                  (1 << 8)
  
 -/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
 +/* Used by CM_MEMIF_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT              11
  #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK                       (1 << 11)
  
 -/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
 +/* Used by CM_MEMIF_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT             12
  #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK              (1 << 12)
  
 -/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
 +/* Used by CM_MEMIF_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT             13
  #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK              (1 << 13)
  
  #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT          9
  #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK           (1 << 9)
  
+ /* Used by CM_L4CFG_CLKSTCTRL */
+ #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_SHIFT              9
+ #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_MASK                       (1 << 9)
  /* Used by CM_CEFUSE_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT         9
  #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK          (1 << 9)
  
 -/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
 +/* Used by CM_MEMIF_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT                    9
  #define OMAP4430_CLKACTIVITY_DLL_CLK_MASK                     (1 << 9)
  
 -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 +/* Used by CM_L4PER_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT                        9
  #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK                 (1 << 9)
  
 -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 +/* Used by CM_L4PER_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT                        10
  #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK                 (1 << 10)
  
 -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 +/* Used by CM_L4PER_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT                 11
  #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK                  (1 << 11)
  
 -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 +/* Used by CM_L4PER_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT                 12
  #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK                  (1 << 12)
  
 -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 +/* Used by CM_L4PER_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT                 13
  #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK                  (1 << 13)
  
 -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 +/* Used by CM_L4PER_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT                 14
  #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK                  (1 << 14)
  
  #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT                 10
  #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK                  (1 << 10)
  
 -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 +/* Used by CM_L4PER_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT             15
  #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK              (1 << 15)
  
  #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT               11
  #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK                (1 << 11)
  
 -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 +/* Used by CM_L3INIT_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT         20
  #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK          (1 << 20)
  
 -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 +/* Used by CM_L3INIT_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT              26
  #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK                       (1 << 26)
  
 -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 +/* Used by CM_L3INIT_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT         21
  #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK          (1 << 21)
  
 -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 +/* Used by CM_L3INIT_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT              27
  #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK                       (1 << 27)
  
 -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 +/* Used by CM_L3INIT_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT            13
  #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK             (1 << 13)
  
 -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 +/* Used by CM_L3INIT_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT             12
  #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK              (1 << 12)
  
 -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 +/* Used by CM_L3INIT_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT          28
  #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK           (1 << 28)
  
 -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 +/* Used by CM_L3INIT_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT          29
  #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK           (1 << 29)
  
 -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 +/* Used by CM_L3INIT_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT             11
  #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK              (1 << 11)
  
 -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 +/* Used by CM_L3INIT_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT             16
  #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK              (1 << 16)
  
 -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 +/* Used by CM_L3INIT_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT          17
  #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK           (1 << 17)
  
 -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 +/* Used by CM_L3INIT_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT          18
  #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK           (1 << 18)
  
 -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 +/* Used by CM_L3INIT_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT          19
  #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK           (1 << 19)
  
  #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT             10
  #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK              (1 << 10)
  
 -/* Used by CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE */
 +/* Used by CM_L3_1_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT                 8
  #define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK                  (1 << 8)
  
 -/* Used by CM_L3_2_CLKSTCTRL, CM_L3_2_CLKSTCTRL_RESTORE */
 +/* Used by CM_L3_2_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT                 8
  #define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK                  (1 << 8)
  
  #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT                       8
  #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK                        (1 << 8)
  
 -/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
 +/* Used by CM_MEMIF_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT              8
  #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK                       (1 << 8)
  
  #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT                       8
  #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK                        (1 << 8)
  
 -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 +/* Used by CM_L3INIT_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT              8
  #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK                       (1 << 8)
  
  #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT            8
  #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK             (1 << 8)
  
 -/* Used by CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE */
 +/* Used by CM_L4CFG_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT                       8
  #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK                        (1 << 8)
  
  #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT                       9
  #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK                        (1 << 9)
  
 -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 +/* Used by CM_L3INIT_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT              9
  #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK                       (1 << 9)
  
 -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 +/* Used by CM_L4PER_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT                       8
  #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK                        (1 << 8)
  
  #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT              12
  #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK                       (1 << 12)
  
 -/* Used by CM_MPU_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */
 +/* Used by CM_MPU_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT                       8
  #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK                        (1 << 8)
  
  #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT              9
  #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK                       (1 << 9)
  
 -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 +/* Used by CM_L4PER_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT             16
  #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK              (1 << 16)
  
 -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 +/* Used by CM_L4PER_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT              17
  #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK                       (1 << 17)
  
 -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 +/* Used by CM_L4PER_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT              18
  #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK                       (1 << 18)
  
 -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 +/* Used by CM_L4PER_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT              19
  #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK                       (1 << 19)
  
 -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 +/* Used by CM_L4PER_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT          25
  #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK           (1 << 25)
  
 -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 +/* Used by CM_L4PER_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT           20
  #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK            (1 << 20)
  
 -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 +/* Used by CM_L4PER_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT           21
  #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK            (1 << 21)
  
 -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 +/* Used by CM_L4PER_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT           22
  #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK            (1 << 22)
  
 -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 +/* Used by CM_L4PER_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT              24
  #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK                       (1 << 24)
  
 -/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
 +/* Used by CM_MEMIF_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT                       10
  #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK                        (1 << 10)
  
  #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT             8
  #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK              (1 << 8)
  
 -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 +/* Used by CM_L3INIT_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT              22
  #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK                       (1 << 22)
  
 -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 +/* Used by CM_L3INIT_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT              23
  #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK                       (1 << 23)
  
 -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 +/* Used by CM_L3INIT_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT              24
  #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK                       (1 << 24)
  
 -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 +/* Used by CM_L3INIT_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT            10
  #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK             (1 << 10)
  
 -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 +/* Used by CM_L3INIT_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT                       14
  #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK                        (1 << 14)
  
 -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 +/* Used by CM_L3INIT_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT            15
  #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK             (1 << 15)
  
  #define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT                 10
  #define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK                  (1 << 10)
  
 -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 +/* Used by CM_L3INIT_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT              30
  #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK                       (1 << 30)
  
 -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 +/* Used by CM_L3INIT_CLKSTCTRL */
  #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT            25
  #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK             (1 << 25)
  
  #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT             11
  #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK              (1 << 11)
  
+ /* Used by CM_WKUP_CLKSTCTRL */
+ #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_SHIFT              13
+ #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_MASK                       (1 << 13)
  /*
   * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL,
   * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
  
  /*
   * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL,
 - * CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ
 + * CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ, CM_L4_WKUP_CLKSEL
   */
  #define OMAP4430_CLKSEL_0_0_SHIFT                             0
  #define OMAP4430_CLKSEL_0_0_MASK                              (1 << 0)
  #define OMAP4430_CLKSEL_60M_SHIFT                             24
  #define OMAP4430_CLKSEL_60M_MASK                              (1 << 24)
  
+ /* Used by CM_MPU_MPU_CLKCTRL */
+ #define OMAP4460_CLKSEL_ABE_DIV_MODE_SHIFT                    25
+ #define OMAP4460_CLKSEL_ABE_DIV_MODE_MASK                     (1 << 25)
  /* Used by CM1_ABE_AESS_CLKCTRL */
  #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT                               24
  #define OMAP4430_CLKSEL_AESS_FCLK_MASK                                (1 << 24)
  
 -/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */
 +/* Used by CM_CLKSEL_CORE */
  #define OMAP4430_CLKSEL_CORE_SHIFT                            0
  #define OMAP4430_CLKSEL_CORE_MASK                             (1 << 0)
  
 -/*
 - * Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2_RESTORE,
 - * CM_SHADOW_FREQ_CONFIG2
 - */
 +/* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */
  #define OMAP4430_CLKSEL_CORE_1_1_SHIFT                                1
  #define OMAP4430_CLKSEL_CORE_1_1_MASK                         (1 << 1)
  
  #define OMAP4430_CLKSEL_DIV_SHIFT                             24
  #define OMAP4430_CLKSEL_DIV_MASK                              (1 << 24)
  
+ /* Used by CM_MPU_MPU_CLKCTRL */
+ #define OMAP4460_CLKSEL_EMIF_DIV_MODE_SHIFT                   24
+ #define OMAP4460_CLKSEL_EMIF_DIV_MODE_MASK                    (1 << 24)
  /* Used by CM_CAM_FDIF_CLKCTRL */
  #define OMAP4430_CLKSEL_FCLK_SHIFT                            24
  #define OMAP4430_CLKSEL_FCLK_MASK                             (0x3 << 24)
  #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT    26
  #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK     (0x3 << 26)
  
 -/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */
 +/* Used by CM_CLKSEL_CORE */
  #define OMAP4430_CLKSEL_L3_SHIFT                              4
  #define OMAP4430_CLKSEL_L3_MASK                                       (1 << 4)
  
 -/*
 - * Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2_RESTORE,
 - * CM_SHADOW_FREQ_CONFIG2
 - */
 +/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
  #define OMAP4430_CLKSEL_L3_SHADOW_SHIFT                               2
  #define OMAP4430_CLKSEL_L3_SHADOW_MASK                                (1 << 2)
  
 -/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */
 +/* Used by CM_CLKSEL_CORE */
  #define OMAP4430_CLKSEL_L4_SHIFT                              8
  #define OMAP4430_CLKSEL_L4_MASK                                       (1 << 8)
  
  #define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT                    24
  #define OMAP4430_CLKSEL_SOURCE_24_24_MASK                     (1 << 24)
  
 -/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 +/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
  #define OMAP4430_CLKSEL_UTMI_P1_SHIFT                         24
  #define OMAP4430_CLKSEL_UTMI_P1_MASK                          (1 << 24)
  
 -/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 +/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
  #define OMAP4430_CLKSEL_UTMI_P2_SHIFT                         25
  #define OMAP4430_CLKSEL_UTMI_P2_MASK                          (1 << 25)
  
   * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL,
   * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL,
   * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL,
 - * CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3INSTR_CLKSTCTRL,
 - * CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE, CM_L3_2_CLKSTCTRL,
 - * CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE,
 - * CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE, CM_L4SEC_CLKSTCTRL,
 - * CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE, CM_MPU_CLKSTCTRL,
 - * CM_MPU_CLKSTCTRL_RESTORE, CM_SDMA_CLKSTCTRL, CM_TESLA_CLKSTCTRL,
 - * CM_WKUP_CLKSTCTRL
 + * CM_L3INIT_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL,
 + * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL,
 + * CM_L4SEC_CLKSTCTRL, CM_MEMIF_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_SDMA_CLKSTCTRL,
 + * CM_TESLA_CLKSTCTRL, CM_WKUP_CLKSTCTRL
   */
  #define OMAP4430_CLKTRCTRL_SHIFT                              0
  #define OMAP4430_CLKTRCTRL_MASK                                       (0x3 << 0)
  #define OMAP4430_CUSTOM_SHIFT                                 6
  #define OMAP4430_CUSTOM_MASK                                  (0x3 << 6)
  
 -/*
 - * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
 - * CM_L4CFG_DYNAMICDEP_RESTORE
 - */
 +/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
  #define OMAP4430_D2D_DYNDEP_SHIFT                             18
  #define OMAP4430_D2D_DYNDEP_MASK                              (1 << 18)
  
  #define OMAP4430_D2D_STATDEP_SHIFT                            18
  #define OMAP4430_D2D_STATDEP_MASK                             (1 << 18)
  
+ /* Used by CM_CLKSEL_DPLL_MPU */
+ #define OMAP4460_DCC_COUNT_MAX_SHIFT                          24
+ #define OMAP4460_DCC_COUNT_MAX_MASK                           (0xff << 24)
+ /* Used by CM_CLKSEL_DPLL_MPU */
+ #define OMAP4460_DCC_EN_SHIFT                                 22
+ #define OMAP4460_DCC_EN_MASK                                  (1 << 22)
  /*
   * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
 - * CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE, CM_SSC_DELTAMSTEP_DPLL_DDRPHY,
 - * CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU,
 - * CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO,
 - * CM_SSC_DELTAMSTEP_DPLL_USB
 + * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA,
 + * CM_SSC_DELTAMSTEP_DPLL_MPU, CM_SSC_DELTAMSTEP_DPLL_PER,
 + * CM_SSC_DELTAMSTEP_DPLL_UNIPRO, CM_SSC_DELTAMSTEP_DPLL_USB
   */
  #define OMAP4430_DELTAMSTEP_SHIFT                             0
  #define OMAP4430_DELTAMSTEP_MASK                              (0xfffff << 0)
  
 -/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
 -#define OMAP4430_DLL_OVERRIDE_SHIFT                           2
 -#define OMAP4430_DLL_OVERRIDE_MASK                            (1 << 2)
+ /* Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_USB */
+ #define OMAP4460_DELTAMSTEP_0_20_SHIFT                                0
+ #define OMAP4460_DELTAMSTEP_0_20_MASK                         (0x1fffff << 0)
 +/* Used by CM_DLL_CTRL */
 +#define OMAP4430_DLL_OVERRIDE_SHIFT                           0
 +#define OMAP4430_DLL_OVERRIDE_MASK                            (1 << 0)
  
 -/* Renamed from DLL_OVERRIDE Used by CM_DLL_CTRL */
 -#define OMAP4430_DLL_OVERRIDE_0_0_SHIFT                               0
 -#define OMAP4430_DLL_OVERRIDE_0_0_MASK                                (1 << 0)
 +/* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */
 +#define OMAP4430_DLL_OVERRIDE_2_2_SHIFT                               2
 +#define OMAP4430_DLL_OVERRIDE_2_2_MASK                                (1 << 2)
  
 -/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
 +/* Used by CM_SHADOW_FREQ_CONFIG1 */
  #define OMAP4430_DLL_RESET_SHIFT                              3
  #define OMAP4430_DLL_RESET_MASK                                       (1 << 3)
  
  /*
 - * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
 - * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA,
 - * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO,
 - * CM_CLKSEL_DPLL_USB
 + * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
 + * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
 + * CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB
   */
  #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT                                23
  #define OMAP4430_DPLL_BYP_CLKSEL_MASK                         (1 << 23)
  #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT                       8
  #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK                        (1 << 8)
  
 -/* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_CORE_RESTORE */
 +/* Used by CM_CLKSEL_DPLL_CORE */
  #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT                  20
  #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK                   (1 << 20)
  
 -/*
 - * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
 - * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
 - */
 +/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
  #define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT                     0
  #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK                      (0x1f << 0)
  
 -/*
 - * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
 - * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
 - */
 +/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
  #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT                        5
  #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK                 (1 << 5)
  
 -/*
 - * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
 - * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
 - */
 +/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
  #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT                       8
  #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK                        (1 << 8)
  
  #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK                 (1 << 10)
  
  /*
 - * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
 - * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
 - * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
 + * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
 + * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
   */
  #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT                                0
  #define OMAP4430_DPLL_CLKOUT_DIV_MASK                         (0x1f << 0)
  #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK                     (0x7f << 0)
  
  /*
 - * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
 - * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
 - * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
 + * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
 + * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
   */
  #define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT                   5
  #define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK                    (1 << 5)
  #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK             (1 << 7)
  
  /*
 - * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
 - * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
 - * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
 + * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
 + * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
   */
  #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT                  8
  #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK                   (1 << 8)
  
 -/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
 +/* Used by CM_SHADOW_FREQ_CONFIG1 */
  #define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT                      8
  #define OMAP4430_DPLL_CORE_DPLL_EN_MASK                               (0x7 << 8)
  
 -/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
 +/* Used by CM_SHADOW_FREQ_CONFIG1 */
  #define OMAP4430_DPLL_CORE_M2_DIV_SHIFT                               11
  #define OMAP4430_DPLL_CORE_M2_DIV_MASK                                (0x1f << 11)
  
 -/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */
 +/* Used by CM_SHADOW_FREQ_CONFIG2 */
  #define OMAP4430_DPLL_CORE_M5_DIV_SHIFT                               3
  #define OMAP4430_DPLL_CORE_M5_DIV_MASK                                (0x1f << 3)
  
  /*
 - * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
 - * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA,
 - * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO
 + * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
 + * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
 + * CM_CLKSEL_DPLL_UNIPRO
   */
  #define OMAP4430_DPLL_DIV_SHIFT                                       0
  #define OMAP4430_DPLL_DIV_MASK                                        (0x7f << 0)
  #define OMAP4430_DPLL_DIV_0_7_MASK                            (0xff << 0)
  
  /*
 - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
 - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
 - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
 + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
 + * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
   */
  #define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT                     8
  #define OMAP4430_DPLL_DRIFTGUARD_EN_MASK                      (1 << 8)
  #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK                  (1 << 3)
  
  /*
 - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
 - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
 - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
 - * CM_CLKMODE_DPLL_USB
 + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
 + * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
 + * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
   */
  #define OMAP4430_DPLL_EN_SHIFT                                        0
  #define OMAP4430_DPLL_EN_MASK                                 (0x7 << 0)
  
  /*
 - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
 - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
 - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO
 + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
 + * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
 + * CM_CLKMODE_DPLL_UNIPRO
   */
  #define OMAP4430_DPLL_LPMODE_EN_SHIFT                         10
  #define OMAP4430_DPLL_LPMODE_EN_MASK                          (1 << 10)
  
  /*
 - * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
 - * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA,
 - * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO
 + * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
 + * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
 + * CM_CLKSEL_DPLL_UNIPRO
   */
  #define OMAP4430_DPLL_MULT_SHIFT                              8
  #define OMAP4430_DPLL_MULT_MASK                                       (0x7ff << 8)
  #define OMAP4430_DPLL_MULT_USB_MASK                           (0xfff << 8)
  
  /*
 - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
 - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
 - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO
 + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
 + * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
 + * CM_CLKMODE_DPLL_UNIPRO
   */
  #define OMAP4430_DPLL_REGM4XEN_SHIFT                          11
  #define OMAP4430_DPLL_REGM4XEN_MASK                           (1 << 11)
  #define OMAP4430_DPLL_SD_DIV_MASK                             (0xff << 24)
  
  /*
 - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
 - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
 - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
 - * CM_CLKMODE_DPLL_USB
 + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
 + * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
 + * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
   */
  #define OMAP4430_DPLL_SSC_ACK_SHIFT                           13
  #define OMAP4430_DPLL_SSC_ACK_MASK                            (1 << 13)
  
  /*
 - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
 - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
 - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
 - * CM_CLKMODE_DPLL_USB
 + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
 + * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
 + * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
   */
  #define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT                    14
  #define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK                     (1 << 14)
  
  /*
 - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
 - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
 - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
 - * CM_CLKMODE_DPLL_USB
 + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
 + * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
 + * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
   */
  #define OMAP4430_DPLL_SSC_EN_SHIFT                            12
  #define OMAP4430_DPLL_SSC_EN_MASK                             (1 << 12)
  
 -/*
 - * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
 - * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE
 - */
 +/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
  #define OMAP4430_DSS_DYNDEP_SHIFT                             8
  #define OMAP4430_DSS_DYNDEP_MASK                              (1 << 8)
  
 -/*
 - * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
 - * CM_SDMA_STATICDEP_RESTORE
 - */
 +/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
  #define OMAP4430_DSS_STATDEP_SHIFT                            8
  #define OMAP4430_DSS_STATDEP_MASK                             (1 << 8)
  
 -/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */
 +/* Used by CM_L3_2_DYNAMICDEP */
  #define OMAP4430_DUCATI_DYNDEP_SHIFT                          0
  #define OMAP4430_DUCATI_DYNDEP_MASK                           (1 << 0)
  
 -/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE */
 +/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
  #define OMAP4430_DUCATI_STATDEP_SHIFT                         0
  #define OMAP4430_DUCATI_STATDEP_MASK                          (1 << 0)
  
 -/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
 +/* Used by CM_SHADOW_FREQ_CONFIG1 */
  #define OMAP4430_FREQ_UPDATE_SHIFT                            0
  #define OMAP4430_FREQ_UPDATE_MASK                             (1 << 0)
  
  #define OMAP4430_FUNC_SHIFT                                   16
  #define OMAP4430_FUNC_MASK                                    (0xfff << 16)
  
 -/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */
 +/* Used by CM_L3_2_DYNAMICDEP */
  #define OMAP4430_GFX_DYNDEP_SHIFT                             10
  #define OMAP4430_GFX_DYNDEP_MASK                              (1 << 10)
  
  #define OMAP4430_GFX_STATDEP_SHIFT                            10
  #define OMAP4430_GFX_STATDEP_MASK                             (1 << 10)
  
 -/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */
 +/* Used by CM_SHADOW_FREQ_CONFIG2 */
  #define OMAP4430_GPMC_FREQ_UPDATE_SHIFT                               0
  #define OMAP4430_GPMC_FREQ_UPDATE_MASK                                (1 << 0)
  
  /*
 - * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
 - * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
 + * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
 + * CM_DIV_M4_DPLL_PER
   */
  #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT                  0
  #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK                   (0x1f << 0)
  
  /*
 - * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
 - * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
 + * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
 + * CM_DIV_M4_DPLL_PER
   */
  #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT             5
  #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK              (1 << 5)
  
  /*
 - * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
 - * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
 + * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
 + * CM_DIV_M4_DPLL_PER
   */
  #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT            8
  #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK             (1 << 8)
  
  /*
 - * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
 - * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
 + * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
 + * CM_DIV_M4_DPLL_PER
   */
  #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT                 12
  #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK                  (1 << 12)
  
  /*
 - * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
 - * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
 + * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
 + * CM_DIV_M5_DPLL_PER
   */
  #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT                  0
  #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK                   (0x1f << 0)
  
  /*
 - * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
 - * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
 + * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
 + * CM_DIV_M5_DPLL_PER
   */
  #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT             5
  #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK              (1 << 5)
  
  /*
 - * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
 - * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
 + * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
 + * CM_DIV_M5_DPLL_PER
   */
  #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT            8
  #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK             (1 << 8)
  
  /*
 - * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
 - * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
 + * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
 + * CM_DIV_M5_DPLL_PER
   */
  #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT                 12
  #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK                  (1 << 12)
  
 -/*
 - * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
 - * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
 - */
 +/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
  #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT                  0
  #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK                   (0x1f << 0)
  
 -/*
 - * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
 - * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
 - */
 +/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
  #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT             5
  #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK              (1 << 5)
  
 -/*
 - * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
 - * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
 - */
 +/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
  #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT            8
  #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK             (1 << 8)
  
 -/*
 - * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
 - * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
 - */
 +/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
  #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT                 12
  #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK                  (1 << 12)
  
 -/*
 - * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
 - * CM_DIV_M7_DPLL_PER
 - */
 +/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
  #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT                  0
  #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK                   (0x1f << 0)
  
 -/*
 - * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
 - * CM_DIV_M7_DPLL_PER
 - */
 +/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
  #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT             5
  #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK              (1 << 5)
  
 -/*
 - * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
 - * CM_DIV_M7_DPLL_PER
 - */
 +/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
  #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT            8
  #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK             (1 << 8)
  
 -/*
 - * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
 - * CM_DIV_M7_DPLL_PER
 - */
 +/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
  #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT                 12
  #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK                  (1 << 12)
  
   * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
   * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
   * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
 - * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE,
 - * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE,
 + * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
   * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
   * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
   * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
   * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
   * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
   * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
 - * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL,
 - * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
 - * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL,
 - * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE,
 - * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
 - * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE,
 + * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
 + * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL,
 + * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL,
   * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
   * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
   * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
   * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
   * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
   * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
 - * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
 - * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE,
 - * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
 - * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
 - * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
 - * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL,
 - * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
 - * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
 - * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL,
 - * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
 - * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
 - * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
 + * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
 + * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
 + * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL,
 + * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL,
 + * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL,
 + * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL,
 + * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL,
 + * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL,
 + * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
   * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
   * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
   * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
  #define OMAP4430_IDLEST_SHIFT                                 16
  #define OMAP4430_IDLEST_MASK                                  (0x3 << 16)
  
 -/*
 - * Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
 - * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE
 - */
 +/* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
  #define OMAP4430_ISS_DYNDEP_SHIFT                             9
  #define OMAP4430_ISS_DYNDEP_MASK                              (1 << 9)
  
  /*
   * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
 - * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
 + * CM_TESLA_STATICDEP
   */
  #define OMAP4430_ISS_STATDEP_SHIFT                            9
  #define OMAP4430_ISS_STATDEP_MASK                             (1 << 9)
  
 -/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_TESLA_DYNAMICDEP */
 +/* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
  #define OMAP4430_IVAHD_DYNDEP_SHIFT                           2
  #define OMAP4430_IVAHD_DYNDEP_MASK                            (1 << 2)
  
  /*
 - * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
 - * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP,
 - * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
 - * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
 + * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
 + * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_L3INIT_STATICDEP,
 + * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
   */
  #define OMAP4430_IVAHD_STATDEP_SHIFT                          2
  #define OMAP4430_IVAHD_STATDEP_MASK                           (1 << 2)
  
 -/*
 - * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
 - * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE
 - */
 +/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
  #define OMAP4430_L3INIT_DYNDEP_SHIFT                          7
  #define OMAP4430_L3INIT_DYNDEP_MASK                           (1 << 7)
  
  /*
 - * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
 - * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
 - * CM_TESLA_STATICDEP
 + * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_MPU_STATICDEP,
 + * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
   */
  #define OMAP4430_L3INIT_STATDEP_SHIFT                         7
  #define OMAP4430_L3INIT_STATDEP_MASK                          (1 << 7)
  
  /*
   * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
 - * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
 - * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
 + * CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
   */
  #define OMAP4430_L3_1_DYNDEP_SHIFT                            5
  #define OMAP4430_L3_1_DYNDEP_MASK                             (1 << 5)
  
  /*
 - * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
 - * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
 + * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
 + * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
   * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
 - * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
 + * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
   */
  #define OMAP4430_L3_1_STATDEP_SHIFT                           5
  #define OMAP4430_L3_1_STATDEP_MASK                            (1 << 5)
  
  /*
 - * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE,
 - * CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP,
 - * CM_IVAHD_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP,
 - * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
 - * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
 + * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP,
 + * CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP, CM_IVAHD_DYNAMICDEP,
 + * CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
 + * CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
   */
  #define OMAP4430_L3_2_DYNDEP_SHIFT                            6
  #define OMAP4430_L3_2_DYNDEP_MASK                             (1 << 6)
  
  /*
 - * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
 - * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
 + * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
 + * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
   * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
 - * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
 + * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
   */
  #define OMAP4430_L3_2_STATDEP_SHIFT                           6
  #define OMAP4430_L3_2_STATDEP_MASK                            (1 << 6)
  
 -/* Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE */
 +/* Used by CM_L3_1_DYNAMICDEP */
  #define OMAP4430_L4CFG_DYNDEP_SHIFT                           12
  #define OMAP4430_L4CFG_DYNDEP_MASK                            (1 << 12)
  
  /*
 - * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
 - * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
 - * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
 + * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
 + * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
   */
  #define OMAP4430_L4CFG_STATDEP_SHIFT                          12
  #define OMAP4430_L4CFG_STATDEP_MASK                           (1 << 12)
  
 -/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */
 +/* Used by CM_L3_2_DYNAMICDEP */
  #define OMAP4430_L4PER_DYNDEP_SHIFT                           13
  #define OMAP4430_L4PER_DYNDEP_MASK                            (1 << 13)
  
  /*
 - * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
 - * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
 - * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
 + * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
 + * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
   */
  #define OMAP4430_L4PER_STATDEP_SHIFT                          13
  #define OMAP4430_L4PER_STATDEP_MASK                           (1 << 13)
  
 -/*
 - * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP,
 - * CM_L4PER_DYNAMICDEP_RESTORE
 - */
 +/* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
  #define OMAP4430_L4SEC_DYNDEP_SHIFT                           14
  #define OMAP4430_L4SEC_DYNDEP_MASK                            (1 << 14)
  
  /*
   * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
 - * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE
 + * CM_SDMA_STATICDEP
   */
  #define OMAP4430_L4SEC_STATDEP_SHIFT                          14
  #define OMAP4430_L4SEC_STATDEP_MASK                           (1 << 14)
  
 -/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
 +/* Used by CM_L4CFG_DYNAMICDEP */
  #define OMAP4430_L4WKUP_DYNDEP_SHIFT                          15
  #define OMAP4430_L4WKUP_DYNDEP_MASK                           (1 << 15)
  
  /*
   * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
 - * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
 + * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
   */
  #define OMAP4430_L4WKUP_STATDEP_SHIFT                         15
  #define OMAP4430_L4WKUP_STATDEP_MASK                          (1 << 15)
  
  /*
 - * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_L3_1_DYNAMICDEP,
 - * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
 - * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP
 + * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
 + * CM_MPU_DYNAMICDEP
   */
  #define OMAP4430_MEMIF_DYNDEP_SHIFT                           4
  #define OMAP4430_MEMIF_DYNDEP_MASK                            (1 << 4)
  
  /*
 - * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
 - * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
 + * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
 + * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
   * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
 - * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
 + * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
   */
  #define OMAP4430_MEMIF_STATDEP_SHIFT                          4
  #define OMAP4430_MEMIF_STATDEP_MASK                           (1 << 4)
  
  /*
   * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
 - * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY,
 - * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
 - * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
 - * CM_SSC_MODFREQDIV_DPLL_USB
 + * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
 + * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER,
 + * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
   */
  #define OMAP4430_MODFREQDIV_EXPONENT_SHIFT                    8
  #define OMAP4430_MODFREQDIV_EXPONENT_MASK                     (0x7 << 8)
  
  /*
   * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
 - * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY,
 - * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
 - * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
 - * CM_SSC_MODFREQDIV_DPLL_USB
 + * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
 + * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER,
 + * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
   */
  #define OMAP4430_MODFREQDIV_MANTISSA_SHIFT                    0
  #define OMAP4430_MODFREQDIV_MANTISSA_MASK                     (0x7f << 0)
   * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
   * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
   * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
 - * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE,
 - * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE,
 + * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
   * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
   * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
   * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
   * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
   * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
   * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
 - * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL,
 - * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
 - * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL,
 - * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE,
 - * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
 - * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE,
 + * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
 + * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL,
 + * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL,
   * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
   * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
   * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
   * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
   * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
   * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
 - * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
 - * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE,
 - * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
 - * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
 - * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
 - * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL,
 - * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
 - * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
 - * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL,
 - * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
 - * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
 - * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
 + * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
 + * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
 + * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL,
 + * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL,
 + * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL,
 + * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL,
 + * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL,
 + * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL,
 + * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
   * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
   * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
   * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
  #define OMAP4430_MODULEMODE_SHIFT                             0
  #define OMAP4430_MODULEMODE_MASK                              (0x3 << 0)
  
+ /* Used by CM_L4CFG_DYNAMICDEP */
+ #define OMAP4460_MPU_DYNDEP_SHIFT                             19
+ #define OMAP4460_MPU_DYNDEP_MASK                              (1 << 19)
  /* Used by CM_DSS_DSS_CLKCTRL */
  #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT                    9
  #define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK                     (1 << 9)
  #define OMAP4430_OPTFCLKEN_CTRLCLK_MASK                               (1 << 8)
  
  /*
 - * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
 - * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE,
 - * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
 - * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
 - * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, CM_WKUP_GPIO1_CLKCTRL
 + * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL,
 + * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL,
 + * CM_WKUP_GPIO1_CLKCTRL
   */
  #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT                                8
  #define OMAP4430_OPTFCLKEN_DBCLK_MASK                         (1 << 8)
  #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT                                10
  #define OMAP4430_OPTFCLKEN_FCLK2_MASK                         (1 << 10)
  
 -/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 +/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
  #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT                   15
  #define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK                    (1 << 15)
  
 -/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 +/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
  #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT              13
  #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK                       (1 << 13)
  
 -/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 +/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
  #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT              14
  #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK                       (1 << 14)
  
 -/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 +/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
  #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT                       11
  #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK                        (1 << 11)
  
 -/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 +/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
  #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT                       12
  #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK                        (1 << 12)
  
  #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT                      10
  #define OMAP4430_OPTFCLKEN_SYS_CLK_MASK                               (1 << 10)
  
+ /* Used by CM_WKUP_BANDGAP_CLKCTRL */
+ #define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT                      8
+ #define OMAP4460_OPTFCLKEN_TS_FCLK_MASK                               (1 << 8)
  /* Used by CM_DSS_DSS_CLKCTRL */
  #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT                               11
  #define OMAP4430_OPTFCLKEN_TV_CLK_MASK                                (1 << 11)
  #define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT                     8
  #define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK                      (1 << 8)
  
 -/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
 +/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
  #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT                  8
  #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK                   (1 << 8)
  
 -/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
 +/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
  #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT                  9
  #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK                   (1 << 9)
  
 -/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
 +/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
  #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT                  10
  #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK                   (1 << 10)
  
 -/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 +/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
  #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT                  8
  #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK                   (1 << 8)
  
 -/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 +/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
  #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT                  9
  #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK                   (1 << 9)
  
 -/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 +/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
  #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT                  10
  #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK                   (1 << 10)
  
  #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT                     22
  #define OMAP4430_PMD_TRACE_MUX_CTRL_MASK                      (0x3 << 22)
  
 -/* Used by CM_DYN_DEP_PRESCAL, CM_DYN_DEP_PRESCAL_RESTORE */
 +/* Used by CM_DYN_DEP_PRESCAL */
  #define OMAP4430_PRESCAL_SHIFT                                        0
  #define OMAP4430_PRESCAL_MASK                                 (0x3f << 0)
  
  #define OMAP4430_R_RTL_SHIFT                                  11
  #define OMAP4430_R_RTL_MASK                                   (0x1f << 11)
  
 -/*
 - * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE,
 - * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE
 - */
 +/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL */
  #define OMAP4430_SAR_MODE_SHIFT                                       4
  #define OMAP4430_SAR_MODE_MASK                                        (1 << 4)
  
  #define OMAP4430_SCHEME_SHIFT                                 30
  #define OMAP4430_SCHEME_MASK                                  (0x3 << 30)
  
 -/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
 +/* Used by CM_L4CFG_DYNAMICDEP */
  #define OMAP4430_SDMA_DYNDEP_SHIFT                            11
  #define OMAP4430_SDMA_DYNDEP_MASK                             (1 << 11)
  
   * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
   * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
   * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
 - * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE,
 - * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
 - * CM_L3INIT_XHPI_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL,
 - * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL
 + * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
 + * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL,
 + * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
 + * CM_TESLA_TESLA_CLKCTRL
   */
  #define OMAP4430_STBYST_SHIFT                                 18
  #define OMAP4430_STBYST_MASK                                  (1 << 18)
  #define OMAP4430_ST_DPLL_CLKDCOLDO_MASK                               (1 << 9)
  
  /*
 - * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
 - * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
 - * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
 + * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
 + * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
   */
  #define OMAP4430_ST_DPLL_CLKOUT_SHIFT                         9
  #define OMAP4430_ST_DPLL_CLKOUT_MASK                          (1 << 9)
  
 -/*
 - * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
 - * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
 - */
 +/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
  #define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT                      9
  #define OMAP4430_ST_DPLL_CLKOUTHIF_MASK                               (1 << 9)
  
  #define OMAP4430_ST_DPLL_CLKOUTX2_MASK                                (1 << 11)
  
  /*
 - * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
 - * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
 + * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
 + * CM_DIV_M4_DPLL_PER
   */
  #define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT                   9
  #define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK                    (1 << 9)
  
  /*
 - * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
 - * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
 + * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
 + * CM_DIV_M5_DPLL_PER
   */
  #define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT                   9
  #define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK                    (1 << 9)
  
 -/*
 - * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
 - * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
 - */
 +/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
  #define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT                   9
  #define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK                    (1 << 9)
  
 -/*
 - * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
 - * CM_DIV_M7_DPLL_PER
 - */
 +/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
  #define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT                   9
  #define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK                    (1 << 9)
  
  #define OMAP4430_SYS_CLKSEL_SHIFT                             0
  #define OMAP4430_SYS_CLKSEL_MASK                              (0x7 << 0)
  
 -/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
 +/* Used by CM_L4CFG_DYNAMICDEP */
  #define OMAP4430_TESLA_DYNDEP_SHIFT                           1
  #define OMAP4430_TESLA_DYNDEP_MASK                            (1 << 1)
  
  #define OMAP4430_TESLA_STATDEP_MASK                           (1 << 1)
  
  /*
 - * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_DUCATI_DYNAMICDEP,
 - * CM_EMU_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE,
 - * CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
 - * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP,
 - * CM_L4PER_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
 + * Used by CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP,
 + * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
 + * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
   */
  #define OMAP4430_WINDOWSIZE_SHIFT                             24
  #define OMAP4430_WINDOWSIZE_MASK                              (0xf << 24)
index f57e0649ab3082903964485a4843b60c8548f882,21b1beb23e5ea14b8bc00fe83f0c9e4a243d66d7..df4b9683f17f5d6e1c4f70cc6693ed511da4ef3d
@@@ -58,10 -58,12 +58,12 @@@ struct clkops 
  #define RATE_IN_36XX          (1 << 4)
  #define RATE_IN_4430          (1 << 5)
  #define RATE_IN_TI816X                (1 << 6)
+ #define RATE_IN_4460          (1 << 7)
  
  #define RATE_IN_24XX          (RATE_IN_242X | RATE_IN_243X)
  #define RATE_IN_34XX          (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
  #define RATE_IN_3XXX          (RATE_IN_34XX | RATE_IN_36XX)
+ #define RATE_IN_44XX          (RATE_IN_4430 | RATE_IN_4460)
  
  /* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
  #define RATE_IN_3430ES2PLUS_36XX      (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
@@@ -152,7 -154,7 +154,7 @@@ struct dpll_data 
        u16                     max_multiplier;
        u8                      last_rounded_n;
        u8                      min_divider;
 -      u                     max_divider;
 +      u16                     max_divider;
        u8                      modes;
  #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
        void __iomem            *autoidle_reg;