]> git.openfabrics.org - ~shefty/rdma-dev.git/commitdiff
Merge branch 'next/fixes2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux...
authorLinus Torvalds <torvalds@linux-foundation.org>
Wed, 27 Jul 2011 00:10:20 +0000 (17:10 -0700)
committerLinus Torvalds <torvalds@linux-foundation.org>
Wed, 27 Jul 2011 00:10:20 +0000 (17:10 -0700)
* 'next/fixes2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: (24 commits)
  ASoC: omap: McBSP: fix build breakage on OMAP1
  OMAP: hwmod: fix the i2c-reset timeout during bootup
  I2C: OMAP2+: add correct functionality flags to all omap2plus i2c dev_attr
  I2C: OMAP2+: Tag all OMAP2+ hwmod defintions with I2C IP revision
  I2C: OMAP1/OMAP2+: create omap I2C functionality flags for each cpu_... test
  I2C: OMAP2+:  Introduce I2C IP versioning constants
  I2C: OMAP2+: increase omap_i2c_dev_attr flags from u8 to u32
  I2C: OMAP2+: Set hwmod flags to only allow 16-bit accesses to i2c
  OMAP4: hwmod data: Change DSS main_clk scheme
  OMAP4: powerdomain data: Remove unsupported MPU powerdomain state
  OMAP4: clock data: Keep GPMC clocks always enabled and hardware managed
  OMAP4: powerdomain data: Fix core mem states and missing cefuse flag
  OMAP2+: PM: Initialise sleep_switch to a non-valid value
  OMAP4: hwmod data: Modify DSS opt clocks
  OMAP4: iommu: fix clock name
  omap: iovmm: s/sg_dma_len(sg)/sg->length/
  omap: iommu: fix pte programming
  arm: omap3: cm-t35: fix slow path warning
  arm: omap3: cm-t35: minor comments fixes
  omap: ZOOM: QUART: Request reset GPIO
  ...

1  2 
arch/arm/mach-omap2/clock44xx_data.c

index 5b7cab794fb92f67664212120f669314deb9789e,257882028492abdc735e6bfc8ea3b35f6f0b29b2..25473a1db3e759fe2761b051fd2b6374161396c9
@@@ -1397,40 -1397,6 +1397,40 @@@ static struct clk dss_dss_clk = 
        .recalc         = &followparent_recalc,
  };
  
 +static const struct clksel_rate div3_8to32_rates[] = {
 +      { .div = 8, .val = 0, .flags = RATE_IN_44XX },
 +      { .div = 16, .val = 1, .flags = RATE_IN_44XX },
 +      { .div = 32, .val = 2, .flags = RATE_IN_44XX },
 +      { .div = 0 },
 +};
 +
 +static const struct clksel div_ts_div[] = {
 +      { .parent = &l4_wkup_clk_mux_ck, .rates = div3_8to32_rates },
 +      { .parent = NULL },
 +};
 +
 +static struct clk div_ts_ck = {
 +      .name           = "div_ts_ck",
 +      .parent         = &l4_wkup_clk_mux_ck,
 +      .clksel         = div_ts_div,
 +      .clksel_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
 +      .clksel_mask    = OMAP4430_CLKSEL_24_25_MASK,
 +      .ops            = &clkops_null,
 +      .recalc         = &omap2_clksel_recalc,
 +      .round_rate     = &omap2_clksel_round_rate,
 +      .set_rate       = &omap2_clksel_set_rate,
 +};
 +
 +static struct clk bandgap_ts_fclk = {
 +      .name           = "bandgap_ts_fclk",
 +      .ops            = &clkops_omap2_dflt,
 +      .enable_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
 +      .enable_bit     = OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
 +      .clkdm_name     = "l4_wkup_clkdm",
 +      .parent         = &div_ts_ck,
 +      .recalc         = &followparent_recalc,
 +};
 +
  static struct clk dss_48mhz_clk = {
        .name           = "dss_48mhz_clk",
        .ops            = &clkops_omap2_dflt,
@@@ -1639,6 -1605,7 +1639,7 @@@ static struct clk gpmc_ick = 
        .ops            = &clkops_omap2_dflt,
        .enable_reg     = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+       .flags          = ENABLE_ON_INIT,
        .clkdm_name     = "l3_2_clkdm",
        .parent         = &l3_div_ck,
        .recalc         = &followparent_recalc,
@@@ -3062,16 -3029,14 +3063,16 @@@ static struct omap_clk omap44xx_clks[] 
        CLK(NULL,       "aes2_fck",                     &aes2_fck,      CK_443X),
        CLK(NULL,       "aess_fck",                     &aess_fck,      CK_443X),
        CLK(NULL,       "bandgap_fclk",                 &bandgap_fclk,  CK_443X),
 +      CLK(NULL,       "bandgap_ts_fclk",              &bandgap_ts_fclk,       CK_446X),
        CLK(NULL,       "des3des_fck",                  &des3des_fck,   CK_443X),
 +      CLK(NULL,       "div_ts_ck",                    &div_ts_ck,     CK_446X),
        CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck,      CK_443X),
        CLK(NULL,       "dmic_fck",                     &dmic_fck,      CK_443X),
        CLK(NULL,       "dsp_fck",                      &dsp_fck,       CK_443X),
-       CLK("omapdss_dss",      "sys_clk",                      &dss_sys_clk,   CK_443X),
-       CLK("omapdss_dss",      "tv_clk",                       &dss_tv_clk,    CK_443X),
-       CLK("omapdss_dss",      "video_clk",                    &dss_48mhz_clk, CK_443X),
-       CLK("omapdss_dss",      "fck",                          &dss_dss_clk,   CK_443X),
+       CLK(NULL,       "dss_sys_clk",                  &dss_sys_clk,   CK_443X),
+       CLK(NULL,       "dss_tv_clk",                   &dss_tv_clk,    CK_443X),
+       CLK(NULL,       "dss_48mhz_clk",                &dss_48mhz_clk, CK_443X),
+       CLK(NULL,       "dss_dss_clk",                  &dss_dss_clk,   CK_443X),
        CLK("omapdss_dss",      "ick",                          &dss_fck,       CK_443X),
        CLK(NULL,       "efuse_ctrl_cust_fck",          &efuse_ctrl_cust_fck,   CK_443X),
        CLK(NULL,       "emif1_fck",                    &emif1_fck,     CK_443X),
@@@ -3244,9 -3209,6 +3245,9 @@@ int __init omap4xxx_clk_init(void
        if (cpu_is_omap44xx()) {
                cpu_mask = RATE_IN_4430;
                cpu_clkflg = CK_443X;
 +      } else if (cpu_is_omap446x()) {
 +              cpu_mask = RATE_IN_4460;
 +              cpu_clkflg = CK_446X;
        }
  
        clk_init(&omap2_clk_functions);