]> git.openfabrics.org - ~shefty/rdma-dev.git/commitdiff
Merge branch 'next/fixes2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux...
authorLinus Torvalds <torvalds@linux-foundation.org>
Wed, 27 Jul 2011 00:10:20 +0000 (17:10 -0700)
committerLinus Torvalds <torvalds@linux-foundation.org>
Wed, 27 Jul 2011 00:10:20 +0000 (17:10 -0700)
* 'next/fixes2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: (24 commits)
  ASoC: omap: McBSP: fix build breakage on OMAP1
  OMAP: hwmod: fix the i2c-reset timeout during bootup
  I2C: OMAP2+: add correct functionality flags to all omap2plus i2c dev_attr
  I2C: OMAP2+: Tag all OMAP2+ hwmod defintions with I2C IP revision
  I2C: OMAP1/OMAP2+: create omap I2C functionality flags for each cpu_... test
  I2C: OMAP2+:  Introduce I2C IP versioning constants
  I2C: OMAP2+: increase omap_i2c_dev_attr flags from u8 to u32
  I2C: OMAP2+: Set hwmod flags to only allow 16-bit accesses to i2c
  OMAP4: hwmod data: Change DSS main_clk scheme
  OMAP4: powerdomain data: Remove unsupported MPU powerdomain state
  OMAP4: clock data: Keep GPMC clocks always enabled and hardware managed
  OMAP4: powerdomain data: Fix core mem states and missing cefuse flag
  OMAP2+: PM: Initialise sleep_switch to a non-valid value
  OMAP4: hwmod data: Modify DSS opt clocks
  OMAP4: iommu: fix clock name
  omap: iovmm: s/sg_dma_len(sg)/sg->length/
  omap: iommu: fix pte programming
  arm: omap3: cm-t35: fix slow path warning
  arm: omap3: cm-t35: minor comments fixes
  omap: ZOOM: QUART: Request reset GPIO
  ...

22 files changed:
arch/arm/mach-omap2/board-cm-t35.c
arch/arm/mach-omap2/board-overo.c
arch/arm/mach-omap2/board-zoom-debugboard.c
arch/arm/mach-omap2/clock.c
arch/arm/mach-omap2/clock44xx_data.c
arch/arm/mach-omap2/hsmmc.c
arch/arm/mach-omap2/i2c.c
arch/arm/mach-omap2/iommu2.c
arch/arm/mach-omap2/omap-iommu.c
arch/arm/mach-omap2/omap_hwmod.c
arch/arm/mach-omap2/omap_hwmod_2420_data.c
arch/arm/mach-omap2/omap_hwmod_2430_data.c
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
arch/arm/mach-omap2/pm.c
arch/arm/mach-omap2/powerdomains44xx_data.c
arch/arm/plat-omap/dmtimer.c
arch/arm/plat-omap/include/plat/i2c.h
arch/arm/plat-omap/include/plat/omap_hwmod.h
arch/arm/plat-omap/iovmm.c
arch/arm/plat-omap/mcbsp.c
include/linux/i2c-omap.h

index 35891d49c631991ac5e69ac995507b1e08b25624..f0749215df115087d27a6cf9b1b3c774138273ce 100644 (file)
@@ -1,8 +1,9 @@
 /*
  * board-cm-t35.c (CompuLab CM-T35 module)
  *
- * Copyright (C) 2009 CompuLab, Ltd.
- * Author: Mike Rapoport <mike@compulab.co.il>
+ * Copyright (C) 2009-2011 CompuLab, Ltd.
+ * Authors: Mike Rapoport <mike@compulab.co.il>
+ *         Igor Grinberg <grinberg@compulab.co.il>
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  * General Public License for more details.
  *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
  */
 
 #include <linux/kernel.h>
@@ -149,12 +145,12 @@ static struct mtd_partition cm_t35_nand_partitions[] = {
        },
        {
                .name           = "linux",
-               .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x280000 */
+               .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x2A0000 */
                .size           = 32 * NAND_BLOCK_SIZE,
        },
        {
                .name           = "rootfs",
-               .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x680000 */
+               .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x6A0000 */
                .size           = MTDPART_SIZ_FULL,
        },
 };
@@ -433,9 +429,9 @@ static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio,
        if (gpio_request_one(wlan_rst, GPIOF_OUT_INIT_HIGH, "WLAN RST") == 0) {
                gpio_export(wlan_rst, 0);
                udelay(10);
-               gpio_set_value(wlan_rst, 0);
+               gpio_set_value_cansleep(wlan_rst, 0);
                udelay(10);
-               gpio_set_value(wlan_rst, 1);
+               gpio_set_value_cansleep(wlan_rst, 1);
        } else {
                pr_err("CM-T35: could not obtain gpio for WiFi reset\n");
        }
index f1f18d03d24c082bebc78b33c683bdc67657b072..f949a9954d761a7e291d5dee6284aabcd74049f8 100644 (file)
@@ -519,7 +519,6 @@ static void __init overo_init(void)
        usb_musb_init(NULL);
        usbhs_init(&usbhs_bdata);
        overo_spi_init();
-       overo_ads7846_init();
        overo_init_smsc911x();
        overo_display_init();
        overo_init_led();
index 6402e781c458c7ebbdd48017acc9527e038f6ef4..369c2eb7715b30de41323fb4dceb04c1b957c2f0 100644 (file)
@@ -23,6 +23,7 @@
 #define ZOOM_SMSC911X_GPIO     158
 #define ZOOM_QUADUART_CS       3
 #define ZOOM_QUADUART_GPIO     102
+#define ZOOM_QUADUART_RST_GPIO 152
 #define QUART_CLK              1843200
 #define DEBUG_BASE             0x08000000
 #define ZOOM_ETHR_START        DEBUG_BASE
@@ -67,6 +68,14 @@ static inline void __init zoom_init_quaduart(void)
        unsigned long cs_mem_base;
        int quart_gpio = 0;
 
+       if (gpio_request_one(ZOOM_QUADUART_RST_GPIO,
+                               GPIOF_OUT_INIT_LOW,
+                               "TL16CP754C GPIO") < 0) {
+               pr_err("Failed to request GPIO%d for TL16CP754C\n",
+                       ZOOM_QUADUART_RST_GPIO);
+               return;
+       }
+
        quart_cs = ZOOM_QUADUART_CS;
 
        if (gpmc_cs_request(quart_cs, SZ_1M, &cs_mem_base) < 0) {
index 180299e4a838c05a2e2ce30afdfdbd49f6cd1524..bf9c36c7dffd55d073702597dd8e95f31544207d 100644 (file)
@@ -453,6 +453,7 @@ int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name)
        if (IS_ERR_VALUE(r)) {
                WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n",
                     mpurate_ck->name, mpurate, r);
+               clk_put(mpurate_ck);
                return -EINVAL;
        }
 
index 5b7cab794fb92f67664212120f669314deb9789e..25473a1db3e759fe2761b051fd2b6374161396c9 100644 (file)
@@ -1639,6 +1639,7 @@ static struct clk gpmc_ick = {
        .ops            = &clkops_omap2_dflt,
        .enable_reg     = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+       .flags          = ENABLE_ON_INIT,
        .clkdm_name     = "l3_2_clkdm",
        .parent         = &l3_div_ck,
        .recalc         = &followparent_recalc,
@@ -3068,10 +3069,10 @@ static struct omap_clk omap44xx_clks[] = {
        CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck,      CK_443X),
        CLK(NULL,       "dmic_fck",                     &dmic_fck,      CK_443X),
        CLK(NULL,       "dsp_fck",                      &dsp_fck,       CK_443X),
-       CLK("omapdss_dss",      "sys_clk",                      &dss_sys_clk,   CK_443X),
-       CLK("omapdss_dss",      "tv_clk",                       &dss_tv_clk,    CK_443X),
-       CLK("omapdss_dss",      "video_clk",                    &dss_48mhz_clk, CK_443X),
-       CLK("omapdss_dss",      "fck",                          &dss_dss_clk,   CK_443X),
+       CLK(NULL,       "dss_sys_clk",                  &dss_sys_clk,   CK_443X),
+       CLK(NULL,       "dss_tv_clk",                   &dss_tv_clk,    CK_443X),
+       CLK(NULL,       "dss_48mhz_clk",                &dss_48mhz_clk, CK_443X),
+       CLK(NULL,       "dss_dss_clk",                  &dss_dss_clk,   CK_443X),
        CLK("omapdss_dss",      "ick",                          &dss_fck,       CK_443X),
        CLK(NULL,       "efuse_ctrl_cust_fck",          &efuse_ctrl_cust_fck,   CK_443X),
        CLK(NULL,       "emif1_fck",                    &emif1_fck,     CK_443X),
index 66868c5d5a29b8207da355ef7163e941296f615c..a9b45c76e1d36a59dc2ad288cbbf2f87cdfe4a1b 100644 (file)
@@ -13,6 +13,7 @@
 #include <linux/slab.h>
 #include <linux/string.h>
 #include <linux/delay.h>
+#include <linux/gpio.h>
 #include <mach/hardware.h>
 #include <plat/mmc.h>
 #include <plat/omap-pm.h>
@@ -213,12 +214,10 @@ static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
 static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
                        int controller_nr)
 {
-       if ((mmc_controller->slots[0].switch_pin > 0) && \
-               (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
+       if (gpio_is_valid(mmc_controller->slots[0].switch_pin))
                omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
                                        OMAP_PIN_INPUT_PULLUP);
-       if ((mmc_controller->slots[0].gpio_wp > 0) && \
-               (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
+       if (gpio_is_valid(mmc_controller->slots[0].gpio_wp))
                omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
                                        OMAP_PIN_INPUT_PULLUP);
        if (cpu_is_omap34xx()) {
index 79c478c4cb1cc0696b62cb0e23ca53596588d14f..ace99944e96f1b0ac50224cc24a838849fc77d49 100644 (file)
 
 #include <plat/cpu.h>
 #include <plat/i2c.h>
+#include <plat/common.h>
+#include <plat/omap_hwmod.h>
 
 #include "mux.h"
 
+/* In register I2C_CON, Bit 15 is the I2C enable bit */
+#define I2C_EN                                 BIT(15)
+#define OMAP2_I2C_CON_OFFSET                   0x24
+#define OMAP4_I2C_CON_OFFSET                   0xA4
+
+/* Maximum microseconds to wait for OMAP module to softreset */
+#define MAX_MODULE_SOFTRESET_WAIT      10000
+
 void __init omap2_i2c_mux_pins(int bus_id)
 {
        char mux_name[sizeof("i2c2_scl.i2c2_scl")];
@@ -37,3 +47,61 @@ void __init omap2_i2c_mux_pins(int bus_id)
        sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id);
        omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
 }
+
+/**
+ * omap_i2c_reset - reset the omap i2c module.
+ * @oh: struct omap_hwmod *
+ *
+ * The i2c moudle in omap2, omap3 had a special sequence to reset. The
+ * sequence is:
+ * - Disable the I2C.
+ * - Write to SOFTRESET bit.
+ * - Enable the I2C.
+ * - Poll on the RESETDONE bit.
+ * The sequence is implemented in below function. This is called for 2420,
+ * 2430 and omap3.
+ */
+int omap_i2c_reset(struct omap_hwmod *oh)
+{
+       u32 v;
+       u16 i2c_con;
+       int c = 0;
+
+       if (oh->class->rev == OMAP_I2C_IP_VERSION_2) {
+               i2c_con = OMAP4_I2C_CON_OFFSET;
+       } else if (oh->class->rev == OMAP_I2C_IP_VERSION_1) {
+               i2c_con = OMAP2_I2C_CON_OFFSET;
+       } else {
+               WARN(1, "Cannot reset I2C block %s: unsupported revision\n",
+                    oh->name);
+               return -EINVAL;
+       }
+
+       /* Disable I2C */
+       v = omap_hwmod_read(oh, i2c_con);
+       v &= ~I2C_EN;
+       omap_hwmod_write(v, oh, i2c_con);
+
+       /* Write to the SOFTRESET bit */
+       omap_hwmod_softreset(oh);
+
+       /* Enable I2C */
+       v = omap_hwmod_read(oh, i2c_con);
+       v |= I2C_EN;
+       omap_hwmod_write(v, oh, i2c_con);
+
+       /* Poll on RESETDONE bit */
+       omap_test_timeout((omap_hwmod_read(oh,
+                               oh->class->sysc->syss_offs)
+                               & SYSS_RESETDONE_MASK),
+                               MAX_MODULE_SOFTRESET_WAIT, c);
+
+       if (c == MAX_MODULE_SOFTRESET_WAIT)
+               pr_warning("%s: %s: softreset failed (waited %d usec)\n",
+                       __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
+       else
+               pr_debug("%s: %s: softreset in %d usec\n", __func__,
+                       oh->name, c);
+
+       return 0;
+}
index adb083e41acd13bc05c6b7cc54de8b6130dee370..f286012783c6c99a9e1cbed453aecdeed43b5e3c 100644 (file)
@@ -225,8 +225,8 @@ static u32 omap2_get_pte_attr(struct iotlb_entry *e)
        attr = e->mixed << 5;
        attr |= e->endian;
        attr |= e->elsz >> 3;
-       attr <<= ((e->pgsz & MMU_CAM_PGSZ_4K) ? 0 : 6);
-
+       attr <<= (((e->pgsz == MMU_CAM_PGSZ_4K) ||
+                       (e->pgsz == MMU_CAM_PGSZ_64K)) ? 0 : 6);
        return attr;
 }
 
index 3fc5dc7233da29ca0eb0c603527da9b46fc13f46..e61feadcda4ee6438b64eb5418871d1733dfebad 100644 (file)
@@ -67,7 +67,7 @@ static struct iommu_device omap4_devices[] = {
                .pdata = {
                        .name = "ducati",
                        .nr_tlb_entries = 32,
-                       .clk_name = "ducati_ick",
+                       .clk_name = "ipu_fck",
                        .da_start = 0x0,
                        .da_end = 0xFFFFF000,
                },
index 7d242c9e2a2c7b5db7a2de4c5aedee3169fbb5e6..02b6016393a8ff24cba4e11af5fbac8738068f82 100644 (file)
@@ -1655,6 +1655,33 @@ void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
                __raw_writel(v, oh->_mpu_rt_va + reg_offs);
 }
 
+/**
+ * omap_hwmod_softreset - reset a module via SYSCONFIG.SOFTRESET bit
+ * @oh: struct omap_hwmod *
+ *
+ * This is a public function exposed to drivers. Some drivers may need to do
+ * some settings before and after resetting the device.  Those drivers after
+ * doing the necessary settings could use this function to start a reset by
+ * setting the SYSCONFIG.SOFTRESET bit.
+ */
+int omap_hwmod_softreset(struct omap_hwmod *oh)
+{
+       u32 v;
+       int ret;
+
+       if (!oh || !(oh->_sysc_cache))
+               return -EINVAL;
+
+       v = oh->_sysc_cache;
+       ret = _set_softreset(oh, &v);
+       if (ret)
+               goto error;
+       _write_sysconfig(v, oh);
+
+error:
+       return ret;
+}
+
 /**
  * omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode
  * @oh: struct omap_hwmod *
index f3901abf2c286911b27ea587f00769d7c3fd3525..a015c69068f68fc9d86a242fc019cd87e7beb7f3 100644 (file)
@@ -1029,9 +1029,16 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = {
 static struct omap_hwmod_class i2c_class = {
        .name           = "i2c",
        .sysc           = &i2c_sysc,
+       .rev            = OMAP_I2C_IP_VERSION_1,
+       .reset          = &omap_i2c_reset,
 };
 
-static struct omap_i2c_dev_attr i2c_dev_attr;
+static struct omap_i2c_dev_attr i2c_dev_attr = {
+       .flags          = OMAP_I2C_FLAG_NO_FIFO |
+                         OMAP_I2C_FLAG_SIMPLE_CLOCK |
+                         OMAP_I2C_FLAG_16BIT_DATA_REG |
+                         OMAP_I2C_FLAG_BUS_SHIFT_2,
+};
 
 /* I2C1 */
 
index 2a52f025bd069f37b07127e28d5a8c5ff011fd2e..16743c7d6e8effe6c1b0089008865543f5798c43 100644 (file)
@@ -1078,10 +1078,15 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = {
 static struct omap_hwmod_class i2c_class = {
        .name           = "i2c",
        .sysc           = &i2c_sysc,
+       .rev            = OMAP_I2C_IP_VERSION_1,
+       .reset          = &omap_i2c_reset,
 };
 
 static struct omap_i2c_dev_attr i2c_dev_attr = {
        .fifo_depth     = 8, /* bytes */
+       .flags          = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
+                         OMAP_I2C_FLAG_BUS_SHIFT_2 |
+                         OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
 };
 
 /* I2C1 */
@@ -1092,6 +1097,7 @@ static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
 
 static struct omap_hwmod omap2430_i2c1_hwmod = {
        .name           = "i2c1",
+       .flags          = HWMOD_16BIT_REG,
        .mpu_irqs       = omap2_i2c1_mpu_irqs,
        .sdma_reqs      = omap2_i2c1_sdma_reqs,
        .main_clk       = "i2chs1_fck",
@@ -1127,6 +1133,7 @@ static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
 
 static struct omap_hwmod omap2430_i2c2_hwmod = {
        .name           = "i2c2",
+       .flags          = HWMOD_16BIT_REG,
        .mpu_irqs       = omap2_i2c2_mpu_irqs,
        .sdma_reqs      = omap2_i2c2_sdma_reqs,
        .main_clk       = "i2chs2_fck",
index 1a52716e48bfe048e804b233746b02c4d0519dde..25bf43b5a4ec02922049abd9fd16806297fc1b37 100644 (file)
@@ -1306,8 +1306,10 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = {
 };
 
 static struct omap_hwmod_class i2c_class = {
-       .name = "i2c",
-       .sysc = &i2c_sysc,
+       .name   = "i2c",
+       .sysc   = &i2c_sysc,
+       .rev    = OMAP_I2C_IP_VERSION_1,
+       .reset  = &omap_i2c_reset,
 };
 
 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
@@ -1607,6 +1609,9 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
 
 static struct omap_i2c_dev_attr i2c1_dev_attr = {
        .fifo_depth     = 8, /* bytes */
+       .flags          = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
+                         OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
+                         OMAP_I2C_FLAG_BUS_SHIFT_2,
 };
 
 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
@@ -1615,6 +1620,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
 
 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
        .name           = "i2c1",
+       .flags          = HWMOD_16BIT_REG,
        .mpu_irqs       = omap2_i2c1_mpu_irqs,
        .sdma_reqs      = omap2_i2c1_sdma_reqs,
        .main_clk       = "i2c1_fck",
@@ -1638,6 +1644,9 @@ static struct omap_hwmod omap3xxx_i2c1_hwmod = {
 
 static struct omap_i2c_dev_attr i2c2_dev_attr = {
        .fifo_depth     = 8, /* bytes */
+       .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
+                OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
+                OMAP_I2C_FLAG_BUS_SHIFT_2,
 };
 
 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
@@ -1646,6 +1655,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
 
 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
        .name           = "i2c2",
+       .flags          = HWMOD_16BIT_REG,
        .mpu_irqs       = omap2_i2c2_mpu_irqs,
        .sdma_reqs      = omap2_i2c2_sdma_reqs,
        .main_clk       = "i2c2_fck",
@@ -1669,6 +1679,9 @@ static struct omap_hwmod omap3xxx_i2c2_hwmod = {
 
 static struct omap_i2c_dev_attr i2c3_dev_attr = {
        .fifo_depth     = 64, /* bytes */
+       .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
+                OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
+                OMAP_I2C_FLAG_BUS_SHIFT_2,
 };
 
 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
@@ -1688,6 +1701,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
 
 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
        .name           = "i2c3",
+       .flags          = HWMOD_16BIT_REG,
        .mpu_irqs       = i2c3_mpu_irqs,
        .sdma_reqs      = i2c3_sdma_reqs,
        .main_clk       = "i2c3_fck",
index e01143725b089aa113a65f0470cbe986d3fa7bad..5d5df49749dfe5b69ceccdc71896ecdf4f837940 100644 (file)
 
 #include <plat/omap_hwmod.h>
 #include <plat/cpu.h>
+#include <plat/i2c.h>
 #include <plat/gpio.h>
 #include <plat/dma.h>
 #include <plat/mcspi.h>
 #include <plat/mcbsp.h>
 #include <plat/mmc.h>
+#include <plat/i2c.h>
 
 #include "omap_hwmod_common_data.h"
 
@@ -1136,7 +1138,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
        .master         = &omap44xx_l3_main_2_hwmod,
        .slave          = &omap44xx_dss_hwmod,
-       .clk            = "l3_div_ck",
+       .clk            = "dss_fck",
        .addr           = omap44xx_dss_dma_addrs,
        .user           = OCP_USER_SDMA,
 };
@@ -1175,7 +1177,7 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 static struct omap_hwmod omap44xx_dss_hwmod = {
        .name           = "dss_core",
        .class          = &omap44xx_dss_hwmod_class,
-       .main_clk       = "dss_fck",
+       .main_clk       = "dss_dss_clk",
        .prcm = {
                .omap4 = {
                        .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
@@ -1238,7 +1240,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
        .master         = &omap44xx_l3_main_2_hwmod,
        .slave          = &omap44xx_dss_dispc_hwmod,
-       .clk            = "l3_div_ck",
+       .clk            = "dss_fck",
        .addr           = omap44xx_dss_dispc_dma_addrs,
        .user           = OCP_USER_SDMA,
 };
@@ -1267,17 +1269,26 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
        &omap44xx_l4_per__dss_dispc,
 };
 
+static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
+       { .role = "sys_clk", .clk = "dss_sys_clk" },
+       { .role = "tv_clk", .clk = "dss_tv_clk" },
+       { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
+};
+
 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
        .name           = "dss_dispc",
        .class          = &omap44xx_dispc_hwmod_class,
+       .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
        .mpu_irqs       = omap44xx_dss_dispc_irqs,
        .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
-       .main_clk       = "dss_fck",
+       .main_clk       = "dss_dss_clk",
        .prcm = {
                .omap4 = {
                        .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
                },
        },
+       .opt_clks       = dss_dispc_opt_clks,
+       .opt_clks_cnt   = ARRAY_SIZE(dss_dispc_opt_clks),
        .slaves         = omap44xx_dss_dispc_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -1329,7 +1340,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
        .master         = &omap44xx_l3_main_2_hwmod,
        .slave          = &omap44xx_dss_dsi1_hwmod,
-       .clk            = "l3_div_ck",
+       .clk            = "dss_fck",
        .addr           = omap44xx_dss_dsi1_dma_addrs,
        .user           = OCP_USER_SDMA,
 };
@@ -1358,17 +1369,23 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
        &omap44xx_l4_per__dss_dsi1,
 };
 
+static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
+       { .role = "sys_clk", .clk = "dss_sys_clk" },
+};
+
 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
        .name           = "dss_dsi1",
        .class          = &omap44xx_dsi_hwmod_class,
        .mpu_irqs       = omap44xx_dss_dsi1_irqs,
        .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
-       .main_clk       = "dss_fck",
+       .main_clk       = "dss_dss_clk",
        .prcm = {
                .omap4 = {
                        .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
                },
        },
+       .opt_clks       = dss_dsi1_opt_clks,
+       .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
        .slaves         = omap44xx_dss_dsi1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -1399,7 +1416,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
        .master         = &omap44xx_l3_main_2_hwmod,
        .slave          = &omap44xx_dss_dsi2_hwmod,
-       .clk            = "l3_div_ck",
+       .clk            = "dss_fck",
        .addr           = omap44xx_dss_dsi2_dma_addrs,
        .user           = OCP_USER_SDMA,
 };
@@ -1428,17 +1445,23 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
        &omap44xx_l4_per__dss_dsi2,
 };
 
+static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
+       { .role = "sys_clk", .clk = "dss_sys_clk" },
+};
+
 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
        .name           = "dss_dsi2",
        .class          = &omap44xx_dsi_hwmod_class,
        .mpu_irqs       = omap44xx_dss_dsi2_irqs,
        .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
-       .main_clk       = "dss_fck",
+       .main_clk       = "dss_dss_clk",
        .prcm = {
                .omap4 = {
                        .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
                },
        },
+       .opt_clks       = dss_dsi2_opt_clks,
+       .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
        .slaves         = omap44xx_dss_dsi2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -1489,7 +1512,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
        .master         = &omap44xx_l3_main_2_hwmod,
        .slave          = &omap44xx_dss_hdmi_hwmod,
-       .clk            = "l3_div_ck",
+       .clk            = "dss_fck",
        .addr           = omap44xx_dss_hdmi_dma_addrs,
        .user           = OCP_USER_SDMA,
 };
@@ -1518,17 +1541,23 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
        &omap44xx_l4_per__dss_hdmi,
 };
 
+static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
+       { .role = "sys_clk", .clk = "dss_sys_clk" },
+};
+
 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
        .name           = "dss_hdmi",
        .class          = &omap44xx_hdmi_hwmod_class,
        .mpu_irqs       = omap44xx_dss_hdmi_irqs,
        .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
-       .main_clk       = "dss_fck",
+       .main_clk       = "dss_dss_clk",
        .prcm = {
                .omap4 = {
                        .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
                },
        },
+       .opt_clks       = dss_hdmi_opt_clks,
+       .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
        .slaves         = omap44xx_dss_hdmi_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -1574,7 +1603,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
        .master         = &omap44xx_l3_main_2_hwmod,
        .slave          = &omap44xx_dss_rfbi_hwmod,
-       .clk            = "l3_div_ck",
+       .clk            = "dss_fck",
        .addr           = omap44xx_dss_rfbi_dma_addrs,
        .user           = OCP_USER_SDMA,
 };
@@ -1603,16 +1632,22 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
        &omap44xx_l4_per__dss_rfbi,
 };
 
+static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
+       { .role = "ick", .clk = "dss_fck" },
+};
+
 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
        .name           = "dss_rfbi",
        .class          = &omap44xx_rfbi_hwmod_class,
        .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
-       .main_clk       = "dss_fck",
+       .main_clk       = "dss_dss_clk",
        .prcm = {
                .omap4 = {
                        .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
                },
        },
+       .opt_clks       = dss_rfbi_opt_clks,
+       .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
        .slaves         = omap44xx_dss_rfbi_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -1642,7 +1677,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
        .master         = &omap44xx_l3_main_2_hwmod,
        .slave          = &omap44xx_dss_venc_hwmod,
-       .clk            = "l3_div_ck",
+       .clk            = "dss_fck",
        .addr           = omap44xx_dss_venc_dma_addrs,
        .user           = OCP_USER_SDMA,
 };
@@ -1674,7 +1709,7 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
        .name           = "dss_venc",
        .class          = &omap44xx_venc_hwmod_class,
-       .main_clk       = "dss_fck",
+       .main_clk       = "dss_dss_clk",
        .prcm = {
                .omap4 = {
                        .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
@@ -2127,6 +2162,12 @@ static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
        .name   = "i2c",
        .sysc   = &omap44xx_i2c_sysc,
+       .rev    = OMAP_I2C_IP_VERSION_2,
+       .reset  = &omap_i2c_reset,
+};
+
+static struct omap_i2c_dev_attr i2c_dev_attr = {
+       .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
 };
 
 /* i2c1 */
@@ -2168,7 +2209,7 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
 static struct omap_hwmod omap44xx_i2c1_hwmod = {
        .name           = "i2c1",
        .class          = &omap44xx_i2c_hwmod_class,
-       .flags          = HWMOD_INIT_NO_RESET,
+       .flags          = HWMOD_16BIT_REG,
        .mpu_irqs       = omap44xx_i2c1_irqs,
        .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
        .main_clk       = "i2c1_fck",
@@ -2179,6 +2220,7 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
        },
        .slaves         = omap44xx_i2c1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
+       .dev_attr       = &i2c_dev_attr,
        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
@@ -2221,7 +2263,7 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
 static struct omap_hwmod omap44xx_i2c2_hwmod = {
        .name           = "i2c2",
        .class          = &omap44xx_i2c_hwmod_class,
-       .flags          = HWMOD_INIT_NO_RESET,
+       .flags          = HWMOD_16BIT_REG,
        .mpu_irqs       = omap44xx_i2c2_irqs,
        .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
        .main_clk       = "i2c2_fck",
@@ -2232,6 +2274,7 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
        },
        .slaves         = omap44xx_i2c2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
+       .dev_attr       = &i2c_dev_attr,
        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
@@ -2274,7 +2317,7 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
 static struct omap_hwmod omap44xx_i2c3_hwmod = {
        .name           = "i2c3",
        .class          = &omap44xx_i2c_hwmod_class,
-       .flags          = HWMOD_INIT_NO_RESET,
+       .flags          = HWMOD_16BIT_REG,
        .mpu_irqs       = omap44xx_i2c3_irqs,
        .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
        .main_clk       = "i2c3_fck",
@@ -2285,6 +2328,7 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
        },
        .slaves         = omap44xx_i2c3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
+       .dev_attr       = &i2c_dev_attr,
        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
@@ -2327,7 +2371,7 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
 static struct omap_hwmod omap44xx_i2c4_hwmod = {
        .name           = "i2c4",
        .class          = &omap44xx_i2c_hwmod_class,
-       .flags          = HWMOD_INIT_NO_RESET,
+       .flags          = HWMOD_16BIT_REG,
        .mpu_irqs       = omap44xx_i2c4_irqs,
        .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
        .main_clk       = "i2c4_fck",
@@ -2338,6 +2382,7 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
        },
        .slaves         = omap44xx_i2c4_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
+       .dev_attr       = &i2c_dev_attr,
        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
index 49486f522dca55b05fc55f74523a2053f8df54e0..d48813fd62de9a539db7f258970f9cc1da204924 100644 (file)
@@ -106,7 +106,7 @@ static void omap2_init_processor_devices(void)
 int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
 {
        u32 cur_state;
-       int sleep_switch = 0;
+       int sleep_switch = -1;
        int ret = 0;
 
        if (pwrdm == NULL || IS_ERR(pwrdm))
index 3a7e678fd5f1c36dc80171683a6cbf509e6467e9..247e79495115e45e43153163b08aa9e31c054cdb 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * OMAP4 Power domains framework
  *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2011 Texas Instruments, Inc.
  * Copyright (C) 2009-2011 Nokia Corporation
  *
  * Abhijit Pagare (abhijitpagare@ti.com)
@@ -41,14 +41,14 @@ static struct powerdomain core_44xx_pwrdm = {
        .banks            = 5,
        .pwrsts_mem_ret = {
                [0] = PWRSTS_OFF,       /* core_nret_bank */
-               [1] = PWRSTS_OFF_RET,   /* core_ocmram */
+               [1] = PWRSTS_RET,       /* core_ocmram */
                [2] = PWRSTS_RET,       /* core_other_bank */
                [3] = PWRSTS_OFF_RET,   /* ducati_l2ram */
                [4] = PWRSTS_OFF_RET,   /* ducati_unicache */
        },
        .pwrsts_mem_on  = {
                [0] = PWRSTS_ON,        /* core_nret_bank */
-               [1] = PWRSTS_OFF_RET,   /* core_ocmram */
+               [1] = PWRSTS_ON,        /* core_ocmram */
                [2] = PWRSTS_ON,        /* core_other_bank */
                [3] = PWRSTS_ON,        /* ducati_l2ram */
                [4] = PWRSTS_ON,        /* ducati_unicache */
@@ -205,7 +205,7 @@ static struct powerdomain mpu_44xx_pwrdm = {
        .prcm_offs        = OMAP4430_PRM_MPU_INST,
        .prcm_partition   = OMAP4430_PRM_PARTITION,
        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-       .pwrsts           = PWRSTS_OFF_RET_ON,
+       .pwrsts           = PWRSTS_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF_RET,
        .banks            = 3,
        .pwrsts_mem_ret = {
@@ -318,6 +318,7 @@ static struct powerdomain cefuse_44xx_pwrdm = {
        .prcm_partition   = OMAP4430_PRM_PARTITION,
        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
        .pwrsts           = PWRSTS_OFF_ON,
+       .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
 
 /*
index 8dfb8186b2c21515245f8229a8886a3f04759158..75a847dd776a3d24ccca85c29aab32b90bbbe3e7 100644 (file)
@@ -209,8 +209,8 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
        }
        omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
 
-       /* Enable autoidle on OMAP2 / OMAP3 */
-       if (cpu_is_omap24xx() || cpu_is_omap34xx())
+       /* Enable autoidle on OMAP2+ */
+       if (cpu_class_is_omap2())
                autoidle = 1;
 
        /*
index 878d632c4092c63600f3d88f509e3c4a23a690f3..7c22b9e10dc3513c6598934943798ee092858803 100644 (file)
@@ -22,6 +22,7 @@
 #define __ASM__ARCH_OMAP_I2C_H
 
 #include <linux/i2c.h>
+#include <linux/i2c-omap.h>
 
 #if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
 extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
@@ -46,10 +47,13 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
  */
 struct omap_i2c_dev_attr {
        u8      fifo_depth;
-       u     flags;
+       u32     flags;
 };
 
 void __init omap1_i2c_mux_pins(int bus_id);
 void __init omap2_i2c_mux_pins(int bus_id);
 
+struct omap_hwmod;
+int omap_i2c_reset(struct omap_hwmod *oh);
+
 #endif /* __ASM__ARCH_OMAP_I2C_H */
index ce06ac6a9709e8ec6fb6e012c4f4f39cc011dc53..fafdfe3c8d4e8e92d3f4a9f610e30d8f38935fa8 100644 (file)
@@ -566,6 +566,7 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
 
 void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs);
 u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs);
+int omap_hwmod_softreset(struct omap_hwmod *oh);
 
 int omap_hwmod_count_resources(struct omap_hwmod *oh);
 int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
index 83a37c54342f414573d942c2c28f5bb9459b4ec7..c60737c49a32fae14b445ce938c59975998d7ae4 100644 (file)
@@ -72,7 +72,7 @@ static size_t sgtable_len(const struct sg_table *sgt)
        for_each_sg(sgt->sgl, sg, sgt->nents, i) {
                size_t bytes;
 
-               bytes = sg_dma_len(sg);
+               bytes = sg->length;
 
                if (!iopgsz_ok(bytes)) {
                        pr_err("%s: sg[%d] not iommu pagesize(%x)\n",
@@ -198,7 +198,7 @@ static void *vmap_sg(const struct sg_table *sgt)
                int err;
 
                pa = sg_phys(sg);
-               bytes = sg_dma_len(sg);
+               bytes = sg->length;
 
                BUG_ON(bytes != PAGE_SIZE);
 
@@ -476,7 +476,7 @@ static int map_iovm_area(struct iommu *obj, struct iovm_struct *new,
                struct iotlb_entry e;
 
                pa = sg_phys(sg);
-               bytes = sg_dma_len(sg);
+               bytes = sg->length;
 
                flags &= ~IOVMF_PGSZ_MASK;
                pgsz = bytes_to_iopgsz(bytes);
index 3c1fbdc92468480a3781e65095e35cbe12154b67..6c62af108710c89fc6f36e814bbf36beec338fb8 100644 (file)
@@ -966,6 +966,33 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx)
 }
 EXPORT_SYMBOL(omap_mcbsp_stop);
 
+/*
+ * The following functions are only required on an OMAP1-only build.
+ * mach-omap2/mcbsp.c contains the real functions
+ */
+#ifndef CONFIG_ARCH_OMAP2PLUS
+int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
+{
+       WARN(1, "%s: should never be called on an OMAP1-only kernel\n",
+            __func__);
+       return -EINVAL;
+}
+
+void omap2_mcbsp1_mux_clkr_src(u8 mux)
+{
+       WARN(1, "%s: should never be called on an OMAP1-only kernel\n",
+            __func__);
+       return;
+}
+
+void omap2_mcbsp1_mux_fsr_src(u8 mux)
+{
+       WARN(1, "%s: should never be called on an OMAP1-only kernel\n",
+            __func__);
+       return;
+}
+#endif
+
 #ifdef CONFIG_ARCH_OMAP3
 #define max_thres(m)                   (mcbsp->pdata->buffer_size)
 #define valid_threshold(m, val)                ((val) <= max_thres(m))
index 7472449cbb7416b7a23f964e542af373fda2411e..0aa0cbd676f773caae994e24c39df3f9241fb066 100644 (file)
@@ -3,6 +3,33 @@
 
 #include <linux/platform_device.h>
 
+/*
+ * Version 2 of the I2C peripheral unit has a different register
+ * layout and extra registers.  The ID register in the V2 peripheral
+ * unit on the OMAP4430 reports the same ID as the V1 peripheral
+ * unit on the OMAP3530, so we must inform the driver which IP
+ * version we know it is running on from platform / cpu-specific
+ * code using these constants in the hwmod class definition.
+ */
+
+#define OMAP_I2C_IP_VERSION_1 1
+#define OMAP_I2C_IP_VERSION_2 2
+
+/* struct omap_i2c_bus_platform_data .flags meanings */
+
+#define OMAP_I2C_FLAG_NO_FIFO                  BIT(0)
+#define OMAP_I2C_FLAG_SIMPLE_CLOCK             BIT(1)
+#define OMAP_I2C_FLAG_16BIT_DATA_REG           BIT(2)
+#define OMAP_I2C_FLAG_RESET_REGS_POSTIDLE      BIT(3)
+#define OMAP_I2C_FLAG_APPLY_ERRATA_I207        BIT(4)
+#define OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK        BIT(5)
+#define OMAP_I2C_FLAG_FORCE_19200_INT_CLK      BIT(6)
+/* how the CPU address bus must be translated for I2C unit access */
+#define OMAP_I2C_FLAG_BUS_SHIFT_NONE 0
+#define OMAP_I2C_FLAG_BUS_SHIFT_1              BIT(7)
+#define OMAP_I2C_FLAG_BUS_SHIFT_2              BIT(8)
+#define OMAP_I2C_FLAG_BUS_SHIFT__SHIFT 7
+
 struct omap_i2c_bus_platform_data {
        u32             clkrate;
        void            (*set_mpu_wkup_lat)(struct device *dev, long set);