Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
authorLinus Torvalds <torvalds@linux-foundation.org>
Tue, 27 Mar 2012 23:47:35 +0000 (16:47 -0700)
committerLinus Torvalds <torvalds@linux-foundation.org>
Tue, 27 Mar 2012 23:47:35 +0000 (16:47 -0700)
Pull "ARM: device tree work" from Arnd Bergmann:
 "Most of these patches convert code from using static platform data to
  describing the hardware in the device tree.  This is only the first
  half of the changes for v3.4 because a lot of patches for this topic
  came in the last week before the merge window.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>"
Fix up trivial conflicts in arch/arm/mach-vexpress/{Kconfig,core.h}

* tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (86 commits)
  Document: devicetree: add OF documents for arch-mmp
  ARM: dts: append DTS file of pxa168
  ARM: mmp: append OF support on pxa168
  ARM: mmp: enable rtc clk in pxa168
  i2c: pxa: add OF support
  serial: pxa: add OF support
  arm/dts: mt_ventoux: very basic support for TeeJet Mt.Ventoux board
  ARM: OMAP2+: Remove extra ifdefs for board-generic
  ARM: OMAP2+: Fix build error when only ARCH_OMAP2/3 or 4 is selected
  ASoC: DT: Add digital microphone binding to PAZ00 board.
  ARM: dt: Add ARM PMU to tegra*.dtsi
  ARM: at91: at91sam9x5cm/dt: add leds support
  ARM: at91: usb_a9g20/dt: add gpio-keys support
  ARM: at91: at91sam9m10g45ek/dt: add gpio-keys support
  ARM: at91: at91sam9m10g45ek/dt: add leds support
  ARM: at91: usb_a9g20/dt: add leds support
  ARM: at91/pio: add new PIO3 features
  ARM: at91: add sam9_smc.o to at91sam9x5 build
  ARM: at91/tc/clocksource: Add 32 bit variant to Timer Counter
  ARM: at91/tc: add device tree support to atmel_tclib
  ...

147 files changed:
Documentation/devicetree/bindings/arm/atmel-aic.txt [new file with mode: 0644]
Documentation/devicetree/bindings/arm/atmel-at91.txt [new file with mode: 0644]
Documentation/devicetree/bindings/arm/fsl.txt
Documentation/devicetree/bindings/arm/mrvl.txt [new file with mode: 0644]
Documentation/devicetree/bindings/arm/omap/intc.txt [new file with mode: 0644]
Documentation/devicetree/bindings/arm/vexpress.txt [new file with mode: 0644]
Documentation/devicetree/bindings/gpio/gpio_atmel.txt [new file with mode: 0644]
Documentation/devicetree/bindings/gpio/mrvl-gpio.txt [new file with mode: 0644]
Documentation/devicetree/bindings/i2c/mrvl-i2c.txt [new file with mode: 0644]
Documentation/devicetree/bindings/rtc/sa1100-rtc.txt [new file with mode: 0644]
Documentation/devicetree/bindings/serial/mrvl-serial.txt [new file with mode: 0644]
arch/arm/Kconfig
arch/arm/boot/dts/am3517_mt_ventoux.dts [new file with mode: 0644]
arch/arm/boot/dts/at91sam9g20.dtsi
arch/arm/boot/dts/at91sam9g45.dtsi
arch/arm/boot/dts/at91sam9m10g45ek.dts
arch/arm/boot/dts/at91sam9x5.dtsi
arch/arm/boot/dts/at91sam9x5cm.dtsi
arch/arm/boot/dts/imx27-phytec-phycore.dts [new file with mode: 0644]
arch/arm/boot/dts/imx27.dtsi [new file with mode: 0644]
arch/arm/boot/dts/imx51-babbage.dts
arch/arm/boot/dts/imx6q-arm2.dts
arch/arm/boot/dts/imx6q-sabrelite.dts
arch/arm/boot/dts/omap3-beagle.dts
arch/arm/boot/dts/omap3-evm.dts [new file with mode: 0644]
arch/arm/boot/dts/omap3.dtsi
arch/arm/boot/dts/omap4-panda.dts
arch/arm/boot/dts/omap4-sdp.dts
arch/arm/boot/dts/omap4.dtsi
arch/arm/boot/dts/pxa168-aspenite.dts [new file with mode: 0644]
arch/arm/boot/dts/pxa168.dtsi [new file with mode: 0644]
arch/arm/boot/dts/tegra-cardhu.dts
arch/arm/boot/dts/tegra-paz00.dts
arch/arm/boot/dts/tegra20.dtsi
arch/arm/boot/dts/tegra30.dtsi
arch/arm/boot/dts/usb_a9g20.dts
arch/arm/boot/dts/vexpress-v2m-rs1.dtsi [new file with mode: 0644]
arch/arm/boot/dts/vexpress-v2m.dtsi [new file with mode: 0644]
arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts [new file with mode: 0644]
arch/arm/boot/dts/vexpress-v2p-ca5s.dts [new file with mode: 0644]
arch/arm/boot/dts/vexpress-v2p-ca9.dts [new file with mode: 0644]
arch/arm/mach-at91/Makefile
arch/arm/mach-at91/Makefile.boot
arch/arm/mach-at91/at91rm9200.c
arch/arm/mach-at91/at91rm9200_devices.c
arch/arm/mach-at91/at91rm9200_time.c
arch/arm/mach-at91/at91sam9260.c
arch/arm/mach-at91/at91sam9260_devices.c
arch/arm/mach-at91/at91sam9261.c
arch/arm/mach-at91/at91sam9261_devices.c
arch/arm/mach-at91/at91sam9263.c
arch/arm/mach-at91/at91sam9263_devices.c
arch/arm/mach-at91/at91sam926x_time.c
arch/arm/mach-at91/at91sam9_alt_reset.S
arch/arm/mach-at91/at91sam9g45.c
arch/arm/mach-at91/at91sam9g45_devices.c
arch/arm/mach-at91/at91sam9g45_reset.S
arch/arm/mach-at91/at91sam9rl.c
arch/arm/mach-at91/at91sam9rl_devices.c
arch/arm/mach-at91/at91sam9x5.c
arch/arm/mach-at91/at91x40.c
arch/arm/mach-at91/at91x40_time.c
arch/arm/mach-at91/board-cpu9krea.c
arch/arm/mach-at91/board-cpuat91.c
arch/arm/mach-at91/board-dt.c
arch/arm/mach-at91/board-eco920.c
arch/arm/mach-at91/board-kb9202.c
arch/arm/mach-at91/board-picotux200.c
arch/arm/mach-at91/board-rm9200dk.c
arch/arm/mach-at91/board-rm9200ek.c
arch/arm/mach-at91/board-snapper9260.c
arch/arm/mach-at91/board-yl-9200.c
arch/arm/mach-at91/clock.c
arch/arm/mach-at91/generic.h
arch/arm/mach-at91/gpio.c
arch/arm/mach-at91/include/mach/at91_matrix.h [new file with mode: 0644]
arch/arm/mach-at91/include/mach/at91_pio.h
arch/arm/mach-at91/include/mach/at91_pmc.h
arch/arm/mach-at91/include/mach/at91_ramc.h [new file with mode: 0644]
arch/arm/mach-at91/include/mach/at91_st.h
arch/arm/mach-at91/include/mach/at91rm9200.h
arch/arm/mach-at91/include/mach/at91rm9200_mc.h
arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h [new file with mode: 0644]
arch/arm/mach-at91/include/mach/at91sam9260.h
arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
arch/arm/mach-at91/include/mach/at91sam9261.h
arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
arch/arm/mach-at91/include/mach/at91sam9263.h
arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
arch/arm/mach-at91/include/mach/at91sam9g45.h
arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
arch/arm/mach-at91/include/mach/at91sam9rl.h
arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
arch/arm/mach-at91/include/mach/at91sam9x5.h
arch/arm/mach-at91/include/mach/at91x40.h
arch/arm/mach-at91/include/mach/gpio.h
arch/arm/mach-at91/include/mach/hardware.h
arch/arm/mach-at91/include/mach/io.h
arch/arm/mach-at91/irq.c
arch/arm/mach-at91/pm.c
arch/arm/mach-at91/pm.h
arch/arm/mach-at91/pm_slowclock.S
arch/arm/mach-at91/setup.c
arch/arm/mach-imx/Kconfig
arch/arm/mach-imx/Makefile
arch/arm/mach-imx/Makefile.boot
arch/arm/mach-imx/clock-imx27.c
arch/arm/mach-imx/imx27-dt.c [new file with mode: 0644]
arch/arm/mach-imx/imx51-dt.c
arch/arm/mach-imx/imx53-dt.c
arch/arm/mach-imx/mach-imx6q.c
arch/arm/mach-mmp/Kconfig
arch/arm/mach-mmp/Makefile
arch/arm/mach-mmp/mmp-dt.c [new file with mode: 0644]
arch/arm/mach-mmp/pxa168.c
arch/arm/mach-omap2/Kconfig
arch/arm/mach-omap2/board-generic.c
arch/arm/mach-omap2/common.h
arch/arm/mach-omap2/irq.c
arch/arm/mach-omap2/pm.c
arch/arm/mach-vexpress/Kconfig
arch/arm/mach-vexpress/Makefile.boot
arch/arm/mach-vexpress/core.h
arch/arm/mach-vexpress/include/mach/debug-macro.S
arch/arm/mach-vexpress/include/mach/irqs.h
arch/arm/mach-vexpress/include/mach/motherboard.h
arch/arm/mach-vexpress/include/mach/uncompress.h
arch/arm/mach-vexpress/platsmp.c
arch/arm/mach-vexpress/v2m.c
arch/arm/plat-mxc/include/mach/common.h
arch/arm/plat-omap/Kconfig
arch/arm/plat-omap/omap_device.c
arch/avr32/mach-at32ap/at32ap700x.c
drivers/clocksource/tcb_clksrc.c
drivers/i2c/busses/i2c-pxa.c
drivers/misc/atmel_tclib.c
drivers/pcmcia/at91_cf.c
drivers/rtc/rtc-at91sam9.c
drivers/tty/serial/atmel_serial.c
drivers/tty/serial/pxa.c
drivers/usb/gadget/at91_udc.c
drivers/usb/gadget/atmel_usba_udc.c
drivers/usb/host/ohci-at91.c
drivers/watchdog/at91rm9200_wdt.c
include/linux/atmel_tc.h

diff --git a/Documentation/devicetree/bindings/arm/atmel-aic.txt b/Documentation/devicetree/bindings/arm/atmel-aic.txt
new file mode 100644 (file)
index 0000000..aabca4f
--- /dev/null
@@ -0,0 +1,38 @@
+* Advanced Interrupt Controller (AIC)
+
+Required properties:
+- compatible: Should be "atmel,<chip>-aic"
+- interrupt-controller: Identifies the node as an interrupt controller.
+- interrupt-parent: For single AIC system, it is an empty property.
+- #interrupt-cells: The number of cells to define the interrupts. It sould be 2.
+  The first cell is the IRQ number (aka "Peripheral IDentifier" on datasheet).
+  The second cell is used to specify flags:
+    bits[3:0] trigger type and level flags:
+      1 = low-to-high edge triggered.
+      2 = high-to-low edge triggered.
+      4 = active high level-sensitive.
+      8 = active low level-sensitive.
+      Valid combinations are 1, 2, 3, 4, 8.
+      Default flag for internal sources should be set to 4 (active high).
+- reg: Should contain AIC registers location and length
+
+Examples:
+       /*
+        * AIC
+        */
+       aic: interrupt-controller@fffff000 {
+               compatible = "atmel,at91rm9200-aic";
+               interrupt-controller;
+               interrupt-parent;
+               #interrupt-cells = <2>;
+               reg = <0xfffff000 0x200>;
+       };
+
+       /*
+        * An interrupt generating device that is wired to an AIC.
+        */
+       dma: dma-controller@ffffec00 {
+               compatible = "atmel,at91sam9g45-dma";
+               reg = <0xffffec00 0x200>;
+               interrupts = <21 4>;
+       };
diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
new file mode 100644 (file)
index 0000000..1aeaf6f
--- /dev/null
@@ -0,0 +1,32 @@
+Atmel AT91 device tree bindings.
+================================
+
+PIT Timer required properties:
+- compatible: Should be "atmel,at91sam9260-pit"
+- reg: Should contain registers location and length
+- interrupts: Should contain interrupt for the PIT which is the IRQ line
+  shared across all System Controller members.
+
+TC/TCLIB Timer required properties:
+- compatible: Should be "atmel,<chip>-pit".
+  <chip> can be "at91rm9200" or "at91sam9x5"
+- reg: Should contain registers location and length
+- interrupts: Should contain all interrupts for the TC block
+  Note that you can specify several interrupt cells if the TC
+  block has one interrupt per channel.
+
+Examples:
+
+One interrupt per TC block:
+       tcb0: timer@fff7c000 {
+               compatible = "atmel,at91rm9200-tcb";
+               reg = <0xfff7c000 0x100>;
+               interrupts = <18 4>;
+       };
+
+One interrupt per TC channel in a TC block:
+       tcb1: timer@fffdc000 {
+               compatible = "atmel,at91rm9200-tcb";
+               reg = <0xfffdc000 0x100>;
+               interrupts = <26 4 27 4 28 4>;
+       };
index 54bdddadf1cf66169b789e2ef53754eafd4bfcc6..bfbc771a65f8937124089c238fe6ac0dcaa96142 100644 (file)
@@ -28,3 +28,25 @@ Required root node properties:
 i.MX6 Quad SABRE Lite Board
 Required root node properties:
     - compatible = "fsl,imx6q-sabrelite", "fsl,imx6q";
+
+Generic i.MX boards
+-------------------
+
+No iomux setup is done for these boards, so this must have been configured
+by the bootloader for boards to work with the generic bindings.
+
+i.MX27 generic board
+Required root node properties:
+    - compatible = "fsl,imx27";
+
+i.MX51 generic board
+Required root node properties:
+    - compatible = "fsl,imx51";
+
+i.MX53 generic board
+Required root node properties:
+    - compatible = "fsl,imx53";
+
+i.MX6q generic board
+Required root node properties:
+    - compatible = "fsl,imx6q";
diff --git a/Documentation/devicetree/bindings/arm/mrvl.txt b/Documentation/devicetree/bindings/arm/mrvl.txt
new file mode 100644 (file)
index 0000000..d8de933
--- /dev/null
@@ -0,0 +1,6 @@
+Marvell Platforms Device Tree Bindings
+----------------------------------------------------
+
+PXA168 Aspenite Board
+Required root node properties:
+       - compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168";
diff --git a/Documentation/devicetree/bindings/arm/omap/intc.txt b/Documentation/devicetree/bindings/arm/omap/intc.txt
new file mode 100644 (file)
index 0000000..f2583e6
--- /dev/null
@@ -0,0 +1,27 @@
+* OMAP Interrupt Controller
+
+OMAP2/3 are using a TI interrupt controller that can support several
+configurable number of interrupts.
+
+Main node required properties:
+
+- compatible : should be:
+       "ti,omap2-intc"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The type shall be a <u32> and the value shall be 1.
+
+  The cell contains the interrupt number in the range [0-128].
+- ti,intc-size: Number of interrupts handled by the interrupt controller.
+- reg: physical base address and size of the intc registers map.
+
+Example:
+
+       intc: interrupt-controller@1 {
+               compatible = "ti,omap2-intc";
+               interrupt-controller;
+               #interrupt-cells = <1>;
+               ti,intc-size = <96>;
+               reg = <0x48200000 0x1000>;
+       };
+
diff --git a/Documentation/devicetree/bindings/arm/vexpress.txt b/Documentation/devicetree/bindings/arm/vexpress.txt
new file mode 100644 (file)
index 0000000..ec8b50c
--- /dev/null
@@ -0,0 +1,146 @@
+ARM Versatile Express boards family
+-----------------------------------
+
+ARM's Versatile Express platform consists of a motherboard and one
+or more daughterboards (tiles). The motherboard provides a set of
+peripherals. Processor and RAM "live" on the tiles.
+
+The motherboard and each core tile should be described by a separate
+Device Tree source file, with the tile's description including
+the motherboard file using a /include/ directive. As the motherboard
+can be initialized in one of two different configurations ("memory
+maps"), care must be taken to include the correct one.
+
+Required properties in the root node:
+- compatible value:
+       compatible = "arm,vexpress,<model>", "arm,vexpress";
+  where <model> is the full tile model name (as used in the tile's
+    Technical Reference Manual), eg.:
+    - for Coretile Express A5x2 (V2P-CA5s):
+       compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
+    - for Coretile Express A9x4 (V2P-CA9):
+       compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
+  If a tile comes in several variants or can be used in more then one
+  configuration, the compatible value should be:
+       compatible = "arm,vexpress,<model>,<variant>", \
+                               "arm,vexpress,<model>", "arm,vexpress";
+  eg:
+    - Coretile Express A15x2 (V2P-CA15) with Tech Chip 1:
+       compatible = "arm,vexpress,v2p-ca15,tc1", \
+                               "arm,vexpress,v2p-ca15", "arm,vexpress";
+    - LogicTile Express 13MG (V2F-2XV6) running Cortex-A7 (3 cores) SMM:
+       compatible = "arm,vexpress,v2f-2xv6,ca7x3", \
+                               "arm,vexpress,v2f-2xv6", "arm,vexpress";
+
+Optional properties in the root node:
+- tile model name (use name from the tile's Technical Reference
+  Manual, eg. "V2P-CA5s")
+       model = "<model>";
+- tile's HBI number (unique ARM's board model ID, visible on the
+  PCB's silkscreen) in hexadecimal transcription:
+       arm,hbi = <0xhbi>
+  eg:
+  - for Coretile Express A5x2 (V2P-CA5s) HBI-0191:
+       arm,hbi = <0x191>;
+  - Coretile Express A9x4 (V2P-CA9) HBI-0225:
+       arm,hbi = <0x225>;
+
+Top-level standard "cpus" node is required. It must contain a node
+with device_type = "cpu" property for every available core, eg.:
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a5";
+                       reg = <0>;
+               };
+       };
+
+The motherboard description file provides a single "motherboard" node
+using 2 address cells corresponding to the Static Memory Bus used
+between the motherboard and the tile. The first cell defines the Chip
+Select (CS) line number, the second cell address offset within the CS.
+All interrupt lines between the motherboard and the tile are active
+high and are described using single cell.
+
+Optional properties of the "motherboard" node:
+- motherboard's memory map variant:
+       arm,v2m-memory-map = "<name>";
+  where name is one of:
+  - "rs1" - for RS1 map (i.a. peripherals on CS3); this map is also
+            referred to as "ARM Cortex-A Series memory map":
+       arm,v2m-memory-map = "rs1";
+  When this property is missing, the motherboard is using the original
+  memory map (also known as the "Legacy memory map", primarily used
+  with the original CoreTile Express A9x4) with peripherals on CS7.
+
+Motherboard .dtsi files provide a set of labelled peripherals that
+can be used to obtain required phandle in the tile's "aliases" node:
+- UARTs, note that the numbers correspond to the physical connectors
+  on the motherboard's back panel:
+       v2m_serial0, v2m_serial1, v2m_serial2 and v2m_serial3
+- I2C controllers:
+       v2m_i2c_dvi and v2m_i2c_pcie
+- SP804 timers:
+       v2m_timer01 and v2m_timer23
+
+Current Linux implementation requires a "arm,v2m_timer" alias
+pointing at one of the motherboard's SP804 timers, if it is to be
+used as the system timer. This alias should be defined in the
+motherboard files.
+
+The tile description must define "ranges", "interrupt-map-mask" and
+"interrupt-map" properties to translate the motherboard's address
+and interrupt space into one used by the tile's processor.
+
+Abbreviated example:
+
+/dts-v1/;
+
+/ {
+       model = "V2P-CA5s";
+       arm,hbi = <0x225>;
+       compatible = "arm,vexpress-v2p-ca5s", "arm,vexpress";
+       interrupt-parent = <&gic>;
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       chosen { };
+
+       aliases {
+               serial0 = &v2m_serial0;
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a5";
+                       reg = <0>;
+               };
+       };
+
+       gic: interrupt-controller@2c001000 {
+               compatible = "arm,cortex-a9-gic";
+               #interrupt-cells = <3>;
+               #address-cells = <0>;
+               interrupt-controller;
+               reg = <0x2c001000 0x1000>,
+                     <0x2c000100 0x100>;
+       };
+
+       motherboard {
+               /* CS0 is visible at 0x08000000 */
+               ranges = <0 0 0x08000000 0x04000000>;
+               interrupt-map-mask = <0 0 63>;
+               /* Active high IRQ 0 is connected to GIC's SPI0 */
+               interrupt-map = <0 0 0 &gic 0 0 4>;
+       };
+};
+
+/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/Documentation/devicetree/bindings/gpio/gpio_atmel.txt b/Documentation/devicetree/bindings/gpio/gpio_atmel.txt
new file mode 100644 (file)
index 0000000..66efc80
--- /dev/null
@@ -0,0 +1,20 @@
+* Atmel GPIO controller (PIO)
+
+Required properties:
+- compatible: "atmel,<chip>-gpio", where <chip> is at91rm9200 or at91sam9x5.
+- reg: Should contain GPIO controller registers location and length
+- interrupts: Should be the port interrupt shared by all the pins.
+- #gpio-cells: Should be two.  The first cell is the pin number and
+  the second cell is used to specify optional parameters (currently
+  unused).
+- gpio-controller: Marks the device node as a GPIO controller.
+
+Example:
+       pioA: gpio@fffff200 {
+               compatible = "atmel,at91rm9200-gpio";
+               reg = <0xfffff200 0x100>;
+               interrupts = <2 4>;
+               #gpio-cells = <2>;
+               gpio-controller;
+       };
+
diff --git a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
new file mode 100644 (file)
index 0000000..1e34cfe
--- /dev/null
@@ -0,0 +1,23 @@
+* Marvell PXA GPIO controller
+
+Required properties:
+- compatible : Should be "mrvl,pxa-gpio" or "mrvl,mmp-gpio"
+- reg : Address and length of the register set for the device
+- interrupts : Should be the port interrupt shared by all gpio pins, if
+- interrupt-name : Should be the name of irq resource.
+  one number.
+- gpio-controller : Marks the device node as a gpio controller.
+- #gpio-cells : Should be one.  It is the pin number.
+
+Example:
+
+       gpio: gpio@d4019000 {
+               compatible = "mrvl,mmp-gpio", "mrvl,pxa-gpio";
+               reg = <0xd4019000 0x1000>;
+               interrupts = <49>, <17>, <18>;
+               interrupt-name = "gpio_mux", "gpio0", "gpio1";
+               gpio-controller;
+               #gpio-cells = <1>;
+               interrupt-controller;
+               #interrupt-cells = <1>;
+      };
diff --git a/Documentation/devicetree/bindings/i2c/mrvl-i2c.txt b/Documentation/devicetree/bindings/i2c/mrvl-i2c.txt
new file mode 100644 (file)
index 0000000..071eb3c
--- /dev/null
@@ -0,0 +1,37 @@
+* I2C
+
+Required properties :
+
+ - reg : Offset and length of the register set for the device
+ - compatible : should be "mrvl,mmp-twsi" where CHIP is the name of a
+   compatible processor, e.g. pxa168, pxa910, mmp2, mmp3.
+   For the pxa2xx/pxa3xx, an additional node "mrvl,pxa-i2c" is required
+   as shown in the example below.
+
+Recommended properties :
+
+ - interrupts : <a b> where a is the interrupt number and b is a
+   field that represents an encoding of the sense and level
+   information for the interrupt.  This should be encoded based on
+   the information in section 2) depending on the type of interrupt
+   controller you have.
+ - interrupt-parent : the phandle for the interrupt controller that
+   services interrupts for this device.
+ - mrvl,i2c-polling : Disable interrupt of i2c controller. Polling
+   status register of i2c controller instead.
+ - mrvl,i2c-fast-mode : Enable fast mode of i2c controller.
+
+Examples:
+       twsi1: i2c@d4011000 {
+               compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
+               reg = <0xd4011000 0x1000>;
+               interrupts = <7>;
+               mrvl,i2c-fast-mode;
+       };
+       
+       twsi2: i2c@d4025000 {
+               compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
+               reg = <0xd4025000 0x1000>;
+               interrupts = <58>;
+       };
+
diff --git a/Documentation/devicetree/bindings/rtc/sa1100-rtc.txt b/Documentation/devicetree/bindings/rtc/sa1100-rtc.txt
new file mode 100644 (file)
index 0000000..0cda19a
--- /dev/null
@@ -0,0 +1,17 @@
+* Marvell Real Time Clock controller
+
+Required properties:
+- compatible: should be "mrvl,sa1100-rtc"
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- interrupts: Should be two. The first interrupt number is the rtc alarm
+  interrupt and the second interrupt number is the rtc hz interrupt.
+- interrupt-names: Assign name of irq resource.
+
+Example:
+       rtc: rtc@d4010000 {
+               compatible = "mrvl,mmp-rtc";
+               reg = <0xd4010000 0x1000>;
+               interrupts = <5>, <6>;
+               interrupt-name = "rtc 1Hz", "rtc alarm";
+       };
diff --git a/Documentation/devicetree/bindings/serial/mrvl-serial.txt b/Documentation/devicetree/bindings/serial/mrvl-serial.txt
new file mode 100644 (file)
index 0000000..d744340
--- /dev/null
@@ -0,0 +1,4 @@
+PXA UART controller
+
+Required properties:
+- compatible : should be "mrvl,mmp-uart" or "mrvl,pxa-uart".
index 8ef416a3a551c8315b9eb06ffdd7bbabd0d7a626..94422601ea5b2e6dfb57169ceb760fce8893c5fe 100644 (file)
@@ -325,6 +325,7 @@ config ARCH_AT91
        select ARCH_REQUIRE_GPIOLIB
        select HAVE_CLK
        select CLKDEV_LOOKUP
+       select IRQ_DOMAIN
        help
          This enables support for systems based on the Atmel AT91RM9200,
          AT91SAM9 processors.
diff --git a/arch/arm/boot/dts/am3517_mt_ventoux.dts b/arch/arm/boot/dts/am3517_mt_ventoux.dts
new file mode 100644 (file)
index 0000000..5eb26d7
--- /dev/null
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2011 Ilya Yanok, EmCraft Systems
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+/include/ "omap3.dtsi"
+
+/ {
+       model = "TeeJet Mt.Ventoux";
+       compatible = "teejet,mt_ventoux", "ti,omap3";
+
+       memory {
+               device_type = "memory";
+               reg = <0x80000000 0x10000000>; /* 256 MB */
+       };
+
+       /* AM35xx doesn't have IVA */
+       soc {
+               iva {
+                       status = "disabled";
+               };
+       };
+};
index 07603b8c95037b10d85739e2dfcafc77d62be7c7..a100db03ec90f511dda6f9cbe45ea9ab96c73401 100644 (file)
                serial4 = &usart3;
                serial5 = &usart4;
                serial6 = &usart5;
+               gpio0 = &pioA;
+               gpio1 = &pioB;
+               gpio2 = &pioC;
+               tcb0 = &tcb0;
+               tcb1 = &tcb1;
        };
        cpus {
                cpu@0 {
                        ranges;
 
                        aic: interrupt-controller@fffff000 {
-                               #interrupt-cells = <1>;
+                               #interrupt-cells = <2>;
                                compatible = "atmel,at91rm9200-aic";
                                interrupt-controller;
                                interrupt-parent;
                                reg = <0xfffff000 0x200>;
                        };
 
+                       pit: timer@fffffd30 {
+                               compatible = "atmel,at91sam9260-pit";
+                               reg = <0xfffffd30 0xf>;
+                               interrupts = <1 4>;
+                       };
+
+                       tcb0: timer@fffa0000 {
+                               compatible = "atmel,at91rm9200-tcb";
+                               reg = <0xfffa0000 0x100>;
+                               interrupts = <17 4 18 4 19 4>;
+                       };
+
+                       tcb1: timer@fffdc000 {
+                               compatible = "atmel,at91rm9200-tcb";
+                               reg = <0xfffdc000 0x100>;
+                               interrupts = <26 4 27 4 28 4>;
+                       };
+
+                       pioA: gpio@fffff400 {
+                               compatible = "atmel,at91rm9200-gpio";
+                               reg = <0xfffff400 0x100>;
+                               interrupts = <2 4>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                               interrupt-controller;
+                       };
+
+                       pioB: gpio@fffff600 {
+                               compatible = "atmel,at91rm9200-gpio";
+                               reg = <0xfffff600 0x100>;
+                               interrupts = <3 4>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                               interrupt-controller;
+                       };
+
+                       pioC: gpio@fffff800 {
+                               compatible = "atmel,at91rm9200-gpio";
+                               reg = <0xfffff800 0x100>;
+                               interrupts = <4 4>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                               interrupt-controller;
+                       };
+
                        dbgu: serial@fffff200 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfffff200 0x200>;
-                               interrupts = <1>;
+                               interrupts = <1 4>;
                                status = "disabled";
                        };
 
                        usart0: serial@fffb0000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfffb0000 0x200>;
-                               interrupts = <6>;
+                               interrupts = <6 4>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
                                status = "disabled";
                        usart1: serial@fffb4000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfffb4000 0x200>;
-                               interrupts = <7>;
+                               interrupts = <7 4>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
                                status = "disabled";
                        usart2: serial@fffb8000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfffb8000 0x200>;
-                               interrupts = <8>;
+                               interrupts = <8 4>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
                                status = "disabled";
                        usart3: serial@fffd0000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfffd0000 0x200>;
-                               interrupts = <23>;
+                               interrupts = <23 4>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
                                status = "disabled";
                        usart4: serial@fffd4000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfffd4000 0x200>;
-                               interrupts = <24>;
+                               interrupts = <24 4>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
                                status = "disabled";
                        usart5: serial@fffd8000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfffd8000 0x200>;
-                               interrupts = <25>;
+                               interrupts = <25 4>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
                                status = "disabled";
                        macb0: ethernet@fffc4000 {
                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                reg = <0xfffc4000 0x100>;
-                               interrupts = <21>;
+                               interrupts = <21 4>;
                                status = "disabled";
                        };
                };
index fffa005300a4274fa29e2c74e610333ae729ac11..f779667159b1aec4949d59c99c01e51f9a2bef43 100644 (file)
                serial2 = &usart1;
                serial3 = &usart2;
                serial4 = &usart3;
+               gpio0 = &pioA;
+               gpio1 = &pioB;
+               gpio2 = &pioC;
+               gpio3 = &pioD;
+               gpio4 = &pioE;
+               tcb0 = &tcb0;
+               tcb1 = &tcb1;
        };
        cpus {
                cpu@0 {
                        ranges;
 
                        aic: interrupt-controller@fffff000 {
-                               #interrupt-cells = <1>;
+                               #interrupt-cells = <2>;
                                compatible = "atmel,at91rm9200-aic";
                                interrupt-controller;
                                interrupt-parent;
                                reg = <0xfffff000 0x200>;
                        };
 
+                       pit: timer@fffffd30 {
+                               compatible = "atmel,at91sam9260-pit";
+                               reg = <0xfffffd30 0xf>;
+                               interrupts = <1 4>;
+                       };
+
+
+                       tcb0: timer@fff7c000 {
+                               compatible = "atmel,at91rm9200-tcb";
+                               reg = <0xfff7c000 0x100>;
+                               interrupts = <18 4>;
+                       };
+
+                       tcb1: timer@fffd4000 {
+                               compatible = "atmel,at91rm9200-tcb";
+                               reg = <0xfffd4000 0x100>;
+                               interrupts = <18 4>;
+                       };
+
                        dma: dma-controller@ffffec00 {
                                compatible = "atmel,at91sam9g45-dma";
                                reg = <0xffffec00 0x200>;
-                               interrupts = <21>;
+                               interrupts = <21 4>;
+                       };
+
+                       pioA: gpio@fffff200 {
+                               compatible = "atmel,at91rm9200-gpio";
+                               reg = <0xfffff200 0x100>;
+                               interrupts = <2 4>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                               interrupt-controller;
+                       };
+
+                       pioB: gpio@fffff400 {
+                               compatible = "atmel,at91rm9200-gpio";
+                               reg = <0xfffff400 0x100>;
+                               interrupts = <3 4>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                               interrupt-controller;
+                       };
+
+                       pioC: gpio@fffff600 {
+                               compatible = "atmel,at91rm9200-gpio";
+                               reg = <0xfffff600 0x100>;
+                               interrupts = <4 4>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                               interrupt-controller;
+                       };
+
+                       pioD: gpio@fffff800 {
+                               compatible = "atmel,at91rm9200-gpio";
+                               reg = <0xfffff800 0x100>;
+                               interrupts = <5 4>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                               interrupt-controller;
+                       };
+
+                       pioE: gpio@fffffa00 {
+                               compatible = "atmel,at91rm9200-gpio";
+                               reg = <0xfffffa00 0x100>;
+                               interrupts = <5 4>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                               interrupt-controller;
                        };
 
                        dbgu: serial@ffffee00 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xffffee00 0x200>;
-                               interrupts = <1>;
+                               interrupts = <1 4>;
                                status = "disabled";
                        };
 
                        usart0: serial@fff8c000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfff8c000 0x200>;
-                               interrupts = <7>;
+                               interrupts = <7 4>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
                                status = "disabled";
                        usart1: serial@fff90000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfff90000 0x200>;
-                               interrupts = <8>;
+                               interrupts = <8 4>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
                                status = "disabled";
                        usart2: serial@fff94000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfff94000 0x200>;
-                               interrupts = <9>;
+                               interrupts = <9 4>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
                                status = "disabled";
                        usart3: serial@fff98000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfff98000 0x200>;
-                               interrupts = <10>;
+                               interrupts = <10 4>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
                                status = "disabled";
                        macb0: ethernet@fffbc000 {
                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                reg = <0xfffbc000 0x100>;
-                               interrupts = <25>;
+                               interrupts = <25 4>;
                                status = "disabled";
                        };
                };
index a387e7704ce1e42d2647a19a85311668507a861d..15e25f903cadad9b47a570c0e7edc3216ce2fa36 100644 (file)
                        };
                };
        };
+
+       leds {
+               compatible = "gpio-leds";
+
+               d8 {
+                       label = "d8";
+                       gpios = <&pioD 30 0>;
+                       linux,default-trigger = "heartbeat";
+               };
+
+               d6 {
+                       label = "d6";
+                       gpios = <&pioD 0 1>;
+                       linux,default-trigger = "nand-disk";
+               };
+
+               d7 {
+                       label = "d7";
+                       gpios = <&pioD 31 1>;
+                       linux,default-trigger = "mmc0";
+               };
+       };
+
+       gpio_keys {
+               compatible = "gpio-keys";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               left_click {
+                       label = "left_click";
+                       gpios = <&pioB 6 1>;
+                       linux,code = <272>;
+                       gpio-key,wakeup;
+               };
+
+               right_click {
+                       label = "right_click";
+                       gpios = <&pioB 7 1>;
+                       linux,code = <273>;
+                       gpio-key,wakeup;
+               };
+
+               left {
+                       label = "Joystick Left";
+                       gpios = <&pioB 14 1>;
+                       linux,code = <105>;
+               };
+
+               right {
+                       label = "Joystick Right";
+                       gpios = <&pioB 15 1>;
+                       linux,code = <106>;
+               };
+
+               up {
+                       label = "Joystick Up";
+                       gpios = <&pioB 16 1>;
+                       linux,code = <103>;
+               };
+
+               down {
+                       label = "Joystick Down";
+                       gpios = <&pioB 17 1>;
+                       linux,code = <108>;
+               };
+
+               enter {
+                       label = "Joystick Press";
+                       gpios = <&pioB 18 1>;
+                       linux,code = <28>;
+               };
+       };
 };
index e91391f50730d8d686c98c6578d8bfac0689509b..a02e636d8a5751f2d7fb46570d2ddc6969071f95 100644 (file)
                        };
 
                        pioA: gpio@fffff400 {
-                               compatible = "atmel,at91rm9200-gpio";
+                               compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                reg = <0xfffff400 0x100>;
                                interrupts = <2 4>;
                                #gpio-cells = <2>;
                                gpio-controller;
+                               interrupt-controller;
                        };
 
                        pioB: gpio@fffff600 {
-                               compatible = "atmel,at91rm9200-gpio";
+                               compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                reg = <0xfffff600 0x100>;
                                interrupts = <2 4>;
                                #gpio-cells = <2>;
                                gpio-controller;
+                               interrupt-controller;
                        };
 
                        pioC: gpio@fffff800 {
-                               compatible = "atmel,at91rm9200-gpio";
+                               compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                reg = <0xfffff800 0x100>;
                                interrupts = <3 4>;
                                #gpio-cells = <2>;
                                gpio-controller;
+                               interrupt-controller;
                        };
 
                        pioD: gpio@fffffa00 {
-                               compatible = "atmel,at91rm9200-gpio";
+                               compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                reg = <0xfffffa00 0x100>;
                                interrupts = <3 4>;
                                #gpio-cells = <2>;
                                gpio-controller;
+                               interrupt-controller;
                        };
 
                        dbgu: serial@fffff200 {
index 4ab5a77f4afca0518e846e37c22d86128c96d318..64ae3e890259e56ed7ab626b8e402620ab2990bb 100644 (file)
        memory@20000000 {
                reg = <0x20000000 0x8000000>;
        };
+
+       leds {
+               compatible = "gpio-leds";
+
+               pb18 {
+                       label = "pb18";
+                       gpios = <&pioB 18 1>;
+                       linux,default-trigger = "heartbeat";
+               };
+
+               pd21 {
+                       label = "pd21";
+                       gpios = <&pioD 21 0>;
+               };
+       };
 };
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts
new file mode 100644 (file)
index 0000000..a51a08f
--- /dev/null
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2012 Sascha Hauer, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "imx27.dtsi"
+
+/ {
+       model = "Phytec pcm038";
+       compatible = "phytec,imx27-pcm038", "fsl,imx27";
+
+       memory {
+               reg = <0x0 0x0>;
+       };
+
+       soc {
+               aipi@10000000 { /* aipi */
+
+                       wdog@10002000 {
+                               status = "okay";
+                       };
+
+                       uart@1000a000 {
+                               fsl,uart-has-rtscts;
+                               status = "okay";
+                       };
+
+                       uart@1000b000 {
+                               fsl,uart-has-rtscts;
+                               status = "okay";
+                       };
+
+                       uart@1000c000 {
+                               fsl,uart-has-rtscts;
+                               status = "okay";
+                       };
+
+                       fec@1002b000 {
+                               status = "okay";
+                       };
+
+                       i2c@1001d000 {
+                               clock-frequency = <400000>;
+                               status = "okay";
+                               at24@4c {
+                                       compatible = "at,24c32";
+                                       pagesize = <32>;
+                                       reg = <0x52>;
+                               };
+                               pcf8563@51 {
+                                       compatible = "nxp,pcf8563";
+                                       reg = <0x51>;
+                               };
+                               lm75@4a {
+                                       compatible = "national,lm75";
+                                       reg = <0x4a>;
+                               };
+                       };
+               };
+       };
+
+       nor_flash@c0000000 {
+               compatible = "cfi-flash";
+               bank-width = <2>;
+               reg = <0xc0000000 0x02000000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+       };
+};
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
new file mode 100644 (file)
index 0000000..bc5e7d5
--- /dev/null
@@ -0,0 +1,217 @@
+/*
+ * Copyright 2012 Sascha Hauer, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+       aliases {
+               serial0 = &uart1;
+               serial1 = &uart2;
+               serial2 = &uart3;
+               serial3 = &uart4;
+               serial4 = &uart5;
+               serial5 = &uart6;
+       };
+
+       avic: avic-interrupt-controller@e0000000 {
+               compatible = "fsl,imx27-avic", "fsl,avic";
+               interrupt-controller;
+               #interrupt-cells = <1>;
+               reg = <0x10040000 0x1000>;
+       };
+
+       clocks {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               osc26m {
+                       compatible = "fsl,imx-osc26m", "fixed-clock";
+                       clock-frequency = <26000000>;
+               };
+       };
+
+       soc {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "simple-bus";
+               interrupt-parent = <&avic>;
+               ranges;
+
+               aipi@10000000 { /* AIPI1 */
+                       compatible = "fsl,aipi-bus", "simple-bus";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       reg = <0x10000000 0x10000000>;
+                       ranges;
+
+                       wdog@10002000 {
+                               compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
+                               reg = <0x10002000 0x4000>;
+                               interrupts = <27>;
+                               status = "disabled";
+                       };
+
+                       uart1: uart@1000a000 {
+                               compatible = "fsl,imx27-uart", "fsl,imx21-uart";
+                               reg = <0x1000a000 0x1000>;
+                               interrupts = <20>;
+                               status = "disabled";
+                       };
+
+                       uart2: uart@1000b000 {
+                               compatible = "fsl,imx27-uart", "fsl,imx21-uart";
+                               reg = <0x1000b000 0x1000>;
+                               interrupts = <19>;
+                               status = "disabled";
+                       };
+
+                       uart3: uart@1000c000 {
+                               compatible = "fsl,imx27-uart", "fsl,imx21-uart";
+                               reg = <0x1000c000 0x1000>;
+                               interrupts = <18>;
+                               status = "disabled";
+                       };
+
+                       uart4: uart@1000d000 {
+                               compatible = "fsl,imx27-uart", "fsl,imx21-uart";
+                               reg = <0x1000d000 0x1000>;
+                               interrupts = <17>;
+                               status = "disabled";
+                       };
+
+                       cspi1: cspi@1000e000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,imx27-cspi";
+                               reg = <0x1000e000 0x1000>;
+                               interrupts = <16>;
+                               status = "disabled";
+                       };
+
+                       cspi2: cspi@1000f000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,imx27-cspi";
+                               reg = <0x1000f000 0x1000>;
+                               interrupts = <15>;
+                               status = "disabled";
+                       };
+
+                       i2c1: i2c@10012000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,imx27-i2c", "fsl,imx1-i2c";
+                               reg = <0x10012000 0x1000>;
+                               interrupts = <12>;
+                               status = "disabled";
+                       };
+
+                       gpio1: gpio@10015000 {
+                               compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+                               reg = <0x10015000 0x100>;
+                               interrupts = <8>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+
+                       gpio2: gpio@10015100 {
+                               compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+                               reg = <0x10015100 0x100>;
+                               interrupts = <8>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+
+                       gpio3: gpio@10015200 {
+                               compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+                               reg = <0x10015200 0x100>;
+                               interrupts = <8>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+
+                       gpio4: gpio@10015300 {
+                               compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+                               reg = <0x10015300 0x100>;
+                               interrupts = <8>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+
+                       gpio5: gpio@10015400 {
+                               compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+                               reg = <0x10015400 0x100>;
+                               interrupts = <8>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+
+                       gpio6: gpio@10015500 {
+                               compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+                               reg = <0x10015500 0x100>;
+                               interrupts = <8>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+
+                       cspi3: cspi@10017000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,imx27-cspi";
+                               reg = <0x10017000 0x1000>;
+                               interrupts = <6>;
+                               status = "disabled";
+                       };
+
+                       uart5: uart@1001b000 {
+                               compatible = "fsl,imx27-uart", "fsl,imx21-uart";
+                               reg = <0x1001b000 0x1000>;
+                               interrupts = <49>;
+                               status = "disabled";
+                       };
+
+                       uart6: uart@1001c000 {
+                               compatible = "fsl,imx27-uart", "fsl,imx21-uart";
+                               reg = <0x1001c000 0x1000>;
+                               interrupts = <48>;
+                               status = "disabled";
+                       };
+
+                       i2c2: i2c@1001d000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,imx27-i2c", "fsl,imx1-i2c";
+                               reg = <0x1001d000 0x1000>;
+                               interrupts = <1>;
+                               status = "disabled";
+                       };
+
+                       fec: fec@1002b000 {
+                               compatible = "fsl,imx27-fec";
+                               reg = <0x1002b000 0x4000>;
+                               interrupts = <50>;
+                               status = "disabled";
+                       };
+               };
+       };
+};
index 564cb8c19f1506363e25282f54a58d792b1bc9ef..9949e6060dee0e185ee865453aa70b83f312ebbb 100644 (file)
                                                compatible = "fsl,mc13892";
                                                spi-max-frequency = <6000000>;
                                                reg = <0>;
-                                               mc13xxx-irq-gpios = <&gpio1 8 0>;
-                                               fsl,mc13xxx-uses-regulator;
+                                               interrupt-parent = <&gpio1>;
+                                               interrupts = <8>;
+
+                                               regulators {
+                                                       sw1_reg: sw1 {
+                                                               regulator-min-microvolt = <600000>;
+                                                               regulator-max-microvolt = <1375000>;
+                                                               regulator-boot-on;
+                                                               regulator-always-on;
+                                                       };
+
+                                                       sw2_reg: sw2 {
+                                                               regulator-min-microvolt = <900000>;
+                                                               regulator-max-microvolt = <1850000>;
+                                                               regulator-boot-on;
+                                                               regulator-always-on;
+                                                       };
+
+                                                       sw3_reg: sw3 {
+                                                               regulator-min-microvolt = <1100000>;
+                                                               regulator-max-microvolt = <1850000>;
+                                                               regulator-boot-on;
+                                                               regulator-always-on;
+                                                       };
+
+                                                       sw4_reg: sw4 {
+                                                               regulator-min-microvolt = <1100000>;
+                                                               regulator-max-microvolt = <1850000>;
+                                                               regulator-boot-on;
+                                                               regulator-always-on;
+                                                       };
+
+                                                       vpll_reg: vpll {
+                                                               regulator-min-microvolt = <1050000>;
+                                                               regulator-max-microvolt = <1800000>;
+                                                               regulator-boot-on;
+                                                               regulator-always-on;
+                                                       };
+
+                                                       vdig_reg: vdig {
+                                                               regulator-min-microvolt = <1650000>;
+                                                               regulator-max-microvolt = <1650000>;
+                                                               regulator-boot-on;
+                                                       };
+
+                                                       vsd_reg: vsd {
+                                                               regulator-min-microvolt = <1800000>;
+                                                               regulator-max-microvolt = <3150000>;
+                                                       };
+
+                                                       vusb2_reg: vusb2 {
+                                                               regulator-min-microvolt = <2400000>;
+                                                               regulator-max-microvolt = <2775000>;
+                                                               regulator-boot-on;
+                                                               regulator-always-on;
+                                                       };
+
+                                                       vvideo_reg: vvideo {
+                                                               regulator-min-microvolt = <2775000>;
+                                                               regulator-max-microvolt = <2775000>;
+                                                       };
+
+                                                       vaudio_reg: vaudio {
+                                                               regulator-min-microvolt = <2300000>;
+                                                               regulator-max-microvolt = <3000000>;
+                                                       };
+
+                                                       vcam_reg: vcam {
+                                                               regulator-min-microvolt = <2500000>;
+                                                               regulator-max-microvolt = <3000000>;
+                                                       };
+
+                                                       vgen1_reg: vgen1 {
+                                                               regulator-min-microvolt = <1200000>;
+                                                               regulator-max-microvolt = <1200000>;
+                                                       };
+
+                                                       vgen2_reg: vgen2 {
+                                                               regulator-min-microvolt = <1200000>;
+                                                               regulator-max-microvolt = <3150000>;
+                                                               regulator-always-on;
+                                                       };
+
+                                                       vgen3_reg: vgen3 {
+                                                               regulator-min-microvolt = <1800000>;
+                                                               regulator-max-microvolt = <2900000>;
+                                                               regulator-always-on;
+                                                       };
+                                               };
                                        };
 
                                        flash: at45db321d@1 {
index c3977e0478b9a1ba7f9376d827fb377910f1275a..ce1c8238c8975c6b84f72304f7ff8ae68dda8c88 100644 (file)
                        usdhc@02198000 { /* uSDHC3 */
                                cd-gpios = <&gpio6 11 0>;
                                wp-gpios = <&gpio6 14 0>;
+                               vmmc-supply = <&reg_3p3v>;
                                status = "okay";
                        };
 
                        usdhc@0219c000 { /* uSDHC4 */
                                fsl,card-wired;
+                               vmmc-supply = <&reg_3p3v>;
                                status = "okay";
                        };
 
                };
        };
 
+       regulators {
+               compatible = "simple-bus";
+
+               reg_3p3v: 3p3v {
+                       compatible = "regulator-fixed";
+                       regulator-name = "3P3V";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+                       regulator-always-on;
+               };
+       };
+
        leds {
                compatible = "gpio-leds";
 
index 08d920de72868a33347091a9d5f09dbc2147994d..4663a4e5a285dab5232c6bd285c17b6f2136a063 100644 (file)
                        usdhc@02198000 { /* uSDHC3 */
                                cd-gpios = <&gpio7 0 0>;
                                wp-gpios = <&gpio7 1 0>;
+                               vmmc-supply = <&reg_3p3v>;
                                status = "okay";
                        };
 
                        usdhc@0219c000 { /* uSDHC4 */
                                cd-gpios = <&gpio2 6 0>;
                                wp-gpios = <&gpio2 7 0>;
+                               vmmc-supply = <&reg_3p3v>;
                                status = "okay";
                        };
 
                        uart2: uart@021e8000 {
                                status = "okay";
                        };
+
+                       i2c@021a0000 { /* I2C1 */
+                               status = "okay";
+                               clock-frequency = <100000>;
+
+                               codec: sgtl5000@0a {
+                                       compatible = "fsl,sgtl5000";
+                                       reg = <0x0a>;
+                                       VDDA-supply = <&reg_2p5v>;
+                                       VDDIO-supply = <&reg_3p3v>;
+                               };
+                       };
+               };
+       };
+
+       regulators {
+               compatible = "simple-bus";
+
+               reg_2p5v: 2p5v {
+                       compatible = "regulator-fixed";
+                       regulator-name = "2P5V";
+                       regulator-min-microvolt = <2500000>;
+                       regulator-max-microvolt = <2500000>;
+                       regulator-always-on;
+               };
+
+               reg_3p3v: 3p3v {
+                       compatible = "regulator-fixed";
+                       regulator-name = "3P3V";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+                       regulator-always-on;
                };
        };
 };
index 9486be62bcddcd4674c9f0daa7e9f0f7b86f8147..9f72cd4cf3084d6aae6e4f3b4bd17a261d89e296 100644 (file)
        model = "TI OMAP3 BeagleBoard";
        compatible = "ti,omap3-beagle", "ti,omap3";
 
-       /*
-        * Since the initial device tree board file does not create any
-        * devices (MMC, network...), the only way to boot is to provide a
-        * ramdisk.
-        */
-       chosen {
-               bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug earlyprintk";
-       };
-
        memory {
                device_type = "memory";
                reg = <0x80000000 0x20000000>; /* 512 MB */
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
new file mode 100644 (file)
index 0000000..2eee16e
--- /dev/null
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+/include/ "omap3.dtsi"
+
+/ {
+       model = "TI OMAP3 EVM (OMAP3530, AM/DM37x)";
+       compatible = "ti,omap3-evm", "ti,omap3";
+
+       memory {
+               device_type = "memory";
+               reg = <0x80000000 0x10000000>; /* 256 MB */
+       };
+};
index 216c3317461d6dc6310571cd070ac7d952a38033..c6121357c1ebc95c29dd29e76f78d9972441e216 100644 (file)
                ranges;
                ti,hwmods = "l3_main";
 
-               intc: interrupt-controller@1 {
-                       compatible = "ti,omap3-intc";
+               intc: interrupt-controller@48200000 {
+                       compatible = "ti,omap2-intc";
                        interrupt-controller;
                        #interrupt-cells = <1>;
+                       ti,intc-size = <96>;
+                       reg = <0x48200000 0x1000>;
                };
 
-               uart1: serial@0x4806a000 {
+               uart1: serial@4806a000 {
                        compatible = "ti,omap3-uart";
                        ti,hwmods = "uart1";
                        clock-frequency = <48000000>;
                };
 
-               uart2: serial@0x4806c000 {
+               uart2: serial@4806c000 {
                        compatible = "ti,omap3-uart";
                        ti,hwmods = "uart2";
                        clock-frequency = <48000000>;
                };
 
-               uart3: serial@0x49020000 {
+               uart3: serial@49020000 {
                        compatible = "ti,omap3-uart";
                        ti,hwmods = "uart3";
                        clock-frequency = <48000000>;
                };
 
-               uart4: serial@0x49042000 {
+               uart4: serial@49042000 {
                        compatible = "ti,omap3-uart";
                        ti,hwmods = "uart4";
                        clock-frequency = <48000000>;
                };
+
+               i2c1: i2c@48070000 {
+                       compatible = "ti,omap3-i2c";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       ti,hwmods = "i2c1";
+               };
+
+               i2c2: i2c@48072000 {
+                       compatible = "ti,omap3-i2c";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       ti,hwmods = "i2c2";
+               };
+
+               i2c3: i2c@48060000 {
+                       compatible = "ti,omap3-i2c";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       ti,hwmods = "i2c3";
+               };
        };
 };
index c7026578ce7d6ef25b22f167ec5265918a5d6c8b..9755ad5917f8b75da64d2aebcd5f79637ad0054d 100644 (file)
        model = "TI OMAP4 PandaBoard";
        compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4";
 
-       /*
-        * Since the initial device tree board file does not create any
-        * devices (MMC, network...), the only way to boot is to provide a
-        * ramdisk.
-        */
-       chosen {
-               bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug";
-       };
-
        memory {
                device_type = "memory";
                reg = <0x80000000 0x40000000>; /* 1 GB */
index 066e28c90328f252639d4d2c1de6b76e2a497a18..63c6b2b2bf42cdf5ac4d595069d3fbb903322b55 100644 (file)
        model = "TI OMAP4 SDP board";
        compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4";
 
-       /*
-        * Since the initial device tree board file does not create any
-        * devices (MMC, network...), the only way to boot is to provide a
-        * ramdisk.
-        */
-       chosen {
-               bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug";
-       };
-
        memory {
                device_type = "memory";
                reg = <0x80000000 0x40000000>; /* 1 GB */
index e8fe75fac7c5e727f135721c1183feef0c89d2b1..3d35559e77bc098b220e2dab2360c86a5f156be1 100644 (file)
                gic: interrupt-controller@48241000 {
                        compatible = "arm,cortex-a9-gic";
                        interrupt-controller;
-                       #interrupt-cells = <1>;
+                       #interrupt-cells = <3>;
                        reg = <0x48241000 0x1000>,
                              <0x48240100 0x0100>;
                };
 
-               uart1: serial@0x4806a000 {
+               uart1: serial@4806a000 {
                        compatible = "ti,omap4-uart";
                        ti,hwmods = "uart1";
                        clock-frequency = <48000000>;
                };
 
-               uart2: serial@0x4806c000 {
+               uart2: serial@4806c000 {
                        compatible = "ti,omap4-uart";
                        ti,hwmods = "uart2";
                        clock-frequency = <48000000>;
                };
 
-               uart3: serial@0x48020000 {
+               uart3: serial@48020000 {
                        compatible = "ti,omap4-uart";
                        ti,hwmods = "uart3";
                        clock-frequency = <48000000>;
                };
 
-               uart4: serial@0x4806e000 {
+               uart4: serial@4806e000 {
                        compatible = "ti,omap4-uart";
                        ti,hwmods = "uart4";
                        clock-frequency = <48000000>;
                };
+
+               i2c1: i2c@48070000 {
+                       compatible = "ti,omap4-i2c";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       ti,hwmods = "i2c1";
+               };
+
+               i2c2: i2c@48072000 {
+                       compatible = "ti,omap4-i2c";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       ti,hwmods = "i2c2";
+               };
+
+               i2c3: i2c@48060000 {
+                       compatible = "ti,omap4-i2c";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       ti,hwmods = "i2c3";
+               };
+
+               i2c4: i2c@48350000 {
+                       compatible = "ti,omap4-i2c";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       ti,hwmods = "i2c4";
+               };
        };
 };
diff --git a/arch/arm/boot/dts/pxa168-aspenite.dts b/arch/arm/boot/dts/pxa168-aspenite.dts
new file mode 100644 (file)
index 0000000..e762fac
--- /dev/null
@@ -0,0 +1,38 @@
+/*
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+/dts-v1/;
+/include/ "pxa168.dtsi"
+
+/ {
+       model = "Marvell PXA168 Aspenite Development Board";
+       compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168";
+
+       chosen {
+               bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on";
+       };
+
+       memory {
+               reg = <0x00000000 0x04000000>;
+       };
+
+       soc {
+               apb@d4000000 {
+                       uart1: uart@d4017000 {
+                               status = "okay";
+                       };
+                       twsi1: i2c@d4011000 {
+                               status = "okay";
+                       };
+                       rtc: rtc@d4010000 {
+                               status = "okay";
+                       };
+               };
+       };
+};
diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi
new file mode 100644 (file)
index 0000000..d32d512
--- /dev/null
@@ -0,0 +1,98 @@
+/*
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+       aliases {
+               serial0 = &uart1;
+               serial1 = &uart2;
+               serial2 = &uart3;
+               i2c0 = &twsi1;
+               i2c1 = &twsi2;
+       };
+
+       intc: intc-interrupt-controller@d4282000 {
+               compatible = "mrvl,mmp-intc", "mrvl,intc";
+               interrupt-controller;
+               #interrupt-cells = <1>;
+               reg = <0xd4282000 0x1000>;
+       };
+
+       soc {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "simple-bus";
+               interrupt-parent = <&intc>;
+               ranges;
+
+               apb@d4000000 {  /* APB */
+                       compatible = "mrvl,apb-bus", "simple-bus";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       reg = <0xd4000000 0x00200000>;
+                       ranges;
+
+                       uart1: uart@d4017000 {
+                               compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
+                               reg = <0xd4017000 0x1000>;
+                               interrupts = <27>;
+                               status = "disabled";
+                       };
+
+                       uart2: uart@d4018000 {
+                               compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
+                               reg = <0xd4018000 0x1000>;
+                               interrupts = <28>;
+                               status = "disabled";
+                       };
+
+                       uart3: uart@d4026000 {
+                               compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
+                               reg = <0xd4026000 0x1000>;
+                               interrupts = <29>;
+                               status = "disabled";
+                       };
+
+                       gpio: gpio@d4019000 {
+                               compatible = "mrvl,mmp-gpio", "mrvl,pxa-gpio";
+                               reg = <0xd4019000 0x1000>;
+                               interrupts = <49>;
+                               interrupt-names = "gpio_mux";
+                               gpio-controller;
+                               #gpio-cells = <1>;
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+
+                       twsi1: i2c@d4011000 {
+                               compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
+                               reg = <0xd4011000 0x1000>;
+                               interrupts = <7>;
+                               mrvl,i2c-fast-mode;
+                               status = "disabled";
+                       };
+
+                       twsi2: i2c@d4025000 {
+                               compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
+                               reg = <0xd4025000 0x1000>;
+                               interrupts = <58>;
+                               status = "disabled";
+                       };
+
+                       rtc: rtc@d4010000 {
+                               compatible = "mrvl,mmp-rtc";
+                               reg = <0xd4010000 0x1000>;
+                               interrupts = <5 6>;
+                               interrupt-names = "rtc 1Hz", "rtc alarm";
+                               status = "disabled";
+                       };
+               };
+       };
+};
index 70c41fc897d741b7b9dd84f366d948def83eef3f..73263501f581076cdfb6da2103ceec59b0a0fd42 100644 (file)
        i2c@7000d000 {
                clock-frequency = <100000>;
        };
+
+       sdhci@78000000 {
+               cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+               wp-gpios = <&gpio 155 0>; /* gpio PT3 */
+               power-gpios = <&gpio 31 0>; /* gpio PD7 */
+       };
+
+       sdhci@78000200 {
+               status = "disable";
+       };
+
+       sdhci@78000400 {
+               status = "disable";
+       };
+
+       sdhci@78000400 {
+               support-8bit;
+       };
 };
index fc97254c36449c499d13db86cc4dc8c5e021b4d8..6c02abb469d4ba971bde9c4fb5aede05a99d4783 100644 (file)
@@ -65,7 +65,8 @@
                        "Headset Mic", "MICBIAS1",
                        "MIC1", "Headset Mic",
                        "Headset Stereophone", "HPR",
-                       "Headset Stereophone", "HPL";
+                       "Headset Stereophone", "HPL",
+                       "DMICDAT", "Digital Mic";
 
                nvidia,audio-codec = <&alc5632>;
                nvidia,i2s-controller = <&tegra_i2s1>;
index ec1f0101c79c928762d22b2339dc6c9d14c777af..aff8a175aa40303a5e6b86385c39046e3734cec8 100644 (file)
                      < 0x50040100 0x0100 >;
        };
 
+       pmu {
+               compatible = "arm,cortex-a9-pmu";
+               interrupts = <0 56 0x04
+                             0 57 0x04>;
+       };
+
        apbdma: dma@6000a000 {
                compatible = "nvidia,tegra20-apbdma";
                reg = <0x6000a000 0x1200>;
index ac4b75cb26c060b3d5a7f605bc7f5566266cf161..62a7b39f1c9a9e8f55ca409e5c192e312fe93d3b 100644 (file)
                      < 0x50040100 0x0100 >;
        };
 
+       pmu {
+               compatible = "arm,cortex-a9-pmu";
+               interrupts = <0 144 0x04
+                             0 145 0x04
+                             0 146 0x04
+                             0 147 0x04>;
+       };
+
        apbdma: dma@6000a000 {
                compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
                reg = <0x6000a000 0x1400>;
index f04b535477f54b5e63c688ab3294d9c826192eae..d74545a2a77cfa8cc9373c5e12e423b4ef8c0b9e 100644 (file)
                        };
                };
        };
+
+       leds {
+               compatible = "gpio-leds";
+
+               user_led {
+                       label = "user_led";
+                       gpios = <&pioB 21 1>;
+                       linux,default-trigger = "heartbeat";
+               };
+       };
+
+       gpio_keys {
+               compatible = "gpio-keys";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               user_pb {
+                       label = "user_pb";
+                       gpios = <&pioB 10 1>;
+                       linux,code = <28>;
+                       gpio-key,wakeup;
+               };
+       };
 };
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
new file mode 100644 (file)
index 0000000..16076e2
--- /dev/null
@@ -0,0 +1,201 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * Motherboard Express uATX
+ * V2M-P1
+ *
+ * HBI-0190D
+ *
+ * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
+ * Technical Reference Manual)
+ *
+ * WARNING! The hardware described in this file is independent from the
+ * original variant (vexpress-v2m.dtsi), but there is a strong
+ * correspondence between the two configurations.
+ *
+ * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
+ * CHANGES TO vexpress-v2m.dtsi!
+ */
+
+/ {
+       aliases {
+               arm,v2m_timer = &v2m_timer01;
+       };
+
+       motherboard {
+               compatible = "simple-bus";
+               arm,v2m-memory-map = "rs1";
+               #address-cells = <2>; /* SMB chipselect number and offset */
+               #size-cells = <1>;
+               #interrupt-cells = <1>;
+
+               flash@0,00000000 {
+                       compatible = "arm,vexpress-flash", "cfi-flash";
+                       reg = <0 0x00000000 0x04000000>,
+                             <4 0x00000000 0x04000000>;
+                       bank-width = <4>;
+               };
+
+               psram@1,00000000 {
+                       compatible = "arm,vexpress-psram", "mtd-ram";
+                       reg = <1 0x00000000 0x02000000>;
+                       bank-width = <4>;
+               };
+
+               vram@2,00000000 {
+                       compatible = "arm,vexpress-vram";
+                       reg = <2 0x00000000 0x00800000>;
+               };
+
+               ethernet@2,02000000 {
+                       compatible = "smsc,lan9118", "smsc,lan9115";
+                       reg = <2 0x02000000 0x10000>;
+                       interrupts = <15>;
+                       phy-mode = "mii";
+                       reg-io-width = <4>;
+                       smsc,irq-active-high;
+                       smsc,irq-push-pull;
+               };
+
+               usb@2,03000000 {
+                       compatible = "nxp,usb-isp1761";
+                       reg = <2 0x03000000 0x20000>;
+                       interrupts = <16>;
+                       port1-otg;
+               };
+
+               iofpga@3,00000000 {
+                       compatible = "arm,amba-bus", "simple-bus";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0 3 0 0x200000>;
+
+                       sysreg@010000 {
+                               compatible = "arm,vexpress-sysreg";
+                               reg = <0x010000 0x1000>;
+                       };
+
+                       sysctl@020000 {
+                               compatible = "arm,sp810", "arm,primecell";
+                               reg = <0x020000 0x1000>;
+                       };
+
+                       /* PCI-E I2C bus */
+                       v2m_i2c_pcie: i2c@030000 {
+                               compatible = "arm,versatile-i2c";
+                               reg = <0x030000 0x1000>;
+
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               pcie-switch@60 {
+                                       compatible = "idt,89hpes32h8";
+                                       reg = <0x60>;
+                               };
+                       };
+
+                       aaci@040000 {
+                               compatible = "arm,pl041", "arm,primecell";
+                               reg = <0x040000 0x1000>;
+                               interrupts = <11>;
+                       };
+
+                       mmci@050000 {
+                               compatible = "arm,pl180", "arm,primecell";
+                               reg = <0x050000 0x1000>;
+                               interrupts = <9 10>;
+                       };
+
+                       kmi@060000 {
+                               compatible = "arm,pl050", "arm,primecell";
+                               reg = <0x060000 0x1000>;
+                               interrupts = <12>;
+                       };
+
+                       kmi@070000 {
+                               compatible = "arm,pl050", "arm,primecell";
+                               reg = <0x070000 0x1000>;
+                               interrupts = <13>;
+                       };
+
+                       v2m_serial0: uart@090000 {
+                               compatible = "arm,pl011", "arm,primecell";
+                               reg = <0x090000 0x1000>;
+                               interrupts = <5>;
+                       };
+
+                       v2m_serial1: uart@0a0000 {
+                               compatible = "arm,pl011", "arm,primecell";
+                               reg = <0x0a0000 0x1000>;
+                               interrupts = <6>;
+                       };
+
+                       v2m_serial2: uart@0b0000 {
+                               compatible = "arm,pl011", "arm,primecell";
+                               reg = <0x0b0000 0x1000>;
+                               interrupts = <7>;
+                       };
+
+                       v2m_serial3: uart@0c0000 {
+                               compatible = "arm,pl011", "arm,primecell";
+                               reg = <0x0c0000 0x1000>;
+                               interrupts = <8>;
+                       };
+
+                       wdt@0f0000 {
+                               compatible = "arm,sp805", "arm,primecell";
+                               reg = <0x0f0000 0x1000>;
+                               interrupts = <0>;
+                       };
+
+                       v2m_timer01: timer@110000 {
+                               compatible = "arm,sp804", "arm,primecell";
+                               reg = <0x110000 0x1000>;
+                               interrupts = <2>;
+                       };
+
+                       v2m_timer23: timer@120000 {
+                               compatible = "arm,sp804", "arm,primecell";
+                               reg = <0x120000 0x1000>;
+                       };
+
+                       /* DVI I2C bus */
+                       v2m_i2c_dvi: i2c@160000 {
+                               compatible = "arm,versatile-i2c";
+                               reg = <0x160000 0x1000>;
+
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               dvi-transmitter@39 {
+                                       compatible = "sil,sii9022-tpi", "sil,sii9022";
+                                       reg = <0x39>;
+                               };
+
+                               dvi-transmitter@60 {
+                                       compatible = "sil,sii9022-cpi", "sil,sii9022";
+                                       reg = <0x60>;
+                               };
+                       };
+
+                       rtc@170000 {
+                               compatible = "arm,pl031", "arm,primecell";
+                               reg = <0x170000 0x1000>;
+                               interrupts = <4>;
+                       };
+
+                       compact-flash@1a0000 {
+                               compatible = "arm,vexpress-cf", "ata-generic";
+                               reg = <0x1a0000 0x100
+                                      0x1a0100 0xf00>;
+                               reg-shift = <2>;
+                       };
+
+                       clcd@1f0000 {
+                               compatible = "arm,pl111", "arm,primecell";
+                               reg = <0x1f0000 0x1000>;
+                               interrupts = <14>;
+                       };
+               };
+       };
+};
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
new file mode 100644 (file)
index 0000000..a6c9c7c
--- /dev/null
@@ -0,0 +1,200 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * Motherboard Express uATX
+ * V2M-P1
+ *
+ * HBI-0190D
+ *
+ * Original memory map ("Legacy memory map" in the board's
+ * Technical Reference Manual)
+ *
+ * WARNING! The hardware described in this file is independent from the
+ * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
+ * correspondence between the two configurations.
+ *
+ * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
+ * CHANGES TO vexpress-v2m-rs1.dtsi!
+ */
+
+/ {
+       aliases {
+               arm,v2m_timer = &v2m_timer01;
+       };
+
+       motherboard {
+               compatible = "simple-bus";
+               #address-cells = <2>; /* SMB chipselect number and offset */
+               #size-cells = <1>;
+               #interrupt-cells = <1>;
+
+               flash@0,00000000 {
+                       compatible = "arm,vexpress-flash", "cfi-flash";
+                       reg = <0 0x00000000 0x04000000>,
+                             <1 0x00000000 0x04000000>;
+                       bank-width = <4>;
+               };
+
+               psram@2,00000000 {
+                       compatible = "arm,vexpress-psram", "mtd-ram";
+                       reg = <2 0x00000000 0x02000000>;
+                       bank-width = <4>;
+               };
+
+               vram@3,00000000 {
+                       compatible = "arm,vexpress-vram";
+                       reg = <3 0x00000000 0x00800000>;
+               };
+
+               ethernet@3,02000000 {
+                       compatible = "smsc,lan9118", "smsc,lan9115";
+                       reg = <3 0x02000000 0x10000>;
+                       interrupts = <15>;
+                       phy-mode = "mii";
+                       reg-io-width = <4>;
+                       smsc,irq-active-high;
+                       smsc,irq-push-pull;
+               };
+
+               usb@3,03000000 {
+                       compatible = "nxp,usb-isp1761";
+                       reg = <3 0x03000000 0x20000>;
+                       interrupts = <16>;
+                       port1-otg;
+               };
+
+               iofpga@7,00000000 {
+                       compatible = "arm,amba-bus", "simple-bus";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0 7 0 0x20000>;
+
+                       sysreg@00000 {
+                               compatible = "arm,vexpress-sysreg";
+                               reg = <0x00000 0x1000>;
+                       };
+
+                       sysctl@01000 {
+                               compatible = "arm,sp810", "arm,primecell";
+                               reg = <0x01000 0x1000>;
+                       };
+
+                       /* PCI-E I2C bus */
+                       v2m_i2c_pcie: i2c@02000 {
+                               compatible = "arm,versatile-i2c";
+                               reg = <0x02000 0x1000>;
+
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               pcie-switch@60 {
+                                       compatible = "idt,89hpes32h8";
+                                       reg = <0x60>;
+                               };
+                       };
+
+                       aaci@04000 {
+                               compatible = "arm,pl041", "arm,primecell";
+                               reg = <0x04000 0x1000>;
+                               interrupts = <11>;
+                       };
+
+                       mmci@05000 {
+                               compatible = "arm,pl180", "arm,primecell";
+                               reg = <0x05000 0x1000>;
+                               interrupts = <9 10>;
+                       };
+
+                       kmi@06000 {
+                               compatible = "arm,pl050", "arm,primecell";
+                               reg = <0x06000 0x1000>;
+                               interrupts = <12>;
+                       };
+
+                       kmi@07000 {
+                               compatible = "arm,pl050", "arm,primecell";
+                               reg = <0x07000 0x1000>;
+                               interrupts = <13>;
+                       };
+
+                       v2m_serial0: uart@09000 {
+                               compatible = "arm,pl011", "arm,primecell";
+                               reg = <0x09000 0x1000>;
+                               interrupts = <5>;
+                       };
+
+                       v2m_serial1: uart@0a000 {
+                               compatible = "arm,pl011", "arm,primecell";
+                               reg = <0x0a000 0x1000>;
+                               interrupts = <6>;
+                       };
+
+                       v2m_serial2: uart@0b000 {
+                               compatible = "arm,pl011", "arm,primecell";
+                               reg = <0x0b000 0x1000>;
+                               interrupts = <7>;
+                       };
+
+                       v2m_serial3: uart@0c000 {
+                               compatible = "arm,pl011", "arm,primecell";
+                               reg = <0x0c000 0x1000>;
+                               interrupts = <8>;
+                       };
+
+                       wdt@0f000 {
+                               compatible = "arm,sp805", "arm,primecell";
+                               reg = <0x0f000 0x1000>;
+                               interrupts = <0>;
+                       };
+
+                       v2m_timer01: timer@11000 {
+                               compatible = "arm,sp804", "arm,primecell";
+                               reg = <0x11000 0x1000>;
+                               interrupts = <2>;
+                       };
+
+                       v2m_timer23: timer@12000 {
+                               compatible = "arm,sp804", "arm,primecell";
+                               reg = <0x12000 0x1000>;
+                       };
+
+                       /* DVI I2C bus */
+                       v2m_i2c_dvi: i2c@16000 {
+                               compatible = "arm,versatile-i2c";
+                               reg = <0x16000 0x1000>;
+
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               dvi-transmitter@39 {
+                                       compatible = "sil,sii9022-tpi", "sil,sii9022";
+                                       reg = <0x39>;
+                               };
+
+                               dvi-transmitter@60 {
+                                       compatible = "sil,sii9022-cpi", "sil,sii9022";
+                                       reg = <0x60>;
+                               };
+                       };
+
+                       rtc@17000 {
+                               compatible = "arm,pl031", "arm,primecell";
+                               reg = <0x17000 0x1000>;
+                               interrupts = <4>;
+                       };
+
+                       compact-flash@1a000 {
+                               compatible = "arm,vexpress-cf", "ata-generic";
+                               reg = <0x1a000 0x100
+                                      0x1a100 0xf00>;
+                               reg-shift = <2>;
+                       };
+
+                       clcd@1f000 {
+                               compatible = "arm,pl111", "arm,primecell";
+                               reg = <0x1f000 0x1000>;
+                               interrupts = <14>;
+                       };
+               };
+       };
+};
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
new file mode 100644 (file)
index 0000000..941b161
--- /dev/null
@@ -0,0 +1,157 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * CoreTile Express A15x2 (version with Test Chip 1)
+ * Cortex-A15 MPCore (V2P-CA15)
+ *
+ * HBI-0237A
+ */
+
+/dts-v1/;
+
+/ {
+       model = "V2P-CA15";
+       arm,hbi = <0x237>;
+       compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
+       interrupt-parent = <&gic>;
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       chosen { };
+
+       aliases {
+               serial0 = &v2m_serial0;
+               serial1 = &v2m_serial1;
+               serial2 = &v2m_serial2;
+               serial3 = &v2m_serial3;
+               i2c0 = &v2m_i2c_dvi;
+               i2c1 = &v2m_i2c_pcie;
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a15";
+                       reg = <0>;
+               };
+
+               cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a15";
+                       reg = <1>;
+               };
+       };
+
+       memory@80000000 {
+               device_type = "memory";
+               reg = <0x80000000 0x40000000>;
+       };
+
+       hdlcd@2b000000 {
+               compatible = "arm,hdlcd";
+               reg = <0x2b000000 0x1000>;
+               interrupts = <0 85 4>;
+       };
+
+       memory-controller@2b0a0000 {
+               compatible = "arm,pl341", "arm,primecell";
+               reg = <0x2b0a0000 0x1000>;
+       };
+
+       wdt@2b060000 {
+               compatible = "arm,sp805", "arm,primecell";
+               reg = <0x2b060000 0x1000>;
+               interrupts = <98>;
+       };
+
+       gic: interrupt-controller@2c001000 {
+               compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+               #interrupt-cells = <3>;
+               #address-cells = <0>;
+               interrupt-controller;
+               reg = <0x2c001000 0x1000>,
+                     <0x2c002000 0x100>;
+       };
+
+       memory-controller@7ffd0000 {
+               compatible = "arm,pl354", "arm,primecell";
+               reg = <0x7ffd0000 0x1000>;
+               interrupts = <0 86 4>,
+                            <0 87 4>;
+       };
+
+       dma@7ffb0000 {
+               compatible = "arm,pl330", "arm,primecell";
+               reg = <0x7ffb0000 0x1000>;
+               interrupts = <0 92 4>,
+                            <0 88 4>,
+                            <0 89 4>,
+                            <0 90 4>,
+                            <0 91 4>;
+       };
+
+       pmu {
+               compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
+               interrupts = <0 68 4>,
+                            <0 69 4>;
+       };
+
+       motherboard {
+               ranges = <0 0 0x08000000 0x04000000>,
+                        <1 0 0x14000000 0x04000000>,
+                        <2 0 0x18000000 0x04000000>,
+                        <3 0 0x1c000000 0x04000000>,
+                        <4 0 0x0c000000 0x04000000>,
+                        <5 0 0x10000000 0x04000000>;
+
+               interrupt-map-mask = <0 0 63>;
+               interrupt-map = <0 0  0 &gic 0  0 4>,
+                               <0 0  1 &gic 0  1 4>,
+                               <0 0  2 &gic 0  2 4>,
+                               <0 0  3 &gic 0  3 4>,
+                               <0 0  4 &gic 0  4 4>,
+                               <0 0  5 &gic 0  5 4>,
+                               <0 0  6 &gic 0  6 4>,
+                               <0 0  7 &gic 0  7 4>,
+                               <0 0  8 &gic 0  8 4>,
+                               <0 0  9 &gic 0  9 4>,
+                               <0 0 10 &gic 0 10 4>,
+                               <0 0 11 &gic 0 11 4>,
+                               <0 0 12 &gic 0 12 4>,
+                               <0 0 13 &gic 0 13 4>,
+                               <0 0 14 &gic 0 14 4>,
+                               <0 0 15 &gic 0 15 4>,
+                               <0 0 16 &gic 0 16 4>,
+                               <0 0 17 &gic 0 17 4>,
+                               <0 0 18 &gic 0 18 4>,
+                               <0 0 19 &gic 0 19 4>,
+                               <0 0 20 &gic 0 20 4>,
+                               <0 0 21 &gic 0 21 4>,
+                               <0 0 22 &gic 0 22 4>,
+                               <0 0 23 &gic 0 23 4>,
+                               <0 0 24 &gic 0 24 4>,
+                               <0 0 25 &gic 0 25 4>,
+                               <0 0 26 &gic 0 26 4>,
+                               <0 0 27 &gic 0 27 4>,
+                               <0 0 28 &gic 0 28 4>,
+                               <0 0 29 &gic 0 29 4>,
+                               <0 0 30 &gic 0 30 4>,
+                               <0 0 31 &gic 0 31 4>,
+                               <0 0 32 &gic 0 32 4>,
+                               <0 0 33 &gic 0 33 4>,
+                               <0 0 34 &gic 0 34 4>,
+                               <0 0 35 &gic 0 35 4>,
+                               <0 0 36 &gic 0 36 4>,
+                               <0 0 37 &gic 0 37 4>,
+                               <0 0 38 &gic 0 38 4>,
+                               <0 0 39 &gic 0 39 4>,
+                               <0 0 40 &gic 0 40 4>,
+                               <0 0 41 &gic 0 41 4>,
+                               <0 0 42 &gic 0 42 4>;
+       };
+};
+
+/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
new file mode 100644 (file)
index 0000000..6905e66
--- /dev/null
@@ -0,0 +1,162 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * CoreTile Express A5x2
+ * Cortex-A5 MPCore (V2P-CA5s)
+ *
+ * HBI-0225B
+ */
+
+/dts-v1/;
+
+/ {
+       model = "V2P-CA5s";
+       arm,hbi = <0x225>;
+       compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
+       interrupt-parent = <&gic>;
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       chosen { };
+
+       aliases {
+               serial0 = &v2m_serial0;
+               serial1 = &v2m_serial1;
+               serial2 = &v2m_serial2;
+               serial3 = &v2m_serial3;
+               i2c0 = &v2m_i2c_dvi;
+               i2c1 = &v2m_i2c_pcie;
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a5";
+                       reg = <0>;
+                       next-level-cache = <&L2>;
+               };
+
+               cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a5";
+                       reg = <1>;
+                       next-level-cache = <&L2>;
+               };
+       };
+
+       memory@80000000 {
+               device_type = "memory";
+               reg = <0x80000000 0x40000000>;
+       };
+
+       hdlcd@2a110000 {
+               compatible = "arm,hdlcd";
+               reg = <0x2a110000 0x1000>;
+               interrupts = <0 85 4>;
+       };
+
+       memory-controller@2a150000 {
+               compatible = "arm,pl341", "arm,primecell";
+               reg = <0x2a150000 0x1000>;
+       };
+
+       memory-controller@2a190000 {
+               compatible = "arm,pl354", "arm,primecell";
+               reg = <0x2a190000 0x1000>;
+               interrupts = <0 86 4>,
+                            <0 87 4>;
+       };
+
+       scu@2c000000 {
+               compatible = "arm,cortex-a5-scu";
+               reg = <0x2c000000 0x58>;
+       };
+
+       timer@2c000600 {
+               compatible = "arm,cortex-a5-twd-timer";
+               reg = <0x2c000600 0x38>;
+               interrupts = <1 2 0x304>,
+                            <1 3 0x304>;
+       };
+
+       gic: interrupt-controller@2c001000 {
+               compatible = "arm,corex-a5-gic", "arm,cortex-a9-gic";
+               #interrupt-cells = <3>;
+               #address-cells = <0>;
+               interrupt-controller;
+               reg = <0x2c001000 0x1000>,
+                     <0x2c000100 0x100>;
+       };
+
+       L2: cache-controller@2c0f0000 {
+               compatible = "arm,pl310-cache";
+               reg = <0x2c0f0000 0x1000>;
+               interrupts = <0 84 4>;
+               cache-level = <2>;
+       };
+
+       pmu {
+               compatible = "arm,cortex-a5-pmu", "arm,cortex-a9-pmu";
+               interrupts = <0 68 4>,
+                            <0 69 4>;
+       };
+
+       motherboard {
+               ranges = <0 0 0x08000000 0x04000000>,
+                        <1 0 0x14000000 0x04000000>,
+                        <2 0 0x18000000 0x04000000>,
+                        <3 0 0x1c000000 0x04000000>,
+                        <4 0 0x0c000000 0x04000000>,
+                        <5 0 0x10000000 0x04000000>;
+
+               interrupt-map-mask = <0 0 63>;
+               interrupt-map = <0 0  0 &gic 0  0 4>,
+                               <0 0  1 &gic 0  1 4>,
+                               <0 0  2 &gic 0  2 4>,
+                               <0 0  3 &gic 0  3 4>,
+                               <0 0  4 &gic 0  4 4>,
+                               <0 0  5 &gic 0  5 4>,
+                               <0 0  6 &gic 0  6 4>,
+                               <0 0  7 &gic 0  7 4>,
+                               <0 0  8 &gic 0  8 4>,
+                               <0 0  9 &gic 0  9 4>,
+                               <0 0 10 &gic 0 10 4>,
+                               <0 0 11 &gic 0 11 4>,
+                               <0 0 12 &gic 0 12 4>,
+                               <0 0 13 &gic 0 13 4>,
+                               <0 0 14 &gic 0 14 4>,
+                               <0 0 15 &gic 0 15 4>,
+                               <0 0 16 &gic 0 16 4>,
+                               <0 0 17 &gic 0 17 4>,
+                               <0 0 18 &gic 0 18 4>,
+                               <0 0 19 &gic 0 19 4>,
+                               <0 0 20 &gic 0 20 4>,
+                               <0 0 21 &gic 0 21 4>,
+                               <0 0 22 &gic 0 22 4>,
+                               <0 0 23 &gic 0 23 4>,
+                               <0 0 24 &gic 0 24 4>,
+                               <0 0 25 &gic 0 25 4>,
+                               <0 0 26 &gic 0 26 4>,
+                               <0 0 27 &gic 0 27 4>,
+                               <0 0 28 &gic 0 28 4>,
+                               <0 0 29 &gic 0 29 4>,
+                               <0 0 30 &gic 0 30 4>,
+                               <0 0 31 &gic 0 31 4>,
+                               <0 0 32 &gic 0 32 4>,
+                               <0 0 33 &gic 0 33 4>,
+                               <0 0 34 &gic 0 34 4>,
+                               <0 0 35 &gic 0 35 4>,
+                               <0 0 36 &gic 0 36 4>,
+                               <0 0 37 &gic 0 37 4>,
+                               <0 0 38 &gic 0 38 4>,
+                               <0 0 39 &gic 0 39 4>,
+                               <0 0 40 &gic 0 40 4>,
+                               <0 0 41 &gic 0 41 4>,
+                               <0 0 42 &gic 0 42 4>;
+       };
+};
+
+/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
new file mode 100644 (file)
index 0000000..da77869
--- /dev/null
@@ -0,0 +1,192 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * CoreTile Express A9x4
+ * Cortex-A9 MPCore (V2P-CA9)
+ *
+ * HBI-0191B
+ */
+
+/dts-v1/;
+
+/ {
+       model = "V2P-CA9";
+       arm,hbi = <0x191>;
+       compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
+       interrupt-parent = <&gic>;
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       chosen { };
+
+       aliases {
+               serial0 = &v2m_serial0;
+               serial1 = &v2m_serial1;
+               serial2 = &v2m_serial2;
+               serial3 = &v2m_serial3;
+               i2c0 = &v2m_i2c_dvi;
+               i2c1 = &v2m_i2c_pcie;
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a9";
+                       reg = <0>;
+                       next-level-cache = <&L2>;
+               };
+
+               cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a9";
+                       reg = <1>;
+                       next-level-cache = <&L2>;
+               };
+
+               cpu@2 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a9";
+                       reg = <2>;
+                       next-level-cache = <&L2>;
+               };
+
+               cpu@3 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a9";
+                       reg = <3>;
+                       next-level-cache = <&L2>;
+               };
+       };
+
+       memory@60000000 {
+               device_type = "memory";
+               reg = <0x60000000 0x40000000>;
+       };
+
+       clcd@10020000 {
+               compatible = "arm,pl111", "arm,primecell";
+               reg = <0x10020000 0x1000>;
+               interrupts = <0 44 4>;
+       };
+
+       memory-controller@100e0000 {
+               compatible = "arm,pl341", "arm,primecell";
+               reg = <0x100e0000 0x1000>;
+       };
+
+       memory-controller@100e1000 {
+               compatible = "arm,pl354", "arm,primecell";
+               reg = <0x100e1000 0x1000>;
+               interrupts = <0 45 4>,
+                            <0 46 4>;
+       };
+
+       timer@100e4000 {
+               compatible = "arm,sp804", "arm,primecell";
+               reg = <0x100e4000 0x1000>;
+               interrupts = <0 48 4>,
+                            <0 49 4>;
+       };
+
+       watchdog@100e5000 {
+               compatible = "arm,sp805", "arm,primecell";
+               reg = <0x100e5000 0x1000>;
+               interrupts = <0 51 4>;
+       };
+
+       scu@1e000000 {
+               compatible = "arm,cortex-a9-scu";
+               reg = <0x1e000000 0x58>;
+       };
+
+       timer@1e000600 {
+               compatible = "arm,cortex-a9-twd-timer";
+               reg = <0x1e000600 0x20>;
+               interrupts = <1 2 0xf04>,
+                            <1 3 0xf04>;
+       };
+
+       gic: interrupt-controller@1e001000 {
+               compatible = "arm,cortex-a9-gic";
+               #interrupt-cells = <3>;
+               #address-cells = <0>;
+               interrupt-controller;
+               reg = <0x1e001000 0x1000>,
+                     <0x1e000100 0x100>;
+       };
+
+       L2: cache-controller@1e00a000 {
+               compatible = "arm,pl310-cache";
+               reg = <0x1e00a000 0x1000>;
+               interrupts = <0 43 4>;
+               cache-level = <2>;
+               arm,data-latency = <1 1 1>;
+               arm,tag-latency = <1 1 1>;
+       };
+
+       pmu {
+               compatible = "arm,cortex-a9-pmu";
+               interrupts = <0 60 4>,
+                            <0 61 4>,
+                            <0 62 4>,
+                            <0 63 4>;
+       };
+
+       motherboard {
+               ranges = <0 0 0x40000000 0x04000000>,
+                        <1 0 0x44000000 0x04000000>,
+                        <2 0 0x48000000 0x04000000>,
+                        <3 0 0x4c000000 0x04000000>,
+                        <7 0 0x10000000 0x00020000>;
+
+               interrupt-map-mask = <0 0 63>;
+               interrupt-map = <0 0  0 &gic 0  0 4>,
+                               <0 0  1 &gic 0  1 4>,
+                               <0 0  2 &gic 0  2 4>,
+                               <0 0  3 &gic 0  3 4>,
+                               <0 0  4 &gic 0  4 4>,
+                               <0 0  5 &gic 0  5 4>,
+                               <0 0  6 &gic 0  6 4>,
+                               <0 0  7 &gic 0  7 4>,
+                               <0 0  8 &gic 0  8 4>,
+                               <0 0  9 &gic 0  9 4>,
+                               <0 0 10 &gic 0 10 4>,
+                               <0 0 11 &gic 0 11 4>,
+                               <0 0 12 &gic 0 12 4>,
+                               <0 0 13 &gic 0 13 4>,
+                               <0 0 14 &gic 0 14 4>,
+                               <0 0 15 &gic 0 15 4>,
+                               <0 0 16 &gic 0 16 4>,
+                               <0 0 17 &gic 0 17 4>,
+                               <0 0 18 &gic 0 18 4>,
+                               <0 0 19 &gic 0 19 4>,
+                               <0 0 20 &gic 0 20 4>,
+                               <0 0 21 &gic 0 21 4>,
+                               <0 0 22 &gic 0 22 4>,
+                               <0 0 23 &gic 0 23 4>,
+                               <0 0 24 &gic 0 24 4>,
+                               <0 0 25 &gic 0 25 4>,
+                               <0 0 26 &gic 0 26 4>,
+                               <0 0 27 &gic 0 27 4>,
+                               <0 0 28 &gic 0 28 4>,
+                               <0 0 29 &gic 0 29 4>,
+                               <0 0 30 &gic 0 30 4>,
+                               <0 0 31 &gic 0 31 4>,
+                               <0 0 32 &gic 0 32 4>,
+                               <0 0 33 &gic 0 33 4>,
+                               <0 0 34 &gic 0 34 4>,
+                               <0 0 35 &gic 0 35 4>,
+                               <0 0 36 &gic 0 36 4>,
+                               <0 0 37 &gic 0 37 4>,
+                               <0 0 38 &gic 0 38 4>,
+                               <0 0 39 &gic 0 39 4>,
+                               <0 0 40 &gic 0 40 4>,
+                               <0 0 41 &gic 0 41 4>,
+                               <0 0 42 &gic 0 42 4>;
+       };
+};
+
+/include/ "vexpress-v2m.dtsi"
index 1b6518518d99e4e9c0ba2fddff74fb62ae766060..8512e53bed9356afb310849b7f976f895c6076d1 100644 (file)
@@ -20,7 +20,7 @@ obj-$(CONFIG_ARCH_AT91SAM9263)        += at91sam9263.o at91sam926x_time.o at91sam9263_d
 obj-$(CONFIG_ARCH_AT91SAM9RL)  += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
-obj-$(CONFIG_ARCH_AT91SAM9X5)  += at91sam9x5.o at91sam926x_time.o
+obj-$(CONFIG_ARCH_AT91SAM9X5)  += at91sam9x5.o at91sam926x_time.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91X40)     += at91x40.o at91x40_time.o
 
 # AT91RM9200 board-specific support
index 2fd051eb2449d7a76490e0f9309c8b2216f35025..0da66ca4a4f83329dfd290b9582abb2b396153db 100644 (file)
@@ -13,4 +13,10 @@ params_phys-y        := 0x20000100
 initrd_phys-y  := 0x20410000
 endif
 
-dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb usb_a9g20.dtb
+# Keep dtb files sorted alphabetically for each SoC
+# sam9g20
+dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9g20.dtb
+# sam9g45
+dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb
+# sam9x5
+dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g25ek.dtb
index dd6e2de134204a5ccf5c28df3bfe41d9b8170314..0df1045311e420e2e96670e62f182f44d39f5481 100644 (file)
@@ -295,7 +295,7 @@ static void at91rm9200_idle(void)
         * Disable the processor clock.  The processor will be automatically
         * re-enabled by an interrupt or by a reset.
         */
-       at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
+       at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
 }
 
 static void at91rm9200_restart(char mode, const char *cmd)
@@ -303,8 +303,8 @@ static void at91rm9200_restart(char mode, const char *cmd)
        /*
         * Perform a hardware reset with the use of the Watchdog timer.
         */
-       at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
-       at91_sys_write(AT91_ST_CR, AT91_ST_WDRST);
+       at91_st_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
+       at91_st_write(AT91_ST_CR, AT91_ST_WDRST);
 }
 
 /* --------------------------------------------------------------------
@@ -319,6 +319,8 @@ static void __init at91rm9200_map_io(void)
 
 static void __init at91rm9200_ioremap_registers(void)
 {
+       at91rm9200_ioremap_st(AT91RM9200_BASE_ST);
+       at91_ioremap_ramc(0, AT91RM9200_BASE_MC, 256);
 }
 
 static void __init at91rm9200_initialize(void)
index 97676bdae9983c98b79f77cb85dd88e833756789..99ce5c955e39d94d24f50005b875459739ef6ce5 100644 (file)
@@ -21,6 +21,7 @@
 #include <mach/board.h>
 #include <mach/at91rm9200.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 
 #include "generic.h"
 
@@ -241,15 +242,15 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
        data->chipselect = 4;           /* can only use EBI ChipSelect 4 */
 
        /* CF takes over CS4, CS5, CS6 */
-       csa = at91_sys_read(AT91_EBI_CSA);
-       at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
+       csa = at91_ramc_read(0, AT91_EBI_CSA);
+       at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
 
        /*
         * Static memory controller timing adjustments.
         * REVISIT:  these timings are in terms of MCK cycles, so
         * when MCK changes (cpufreq etc) so must these values...
         */
-       at91_sys_write(AT91_SMC_CSR(4),
+       at91_ramc_write(0, AT91_SMC_CSR(4),
                                  AT91_SMC_ACSS_STD
                                | AT91_SMC_DBW_16
                                | AT91_SMC_BAT
@@ -407,11 +408,11 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
                return;
 
        /* enable the address range of CS3 */
-       csa = at91_sys_read(AT91_EBI_CSA);
-       at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
+       csa = at91_ramc_read(0, AT91_EBI_CSA);
+       at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
 
        /* set the bus interface characteristics */
-       at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
+       at91_ramc_write(0, AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
                | AT91_SMC_NWS_(5)
                | AT91_SMC_TDF_(1)
                | AT91_SMC_RWSETUP_(0)  /* tDS Data Set up Time 30 - ns */
@@ -1114,7 +1115,6 @@ static inline void configure_usart3_pins(unsigned pins)
 }
 
 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];  /* the UARTs to use */
-struct platform_device *atmel_default_console_device;  /* the serial console device */
 
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
index a028cdf8f9749d8ad4da1aef23386da5850330c4..dd7f782b0b91731202c3d8e10f02597b7d89518c 100644 (file)
@@ -43,9 +43,9 @@ static inline unsigned long read_CRTR(void)
 {
        unsigned long x1, x2;
 
-       x1 = at91_sys_read(AT91_ST_CRTR);
+       x1 = at91_st_read(AT91_ST_CRTR);
        do {
-               x2 = at91_sys_read(AT91_ST_CRTR);
+               x2 = at91_st_read(AT91_ST_CRTR);
                if (x1 == x2)
                        break;
                x1 = x2;
@@ -58,7 +58,7 @@ static inline unsigned long read_CRTR(void)
  */
 static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
 {
-       u32     sr = at91_sys_read(AT91_ST_SR) & irqmask;
+       u32     sr = at91_st_read(AT91_ST_SR) & irqmask;
 
        /*
         * irqs should be disabled here, but as the irq is shared they are only
@@ -110,22 +110,22 @@ static void
 clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
 {
        /* Disable and flush pending timer interrupts */
-       at91_sys_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
-       (void) at91_sys_read(AT91_ST_SR);
+       at91_st_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
+       at91_st_read(AT91_ST_SR);
 
        last_crtr = read_CRTR();
        switch (mode) {
        case CLOCK_EVT_MODE_PERIODIC:
                /* PIT for periodic irqs; fixed rate of 1/HZ */
                irqmask = AT91_ST_PITS;
-               at91_sys_write(AT91_ST_PIMR, RM9200_TIMER_LATCH);
+               at91_st_write(AT91_ST_PIMR, RM9200_TIMER_LATCH);
                break;
        case CLOCK_EVT_MODE_ONESHOT:
                /* ALM for oneshot irqs, set by next_event()
                 * before 32 seconds have passed
                 */
                irqmask = AT91_ST_ALMS;
-               at91_sys_write(AT91_ST_RTAR, last_crtr);
+               at91_st_write(AT91_ST_RTAR, last_crtr);
                break;
        case CLOCK_EVT_MODE_SHUTDOWN:
        case CLOCK_EVT_MODE_UNUSED:
@@ -133,7 +133,7 @@ clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
                irqmask = 0;
                break;
        }
-       at91_sys_write(AT91_ST_IER, irqmask);
+       at91_st_write(AT91_ST_IER, irqmask);
 }
 
 static int
@@ -156,12 +156,12 @@ clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
        alm = read_CRTR();
 
        /* Cancel any pending alarm; flush any pending IRQ */
-       at91_sys_write(AT91_ST_RTAR, alm);
-       (void) at91_sys_read(AT91_ST_SR);
+       at91_st_write(AT91_ST_RTAR, alm);
+       at91_st_read(AT91_ST_SR);
 
        /* Schedule alarm by writing RTAR. */
        alm += delta;
-       at91_sys_write(AT91_ST_RTAR, alm);
+       at91_st_write(AT91_ST_RTAR, alm);
 
        return status;
 }
@@ -175,15 +175,24 @@ static struct clock_event_device clkevt = {
        .set_mode       = clkevt32k_mode,
 };
 
+void __iomem *at91_st_base;
+
+void __init at91rm9200_ioremap_st(u32 addr)
+{
+       at91_st_base = ioremap(addr, 256);
+       if (!at91_st_base)
+               panic("Impossible to ioremap ST\n");
+}
+
 /*
  * ST (system timer) module supports both clockevents and clocksource.
  */
 void __init at91rm9200_timer_init(void)
 {
        /* Disable all timer interrupts, and clear any pending ones */
-       at91_sys_write(AT91_ST_IDR,
+       at91_st_write(AT91_ST_IDR,
                AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
-       (void) at91_sys_read(AT91_ST_SR);
+       at91_st_read(AT91_ST_SR);
 
        /* Make IRQs happen for the system timer */
        setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq);
@@ -192,7 +201,7 @@ void __init at91rm9200_timer_init(void)
         * directly for the clocksource and all clockevents, after adjusting
         * its prescaler from the 1 Hz default.
         */
-       at91_sys_write(AT91_ST_RTMR, 1);
+       at91_st_write(AT91_ST_RTMR, 1);
 
        /* Setup timer clockevent, with minimum of two ticks (important!!) */
        clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift);
index 9ac8c6fe3363b6af723c8366108d6d863bcb9415..14b5a9c9a5144c2b36215ab139596bae9a739bd5 100644 (file)
@@ -209,6 +209,13 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
        CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
        CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
+       /* more tc lookup table for DT entries */
+       CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
+       CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
+       CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
+       CLKDEV_CON_DEV_ID("t0_clk", "fffdc000.timer", &tc3_clk),
+       CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk),
+       CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
        /* fake hclk clock */
        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
        CLKDEV_CON_ID("pioA", &pioA_clk),
@@ -310,34 +317,27 @@ static void __init at91sam9xe_map_io(void)
 
 static void __init at91sam9260_map_io(void)
 {
-       if (cpu_is_at91sam9xe()) {
+       if (cpu_is_at91sam9xe())
                at91sam9xe_map_io();
-       } else if (cpu_is_at91sam9g20()) {
-               at91_init_sram(0, AT91SAM9G20_SRAM0_BASE, AT91SAM9G20_SRAM0_SIZE);
-               at91_init_sram(1, AT91SAM9G20_SRAM1_BASE, AT91SAM9G20_SRAM1_SIZE);
-       } else {
-               at91_init_sram(0, AT91SAM9260_SRAM0_BASE, AT91SAM9260_SRAM0_SIZE);
-               at91_init_sram(1, AT91SAM9260_SRAM1_BASE, AT91SAM9260_SRAM1_SIZE);
-       }
+       else if (cpu_is_at91sam9g20())
+               at91_init_sram(0, AT91SAM9G20_SRAM_BASE, AT91SAM9G20_SRAM_SIZE);
+       else
+               at91_init_sram(0, AT91SAM9260_SRAM_BASE, AT91SAM9260_SRAM_SIZE);
 }
 
 static void __init at91sam9260_ioremap_registers(void)
 {
        at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
        at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
+       at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC, 512);
        at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
        at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
-}
-
-static void at91sam9260_idle(void)
-{
-       at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
-       cpu_do_idle();
+       at91_ioremap_matrix(AT91SAM9260_BASE_MATRIX);
 }
 
 static void __init at91sam9260_initialize(void)
 {
-       arm_pm_idle = at91sam9260_idle;
+       arm_pm_idle = at91sam9_idle;
        arm_pm_restart = at91sam9_alt_restart;
        at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
                        | (1 << AT91SAM9260_ID_IRQ2);
index 5a24f0b4554db2b7e4ea50e620b464e2e9b9363a..7e5651ee9f859f9689b76f07ca5bc834d3aa871a 100644 (file)
@@ -21,6 +21,7 @@
 #include <mach/cpu.h>
 #include <mach/at91sam9260.h>
 #include <mach/at91sam9260_matrix.h>
+#include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
 
 #include "generic.h"
@@ -422,8 +423,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
        if (!data)
                return;
 
-       csa = at91_sys_read(AT91_MATRIX_EBICSA);
-       at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+       csa = at91_matrix_read(AT91_MATRIX_EBICSA);
+       at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
 
        /* enable pin */
        if (gpio_is_valid(data->enable_pin))
@@ -641,7 +642,7 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
 static struct resource tcb0_resources[] = {
        [0] = {
                .start  = AT91SAM9260_BASE_TCB0,
-               .end    = AT91SAM9260_BASE_TCB0 + SZ_16K - 1,
+               .end    = AT91SAM9260_BASE_TCB0 + SZ_256 - 1,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
@@ -671,7 +672,7 @@ static struct platform_device at91sam9260_tcb0_device = {
 static struct resource tcb1_resources[] = {
        [0] = {
                .start  = AT91SAM9260_BASE_TCB1,
-               .end    = AT91SAM9260_BASE_TCB1 + SZ_16K - 1,
+               .end    = AT91SAM9260_BASE_TCB1 + SZ_256 - 1,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
@@ -698,8 +699,25 @@ static struct platform_device at91sam9260_tcb1_device = {
        .num_resources  = ARRAY_SIZE(tcb1_resources),
 };
 
+#if defined(CONFIG_OF)
+static struct of_device_id tcb_ids[] = {
+       { .compatible = "atmel,at91rm9200-tcb" },
+       { /*sentinel*/ }
+};
+#endif
+
 static void __init at91_add_device_tc(void)
 {
+#if defined(CONFIG_OF)
+       struct device_node *np;
+
+       np = of_find_matching_node(NULL, tcb_ids);
+       if (np) {
+               of_node_put(np);
+               return;
+       }
+#endif
+
        platform_device_register(&at91sam9260_tcb0_device);
        platform_device_register(&at91sam9260_tcb1_device);
 }
@@ -717,18 +735,42 @@ static struct resource rtt_resources[] = {
                .start  = AT91SAM9260_BASE_RTT,
                .end    = AT91SAM9260_BASE_RTT + SZ_16 - 1,
                .flags  = IORESOURCE_MEM,
-       }
+       }, {
+               .flags  = IORESOURCE_MEM,
+       },
 };
 
 static struct platform_device at91sam9260_rtt_device = {
        .name           = "at91_rtt",
        .id             = 0,
        .resource       = rtt_resources,
-       .num_resources  = ARRAY_SIZE(rtt_resources),
 };
 
+
+#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
+static void __init at91_add_device_rtt_rtc(void)
+{
+       at91sam9260_rtt_device.name = "rtc-at91sam9";
+       /*
+        * The second resource is needed:
+        * GPBR will serve as the storage for RTC time offset
+        */
+       at91sam9260_rtt_device.num_resources = 2;
+       rtt_resources[1].start = AT91SAM9260_BASE_GPBR +
+                                4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
+       rtt_resources[1].end = rtt_resources[1].start + 3;
+}
+#else
+static void __init at91_add_device_rtt_rtc(void)
+{
+       /* Only one resource is needed: RTT not used as RTC */
+       at91sam9260_rtt_device.num_resources = 1;
+}
+#endif
+
 static void __init at91_add_device_rtt(void)
 {
+       at91_add_device_rtt_rtc();
        platform_device_register(&at91sam9260_rtt_device);
 }
 
@@ -1139,7 +1181,6 @@ static inline void configure_usart5_pins(void)
 }
 
 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];  /* the UARTs to use */
-struct platform_device *atmel_default_console_device;  /* the serial console device */
 
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
@@ -1264,7 +1305,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
        if (!data)
                return;
 
-       csa = at91_sys_read(AT91_MATRIX_EBICSA);
+       csa = at91_matrix_read(AT91_MATRIX_EBICSA);
 
        switch (data->chipselect) {
        case 4:
@@ -1287,7 +1328,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
                return;
        }
 
-       at91_sys_write(AT91_MATRIX_EBICSA, csa);
+       at91_matrix_write(AT91_MATRIX_EBICSA, csa);
 
        if (gpio_is_valid(data->rst_pin)) {
                at91_set_multi_drive(data->rst_pin, 0);
index ab76868f01f5ee8e48b80359d3064e531ae3c86d..684c5dfd92ac5a00eaf736ed5d5949769f4bdbd4 100644 (file)
@@ -283,19 +283,15 @@ static void __init at91sam9261_ioremap_registers(void)
 {
        at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
        at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
+       at91_ioremap_ramc(0, AT91SAM9261_BASE_SDRAMC, 512);
        at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
        at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
-}
-
-static void at91sam9261_idle(void)
-{
-       at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
-       cpu_do_idle();
+       at91_ioremap_matrix(AT91SAM9261_BASE_MATRIX);
 }
 
 static void __init at91sam9261_initialize(void)
 {
-       arm_pm_idle = at91sam9261_idle;
+       arm_pm_idle = at91sam9_idle;
        arm_pm_restart = at91sam9_alt_restart;
        at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
                        | (1 << AT91SAM9261_ID_IRQ2);
index 1e28bed8f425063e99af8ac417035e5e6d01900f..096da87dc00d41359fa793f6dd25f541516dd86c 100644 (file)
@@ -24,6 +24,7 @@
 #include <mach/board.h>
 #include <mach/at91sam9261.h>
 #include <mach/at91sam9261_matrix.h>
+#include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
 
 #include "generic.h"
@@ -236,8 +237,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
        if (!data)
                return;
 
-       csa = at91_sys_read(AT91_MATRIX_EBICSA);
-       at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+       csa = at91_matrix_read(AT91_MATRIX_EBICSA);
+       at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
 
        /* enable pin */
        if (gpio_is_valid(data->enable_pin))
@@ -603,6 +604,8 @@ static struct resource rtt_resources[] = {
                .start  = AT91SAM9261_BASE_RTT,
                .end    = AT91SAM9261_BASE_RTT + SZ_16 - 1,
                .flags  = IORESOURCE_MEM,
+       }, {
+               .flags  = IORESOURCE_MEM,
        }
 };
 
@@ -610,11 +613,32 @@ static struct platform_device at91sam9261_rtt_device = {
        .name           = "at91_rtt",
        .id             = 0,
        .resource       = rtt_resources,
-       .num_resources  = ARRAY_SIZE(rtt_resources),
 };
 
+#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
+static void __init at91_add_device_rtt_rtc(void)
+{
+       at91sam9261_rtt_device.name = "rtc-at91sam9";
+       /*
+        * The second resource is needed:
+        * GPBR will serve as the storage for RTC time offset
+        */
+       at91sam9261_rtt_device.num_resources = 2;
+       rtt_resources[1].start = AT91SAM9261_BASE_GPBR +
+                                4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
+       rtt_resources[1].end = rtt_resources[1].start + 3;
+}
+#else
+static void __init at91_add_device_rtt_rtc(void)
+{
+       /* Only one resource is needed: RTT not used as RTC */
+       at91sam9261_rtt_device.num_resources = 1;
+}
+#endif
+
 static void __init at91_add_device_rtt(void)
 {
+       at91_add_device_rtt_rtc();
        platform_device_register(&at91sam9261_rtt_device);
 }
 
@@ -991,7 +1015,6 @@ static inline void configure_usart2_pins(unsigned pins)
 }
 
 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];  /* the UARTs to use */
-struct platform_device *atmel_default_console_device;  /* the serial console device */
 
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
index 247ab633abccc72918d0e23be60c7e937deb5b61..0b4fa5a7f685907d03aa4efc89a758e0e26d4230 100644 (file)
@@ -303,20 +303,17 @@ static void __init at91sam9263_ioremap_registers(void)
 {
        at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
        at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
+       at91_ioremap_ramc(0, AT91SAM9263_BASE_SDRAMC0, 512);
+       at91_ioremap_ramc(1, AT91SAM9263_BASE_SDRAMC1, 512);
        at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
        at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
        at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
-}
-
-static void at91sam9263_idle(void)
-{
-       at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
-       cpu_do_idle();
+       at91_ioremap_matrix(AT91SAM9263_BASE_MATRIX);
 }
 
 static void __init at91sam9263_initialize(void)
 {
-       arm_pm_idle = at91sam9263_idle;
+       arm_pm_idle = at91sam9_idle;
        arm_pm_restart = at91sam9_alt_restart;
        at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
 
index 70709ab0102ad74f3f44354051b0d19ca4784598..53688c46f95652f02fced22b9d1979cd6799df1b 100644 (file)
@@ -23,6 +23,7 @@
 #include <mach/board.h>
 #include <mach/at91sam9263.h>
 #include <mach/at91sam9263_matrix.h>
+#include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
 
 #include "generic.h"
@@ -409,7 +410,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
         * we assume SMC timings are configured by board code,
         * except True IDE where timings are controlled by driver
         */
-       ebi0_csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
+       ebi0_csa = at91_matrix_read(AT91_MATRIX_EBI0CSA);
        switch (data->chipselect) {
        case 4:
                at91_set_A_periph(AT91_PIN_PD6, 0);  /* EBI0_NCS4/CFCS0 */
@@ -428,7 +429,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
                       data->chipselect);
                return;
        }
-       at91_sys_write(AT91_MATRIX_EBI0CSA, ebi0_csa);
+       at91_matrix_write(AT91_MATRIX_EBI0CSA, ebi0_csa);
 
        if (gpio_is_valid(data->det_pin)) {
                at91_set_gpio_input(data->det_pin, 1);
@@ -496,8 +497,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
        if (!data)
                return;
 
-       csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
-       at91_sys_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
+       csa = at91_matrix_read(AT91_MATRIX_EBI0CSA);
+       at91_matrix_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
 
        /* enable pin */
        if (gpio_is_valid(data->enable_pin))
@@ -966,6 +967,8 @@ static struct resource rtt0_resources[] = {
                .start  = AT91SAM9263_BASE_RTT0,
                .end    = AT91SAM9263_BASE_RTT0 + SZ_16 - 1,
                .flags  = IORESOURCE_MEM,
+       }, {
+               .flags  = IORESOURCE_MEM,
        }
 };
 
@@ -973,7 +976,6 @@ static struct platform_device at91sam9263_rtt0_device = {
        .name           = "at91_rtt",
        .id             = 0,
        .resource       = rtt0_resources,
-       .num_resources  = ARRAY_SIZE(rtt0_resources),
 };
 
 static struct resource rtt1_resources[] = {
@@ -981,6 +983,8 @@ static struct resource rtt1_resources[] = {
                .start  = AT91SAM9263_BASE_RTT1,
                .end    = AT91SAM9263_BASE_RTT1 + SZ_16 - 1,
                .flags  = IORESOURCE_MEM,
+       }, {
+               .flags  = IORESOURCE_MEM,
        }
 };
 
@@ -988,11 +992,53 @@ static struct platform_device at91sam9263_rtt1_device = {
        .name           = "at91_rtt",
        .id             = 1,
        .resource       = rtt1_resources,
-       .num_resources  = ARRAY_SIZE(rtt1_resources),
 };
 
+#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
+static void __init at91_add_device_rtt_rtc(void)
+{
+       struct platform_device *pdev;
+       struct resource *r;
+
+       switch (CONFIG_RTC_DRV_AT91SAM9_RTT) {
+       case 0:
+               /*
+                * The second resource is needed only for the chosen RTT:
+                * GPBR will serve as the storage for RTC time offset
+                */
+               at91sam9263_rtt0_device.num_resources = 2;
+               at91sam9263_rtt1_device.num_resources = 1;
+               pdev = &at91sam9263_rtt0_device;
+               r = rtt0_resources;
+               break;
+       case 1:
+               at91sam9263_rtt0_device.num_resources = 1;
+               at91sam9263_rtt1_device.num_resources = 2;
+               pdev = &at91sam9263_rtt1_device;
+               r = rtt1_resources;
+               break;
+       default:
+               pr_err("at91sam9263: only supports 2 RTT (%d)\n",
+                      CONFIG_RTC_DRV_AT91SAM9_RTT);
+               return;
+       }
+
+       pdev->name = "rtc-at91sam9";
+       r[1].start = AT91SAM9263_BASE_GPBR + 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
+       r[1].end = r[1].start + 3;
+}
+#else
+static void __init at91_add_device_rtt_rtc(void)
+{
+       /* Only one resource is needed: RTT not used as RTC */
+       at91sam9263_rtt0_device.num_resources = 1;
+       at91sam9263_rtt1_device.num_resources = 1;
+}
+#endif
+
 static void __init at91_add_device_rtt(void)
 {
+       at91_add_device_rtt_rtc();
        platform_device_register(&at91sam9263_rtt0_device);
        platform_device_register(&at91sam9263_rtt1_device);
 }
@@ -1378,7 +1424,6 @@ static inline void configure_usart2_pins(unsigned pins)
 }
 
 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];  /* the UARTs to use */
-struct platform_device *atmel_default_console_device;  /* the serial console device */
 
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
index d89ead740a99756b51492064eb7b3922226526e2..a94758b42737a3d33a3cdce0bee439103ea8f7ab 100644 (file)
@@ -14,6 +14,9 @@
 #include <linux/kernel.h>
 #include <linux/clk.h>
 #include <linux/clockchips.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 #include <asm/mach/time.h>
 
@@ -133,7 +136,8 @@ static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
 static struct irqaction at91sam926x_pit_irq = {
        .name           = "at91_tick",
        .flags          = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-       .handler        = at91sam926x_pit_interrupt
+       .handler        = at91sam926x_pit_interrupt,
+       .irq            = AT91_ID_SYS,
 };
 
 static void at91sam926x_pit_reset(void)
@@ -149,6 +153,51 @@ static void at91sam926x_pit_reset(void)
        pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
 }
 
+#ifdef CONFIG_OF
+static struct of_device_id pit_timer_ids[] = {
+       { .compatible = "atmel,at91sam9260-pit" },
+       { /* sentinel */ }
+};
+
+static int __init of_at91sam926x_pit_init(void)
+{
+       struct device_node      *np;
+       int                     ret;
+
+       np = of_find_matching_node(NULL, pit_timer_ids);
+       if (!np)
+               goto err;
+
+       pit_base_addr = of_iomap(np, 0);
+       if (!pit_base_addr)
+               goto node_err;
+
+       /* Get the interrupts property */
+       ret = irq_of_parse_and_map(np, 0);
+       if (!ret) {
+               pr_crit("AT91: PIT: Unable to get IRQ from DT\n");
+               goto ioremap_err;
+       }
+       at91sam926x_pit_irq.irq = ret;
+
+       of_node_put(np);
+
+       return 0;
+
+ioremap_err:
+       iounmap(pit_base_addr);
+node_err:
+       of_node_put(np);
+err:
+       return -EINVAL;
+}
+#else
+static int __init of_at91sam926x_pit_init(void)
+{
+       return -EINVAL;
+}
+#endif
+
 /*
  * Set up both clocksource and clockevent support.
  */
@@ -156,6 +205,10 @@ static void __init at91sam926x_pit_init(void)
 {
        unsigned long   pit_rate;
        unsigned        bits;
+       int             ret;
+
+       /* For device tree enabled device: initialize here */
+       of_at91sam926x_pit_init();
 
        /*
         * Use our actual MCK to figure out how many MCK/16 ticks per
@@ -177,7 +230,9 @@ static void __init at91sam926x_pit_init(void)
        clocksource_register_hz(&pit_clk, pit_rate);
 
        /* Set up irq handler */
-       setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq);
+       ret = setup_irq(at91sam926x_pit_irq.irq, &at91sam926x_pit_irq);
+       if (ret)
+               pr_crit("AT91: PIT: Unable to setup IRQ\n");
 
        /* Set up and register clockevents */
        pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
@@ -193,6 +248,15 @@ static void at91sam926x_pit_suspend(void)
 
 void __init at91sam926x_ioremap_pit(u32 addr)
 {
+#if defined(CONFIG_OF)
+       struct device_node *np =
+               of_find_matching_node(NULL, pit_timer_ids);
+
+       if (np) {
+               of_node_put(np);
+               return;
+       }
+#endif
        pit_base_addr = ioremap(addr, 16);
 
        if (!pit_base_addr)
index 518e42377171c8fb25e5888c8863f7b363721a99..7af2e108b8a057d65deb5b49a725b3881e9b00cd 100644 (file)
 
 #include <linux/linkage.h>
 #include <mach/hardware.h>
-#include <mach/at91sam9_sdramc.h>
+#include <mach/at91_ramc.h>
 #include <mach/at91_rstc.h>
 
                        .arm
 
                        .globl  at91sam9_alt_restart
 
-at91sam9_alt_restart:  ldr     r0, .at91_va_base_sdramc        @ preload constants
-                       ldr     r1, =at91_rstc_base
-                       ldr     r1, [r1]
+at91sam9_alt_restart:  ldr     r0, =at91_ramc_base             @ preload constants
+                       ldr     r0, [r0]
+                       ldr     r4, =at91_rstc_base
+                       ldr     r1, [r4]
 
                        mov     r2, #1
                        mov     r3, #AT91_SDRAMC_LPCB_POWER_DOWN
@@ -37,6 +38,3 @@ at91sam9_alt_restart: ldr     r0, .at91_va_base_sdramc        @ preload constants
                        str     r4, [r1, #AT91_RSTC_CR]         @ reset processor
 
                        b       .
-
-.at91_va_base_sdramc:
-       .word AT91_VA_BASE_SYS + AT91_SDRAMC0
index 5b12192e52ecc59e8fde425146f8811469149179..0014573dfe17cb293e1b303c52781de7c69d03c3 100644 (file)
@@ -229,6 +229,9 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
        CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
        CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
+       /* more tc lookup table for DT entries */
+       CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb0_clk),
+       CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
        /* fake hclk clock */
        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
        CLKDEV_CON_ID("pioA", &pioA_clk),
@@ -317,12 +320,6 @@ static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
        }
 };
 
-static void at91sam9g45_idle(void)
-{
-       at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
-       cpu_do_idle();
-}
-
 /* --------------------------------------------------------------------
  *  AT91SAM9G45 processor initialization
  * -------------------------------------------------------------------- */
@@ -337,13 +334,16 @@ static void __init at91sam9g45_ioremap_registers(void)
 {
        at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
        at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC);
+       at91_ioremap_ramc(0, AT91SAM9G45_BASE_DDRSDRC1, 512);
+       at91_ioremap_ramc(1, AT91SAM9G45_BASE_DDRSDRC0, 512);
        at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
        at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
+       at91_ioremap_matrix(AT91SAM9G45_BASE_MATRIX);
 }
 
 static void __init at91sam9g45_initialize(void)
 {
-       arm_pm_idle = at91sam9g45_idle;
+       arm_pm_idle = at91sam9_idle;
        arm_pm_restart = at91sam9g45_restart;
        at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
 
index bd4e68cd3e2f31d43c982a03f405c544cabb926a..4320b2096789c73a4c5110af51324472f80890c4 100644 (file)
@@ -25,6 +25,7 @@
 #include <mach/board.h>
 #include <mach/at91sam9g45.h>
 #include <mach/at91sam9g45_matrix.h>
+#include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at_hdmac.h>
 #include <mach/atmel-mci.h>
@@ -557,8 +558,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
        if (!data)
                return;
 
-       csa = at91_sys_read(AT91_MATRIX_EBICSA);
-       at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
+       csa = at91_matrix_read(AT91_MATRIX_EBICSA);
+       at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
 
        /* enable pin */
        if (gpio_is_valid(data->enable_pin))
@@ -1051,7 +1052,7 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
 static struct resource tcb0_resources[] = {
        [0] = {
                .start  = AT91SAM9G45_BASE_TCB0,
-               .end    = AT91SAM9G45_BASE_TCB0 + SZ_16K - 1,
+               .end    = AT91SAM9G45_BASE_TCB0 + SZ_256 - 1,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
@@ -1072,7 +1073,7 @@ static struct platform_device at91sam9g45_tcb0_device = {
 static struct resource tcb1_resources[] = {
        [0] = {
                .start  = AT91SAM9G45_BASE_TCB1,
-               .end    = AT91SAM9G45_BASE_TCB1 + SZ_16K - 1,
+               .end    = AT91SAM9G45_BASE_TCB1 + SZ_256 - 1,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
@@ -1089,8 +1090,25 @@ static struct platform_device at91sam9g45_tcb1_device = {
        .num_resources  = ARRAY_SIZE(tcb1_resources),
 };
 
+#if defined(CONFIG_OF)
+static struct of_device_id tcb_ids[] = {
+       { .compatible = "atmel,at91rm9200-tcb" },
+       { /*sentinel*/ }
+};
+#endif
+
 static void __init at91_add_device_tc(void)
 {
+#if defined(CONFIG_OF)
+       struct device_node *np;
+
+       np = of_find_matching_node(NULL, tcb_ids);
+       if (np) {
+               of_node_put(np);
+               return;
+       }
+#endif
+
        platform_device_register(&at91sam9g45_tcb0_device);
        platform_device_register(&at91sam9g45_tcb1_device);
 }
@@ -1193,6 +1211,8 @@ static struct resource rtt_resources[] = {
                .start  = AT91SAM9G45_BASE_RTT,
                .end    = AT91SAM9G45_BASE_RTT + SZ_16 - 1,
                .flags  = IORESOURCE_MEM,
+       }, {
+               .flags  = IORESOURCE_MEM,
        }
 };
 
@@ -1200,11 +1220,32 @@ static struct platform_device at91sam9g45_rtt_device = {
        .name           = "at91_rtt",
        .id             = 0,
        .resource       = rtt_resources,
-       .num_resources  = ARRAY_SIZE(rtt_resources),
 };
 
+#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
+static void __init at91_add_device_rtt_rtc(void)
+{
+       at91sam9g45_rtt_device.name = "rtc-at91sam9";
+       /*
+        * The second resource is needed:
+        * GPBR will serve as the storage for RTC time offset
+        */
+       at91sam9g45_rtt_device.num_resources = 2;
+       rtt_resources[1].start = AT91SAM9G45_BASE_GPBR +
+                                4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
+       rtt_resources[1].end = rtt_resources[1].start + 3;
+}
+#else
+static void __init at91_add_device_rtt_rtc(void)
+{
+       /* Only one resource is needed: RTT not used as RTC */
+       at91sam9g45_rtt_device.num_resources = 1;
+}
+#endif
+
 static void __init at91_add_device_rtt(void)
 {
+       at91_add_device_rtt_rtc();
        platform_device_register(&at91sam9g45_rtt_device);
 }
 
@@ -1659,7 +1700,6 @@ static inline void configure_usart3_pins(unsigned pins)
 }
 
 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];  /* the UARTs to use */
-struct platform_device *atmel_default_console_device;  /* the serial console device */
 
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
index 0468be10980b57dce18e057817cf3879fb39a545..9d457182c86c73f7ab5d3a0daef884781a518bbb 100644 (file)
@@ -12,7 +12,7 @@
 
 #include <linux/linkage.h>
 #include <mach/hardware.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ramc.h>
 #include <mach/at91_rstc.h>
 
                        .arm
                        .globl  at91sam9g45_restart
 
 at91sam9g45_restart:
-                       ldr     r0, .at91_va_base_sdramc0       @ preload constants
-                       ldr     r1, =at91_rstc_base
-                       ldr     r1, [r1]
+                       ldr     r5, =at91_ramc_base             @ preload constants
+                       ldr     r0, [r5]
+                       ldr     r4, =at91_rstc_base
+                       ldr     r1, [r4]
 
                        mov     r2, #1
                        mov     r3, #AT91_DDRSDRC_LPCB_POWER_DOWN
@@ -35,6 +36,3 @@ at91sam9g45_restart:
                        str     r4, [r1, #AT91_RSTC_CR]         @ reset processor
 
                        b       .
-
-.at91_va_base_sdramc0:
-       .word AT91_VA_BASE_SYS + AT91_DDRSDRC0
index fd60e226a987d1533504327dfe22e17a6a08b9d2..63d9372eb18efe2f9d476aa85c7d9e4f724ef4b7 100644 (file)
@@ -288,19 +288,15 @@ static void __init at91sam9rl_ioremap_registers(void)
 {
        at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
        at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
+       at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
        at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
        at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
-}
-
-static void at91sam9rl_idle(void)
-{
-       at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
-       cpu_do_idle();
+       at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
 }
 
 static void __init at91sam9rl_initialize(void)
 {
-       arm_pm_idle = at91sam9rl_idle;
+       arm_pm_idle = at91sam9_idle;
        arm_pm_restart = at91sam9_alt_restart;
        at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
 
index 9be71c11d0f098ddaadf4528cc2cdc1d17b52a3c..eda72e83037dc7dd176c859e7f4ad874a9506a75 100644 (file)
@@ -20,6 +20,7 @@
 #include <mach/board.h>
 #include <mach/at91sam9rl.h>
 #include <mach/at91sam9rl_matrix.h>
+#include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at_hdmac.h>
 
@@ -265,8 +266,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
        if (!data)
                return;
 
-       csa = at91_sys_read(AT91_MATRIX_EBICSA);
-       at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+       csa = at91_matrix_read(AT91_MATRIX_EBICSA);
+       at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
 
        /* enable pin */
        if (gpio_is_valid(data->enable_pin))
@@ -682,6 +683,8 @@ static struct resource rtt_resources[] = {
                .start  = AT91SAM9RL_BASE_RTT,
                .end    = AT91SAM9RL_BASE_RTT + SZ_16 - 1,
                .flags  = IORESOURCE_MEM,
+       }, {
+               .flags  = IORESOURCE_MEM,
        }
 };
 
@@ -689,11 +692,32 @@ static struct platform_device at91sam9rl_rtt_device = {
        .name           = "at91_rtt",
        .id             = 0,
        .resource       = rtt_resources,
-       .num_resources  = ARRAY_SIZE(rtt_resources),
 };
 
+#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
+static void __init at91_add_device_rtt_rtc(void)
+{
+       at91sam9rl_rtt_device.name = "rtc-at91sam9";
+       /*
+        * The second resource is needed:
+        * GPBR will serve as the storage for RTC time offset
+        */
+       at91sam9rl_rtt_device.num_resources = 2;
+       rtt_resources[1].start = AT91SAM9RL_BASE_GPBR +
+                                4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
+       rtt_resources[1].end = rtt_resources[1].start + 3;
+}
+#else
+static void __init at91_add_device_rtt_rtc(void)
+{
+       /* Only one resource is needed: RTT not used as RTC */
+       at91sam9rl_rtt_device.num_resources = 1;
+}
+#endif
+
 static void __init at91_add_device_rtt(void)
 {
+       at91_add_device_rtt_rtc();
        platform_device_register(&at91sam9rl_rtt_device);
 }
 
@@ -1128,7 +1152,6 @@ static inline void configure_usart3_pins(unsigned pins)
 }
 
 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];  /* the UARTs to use */
-struct platform_device *atmel_default_console_device;  /* the serial console device */
 
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
index 1c3444d2ee0c55ff88fd83453a2d0e96bb357b49..a34d96afa746ff6f45815d0503d2756ae7dd0f75 100644 (file)
@@ -301,8 +301,7 @@ static void __init at91sam9x5_map_io(void)
 
 static void __init at91sam9x5_ioremap_registers(void)
 {
-       if (of_at91sam926x_pit_init() < 0)
-               panic("Impossible to find PIT\n");
+       at91_ioremap_ramc(0, AT91SAM9X5_BASE_DDRSDRC0, 512);
 }
 
 void __init at91sam9x5_initialize(void)
@@ -317,10 +316,6 @@ void __init at91sam9x5_initialize(void)
 /* --------------------------------------------------------------------
  *  AT91SAM9x5 devices (temporary before modification of code)
  * -------------------------------------------------------------------- */
-void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
-void __init at91_set_serial_console(unsigned portnr) {}
-struct platform_device *atmel_default_console_device = NULL;
-
 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
 
 /* --------------------------------------------------------------------
index 0154b7f44ff199a72483c70a94dcffe11bfb60cf..5400a1d6503566d7258a801e6b8aca3e6c636021 100644 (file)
@@ -44,7 +44,7 @@ static void at91x40_idle(void)
         * Disable the processor clock.  The processor will be automatically
         * re-enabled by an interrupt or by a reset.
         */
-       at91_sys_write(AT91_PS_CR, AT91_PS_CR_CPU);
+       __raw_writel(AT91_PS_CR_CPU, AT91_PS_CR);
        cpu_do_idle();
 }
 
index dfff2895f4b286c4134a2a9f6425c90ce27e76ca..6ca680a1d5d112bb32cfa347c08c845f4d24ff6f 100644 (file)
 #include <asm/mach/time.h>
 #include <mach/at91_tc.h>
 
+#define at91_tc_read(field) \
+       __raw_readl(AT91_TC + field)
+
+#define at91_tc_write(field, value) \
+       __raw_writel(value, AT91_TC + field);
+
 /*
  *     3 counter/timer units present.
  */
 
 static unsigned long at91x40_gettimeoffset(void)
 {
-       return (at91_sys_read(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 / (AT91X40_MASTER_CLOCK / 128));
+       return (at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 / (AT91X40_MASTER_CLOCK / 128));
 }
 
 static irqreturn_t at91x40_timer_interrupt(int irq, void *dev_id)
 {
-       at91_sys_read(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_SR);
+       at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_SR);
        timer_tick();
        return IRQ_HANDLED;
 }
@@ -57,20 +63,20 @@ void __init at91x40_timer_init(void)
 {
        unsigned int v;
 
-       at91_sys_write(AT91_TC + AT91_TC_BCR, 0);
-       v = at91_sys_read(AT91_TC + AT91_TC_BMR);
+       at91_tc_write(AT91_TC_BCR, 0);
+       v = at91_tc_read(AT91_TC_BMR);
        v = (v & ~AT91_TC_TC1XC1S) | AT91_TC_TC1XC1S_NONE;
-       at91_sys_write(AT91_TC + AT91_TC_BMR, v);
+       at91_tc_write(AT91_TC_BMR, v);
 
-       at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CCR, AT91_TC_CLKDIS);
-       at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CMR, (AT91_TC_TIMER_CLOCK4 | AT91_TC_CPCTRG));
-       at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_IDR, 0xffffffff);
-       at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_RC, (AT91X40_MASTER_CLOCK / 128) / HZ - 1);
-       at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_IER, (1<<4));
+       at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, AT91_TC_CLKDIS);
+       at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CMR, (AT91_TC_TIMER_CLOCK4 | AT91_TC_CPCTRG));
+       at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IDR, 0xffffffff);
+       at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_RC, (AT91X40_MASTER_CLOCK / 128) / HZ - 1);
+       at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IER, (1<<4));
 
        setup_irq(AT91X40_ID_TC1, &at91x40_timer_irq);
 
-       at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN));
+       at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN));
 }
 
 struct sys_timer at91x40_timer = {
index 9ab3d1ea326d445bfe36bda16e37e47119a94f7a..989e1c5a9ca0428a8caca37bc18625bf3278502b 100644 (file)
@@ -43,6 +43,7 @@
 #include <mach/board.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91sam9260_matrix.h>
+#include <mach/at91_matrix.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
@@ -238,8 +239,8 @@ static __init void cpu9krea_add_device_nor(void)
 {
        unsigned long csa;
 
-       csa = at91_sys_read(AT91_MATRIX_EBICSA);
-       at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_VDDIOMSEL_3_3V);
+       csa = at91_matrix_read(AT91_MATRIX_EBICSA);
+       at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_VDDIOMSEL_3_3V);
 
        /* configure chip-select 0 (NOR) */
        sam9_smc_configure(0, 0, &cpu9krea_nor_smc_config);
index 368e1427ad998af7be547ed2689c6b5a0d0aacf4..e094cc81fe251d099fc31ceef5af8d9d2bfe1dd0 100644 (file)
@@ -38,6 +38,7 @@
 
 #include <mach/board.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 #include <mach/cpu.h>
 
 #include "generic.h"
index 05793156d1783949b6c3d6f7eae20f72d1f714f7..583b72472ad99f7ee9ee58e48382aa164c7c6bcc 100644 (file)
@@ -15,7 +15,7 @@
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/gpio.h>
-#include <linux/irqdomain.h>
+#include <linux/of.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 
@@ -38,12 +38,6 @@ static void __init ek_init_early(void)
 {
        /* Initialize processor: 12.000 MHz crystal */
        at91_initialize(12000000);
-
-       /* DGBU on ttyS0. (Rx & Tx only) */
-       at91_register_uart(0, 0, 0);
-
-       /* set serial console to ttyS0 (ie, DBGU) */
-       at91_set_serial_console(0);
 }
 
 /* det_pin is not connected */
@@ -88,15 +82,17 @@ static void __init ek_add_device_nand(void)
        at91_add_device_nand(&ek_nand_data);
 }
 
-static const struct of_device_id aic_of_match[] __initconst = {
-       { .compatible = "atmel,at91rm9200-aic", },
-       {},
+static const struct of_device_id irq_of_match[] __initconst = {
+
+       { .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
+       { .compatible = "atmel,at91rm9200-gpio", .data = at91_gpio_of_irq_setup },
+       { .compatible = "atmel,at91sam9x5-gpio", .data = at91_gpio_of_irq_setup },
+       { /*sentinel*/ }
 };
 
 static void __init at91_dt_init_irq(void)
 {
-       irq_domain_generate_simple(aic_of_match, 0xfffff000, 0);
-       at91_init_irq_default();
+       of_irq_init(irq_of_match);
 }
 
 static void __init at91_dt_device_init(void)
index 07ef35b0ec2cdceecf7e124e705cb842c31b1b62..f23aabef8551d69fc395dcf88b5eabdf152fe2f8 100644 (file)
@@ -26,6 +26,7 @@
 
 #include <mach/board.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 #include <mach/cpu.h>
 
 #include "generic.h"
@@ -110,7 +111,7 @@ static void __init eco920_board_init(void)
        at91_add_device_mmc(0, &eco920_mmc_data);
        platform_device_register(&eco920_flash);
 
-       at91_sys_write(AT91_SMC_CSR(7), AT91_SMC_RWHOLD_(1)
+       at91_ramc_write(0, AT91_SMC_CSR(7),     AT91_SMC_RWHOLD_(1)
                                | AT91_SMC_RWSETUP_(1)
                                | AT91_SMC_DBW_8
                                | AT91_SMC_WSEN
@@ -122,7 +123,7 @@ static void __init eco920_board_init(void)
        at91_set_deglitch(AT91_PIN_PA23, 1);
 
 /* Initialization of the Static Memory Controller for Chip Select 3 */
-       at91_sys_write(AT91_SMC_CSR(3),
+       at91_ramc_write(0, AT91_SMC_CSR(3),
                AT91_SMC_DBW_16  |      /* 16 bit */
                AT91_SMC_WSEN    |
                AT91_SMC_NWS_(5) |      /* wait states */
index d75a4a2ad9c20bc9d1e13067c5f6db4d689bbc9c..bb9914582013684336c958e8a3ca53f8f3f7a942 100644 (file)
@@ -38,6 +38,7 @@
 #include <mach/board.h>
 #include <mach/cpu.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 
 #include "generic.h"
 
index ab024fa11d5c7d1011086070178b1e7dc3f04ca6..59e35dd1486301b556f20befed659a5bea9525b2 100644 (file)
@@ -39,6 +39,7 @@
 
 #include <mach/board.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 
 #include "generic.h"
 
index 782f37946af5b561ea066d491ce51f4cd645c44e..9083df04e7edb669b6f2fc1de5344964b47e94be 100644 (file)
@@ -41,6 +41,7 @@
 #include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 
 #include "generic.h"
 
index ef7c12a922464d3accbd06e263a2e548115906ac..11cbaa8946fe0e269877104aac08da9fe03818e9 100644 (file)
@@ -41,6 +41,7 @@
 #include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 
 #include "generic.h"
 
index 4770db08e5a6c1895b52794d02eba84b499da56c..3c2e3fcc310c09668f10555dbdc1a530a35dd89f 100644 (file)
@@ -145,11 +145,11 @@ static struct i2c_board_info __initdata snapper9260_i2c_devices[] = {
                /* Audio codec */
                I2C_BOARD_INFO("tlv320aic23", 0x1a),
        },
-       {
+};
+
+static struct i2c_board_info __initdata snapper9260_i2c_isl1208 = {
                /* RTC */
                I2C_BOARD_INFO("isl1208", 0x6f),
-               .irq = gpio_to_irq(AT91_PIN_PA31),
-       },
 };
 
 static void __init snapper9260_add_device_nand(void)
@@ -163,6 +163,10 @@ static void __init snapper9260_board_init(void)
 {
        at91_add_device_i2c(snapper9260_i2c_devices,
                            ARRAY_SIZE(snapper9260_i2c_devices));
+
+       snapper9260_i2c_isl1208.irq = gpio_to_irq(AT91_PIN_PA31);
+       i2c_register_board_info(0, &snapper9260_i2c_isl1208, 1);
+
        at91_add_device_serial();
        at91_add_device_usbh(&snapper9260_usbh_data);
        at91_add_device_udc(&snapper9260_udc_data);
index bbd553e1cd93d024cc4b8c5931f989c3a5becbfa..52f460768f71ef758bb541c85735b722acc6be6e 100644 (file)
@@ -45,6 +45,7 @@
 #include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 #include <mach/cpu.h>
 
 #include "generic.h"
@@ -393,7 +394,7 @@ static void yl9200_init_video(void)
        at91_set_A_periph(AT91_PIN_PC6, 0);
 
        /* Initialization of the Static Memory Controller for Chip Select 2 */
-       at91_sys_write(AT91_SMC_CSR(2), AT91_SMC_DBW_16         /* 16 bit */
+       at91_ramc_write(0, AT91_SMC_CSR(2), AT91_SMC_DBW_16             /* 16 bit */
                        | AT91_SMC_WSEN | AT91_SMC_NWS_(0x4)    /* wait states */
                        | AT91_SMC_TDF_(0x100)                  /* float time */
        );
index a5291e0e7004aa4431486a77a0d935a53a4ece8f..be51ca7f694d1a0515ddd9d5ecf0c4a9253dc078 100644 (file)
 #include <mach/at91_pmc.h>
 #include <mach/cpu.h>
 
+#include <asm/proc-fns.h>
+
 #include "clock.h"
 #include "generic.h"
 
+void __iomem *at91_pmc_base;
 
 /*
  * There's a lot more which can be done with clocks, including cpufreq
@@ -123,11 +126,11 @@ static void pllb_mode(struct clk *clk, int is_on)
                value = 0;
 
        // REVISIT: Add work-around for AT91RM9200 Errata #26 ?
-       at91_sys_write(AT91_CKGR_PLLBR, value);
+       at91_pmc_write(AT91_CKGR_PLLBR, value);
 
        do {
                cpu_relax();
-       } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
+       } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
 }
 
 static struct clk pllb = {
@@ -142,24 +145,24 @@ static struct clk pllb = {
 static void pmc_sys_mode(struct clk *clk, int is_on)
 {
        if (is_on)
-               at91_sys_write(AT91_PMC_SCER, clk->pmc_mask);
+               at91_pmc_write(AT91_PMC_SCER, clk->pmc_mask);
        else
-               at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
+               at91_pmc_write(AT91_PMC_SCDR, clk->pmc_mask);
 }
 
 static void pmc_uckr_mode(struct clk *clk, int is_on)
 {
-       unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
+       unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR);
 
        if (is_on) {
                is_on = AT91_PMC_LOCKU;
-               at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
+               at91_pmc_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
        } else
-               at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
+               at91_pmc_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
 
        do {
                cpu_relax();
-       } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
+       } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
 }
 
 /* USB function clocks (PLLB must be 48 MHz) */
@@ -195,9 +198,9 @@ struct clk mck = {
 static void pmc_periph_mode(struct clk *clk, int is_on)
 {
        if (is_on)
-               at91_sys_write(AT91_PMC_PCER, clk->pmc_mask);
+               at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask);
        else
-               at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask);
+               at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask);
 }
 
 static struct clk __init *at91_css_to_clk(unsigned long css)
@@ -357,10 +360,10 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
                if (actual && actual <= rate) {
                        u32     pckr;
 
-                       pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
+                       pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
                        pckr &= css_mask;       /* keep clock selection */
                        pckr |= prescale << prescale_offset;
-                       at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
+                       at91_pmc_write(AT91_PMC_PCKR(clk->id), pckr);
                        clk->rate_hz = actual;
                        break;
                }
@@ -394,7 +397,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
 
        clk->rate_hz = parent->rate_hz;
        clk->parent = parent;
-       at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id);
+       at91_pmc_write(AT91_PMC_PCKR(clk->id), parent->id);
 
        spin_unlock_irqrestore(&clk_lock, flags);
        return 0;
@@ -413,7 +416,7 @@ static void __init init_programmable_clock(struct clk *clk)
        else
                css_mask = AT91_PMC_CSS;
 
-       pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
+       pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
        parent = at91_css_to_clk(pckr & css_mask);
        clk->parent = parent;
        clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr);
@@ -430,19 +433,24 @@ static int at91_clk_show(struct seq_file *s, void *unused)
        u32             scsr, pcsr, uckr = 0, sr;
        struct clk      *clk;
 
-       seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
-       seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR));
-       seq_printf(s, "MOR  = %8x\n", at91_sys_read(AT91_CKGR_MOR));
-       seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
-       seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
+       scsr = at91_pmc_read(AT91_PMC_SCSR);
+       pcsr = at91_pmc_read(AT91_PMC_PCSR);
+       sr = at91_pmc_read(AT91_PMC_SR);
+       seq_printf(s, "SCSR = %8x\n", scsr);
+       seq_printf(s, "PCSR = %8x\n", pcsr);
+       seq_printf(s, "MOR  = %8x\n", at91_pmc_read(AT91_CKGR_MOR));
+       seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR));
+       seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR));
        if (cpu_has_pllb())
-               seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
-       if (cpu_has_utmi())
-               seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR));
-       seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
+               seq_printf(s, "PLLB = %8x\n", at91_pmc_read(AT91_CKGR_PLLBR));
+       if (cpu_has_utmi()) {
+               uckr = at91_pmc_read(AT91_CKGR_UCKR);
+               seq_printf(s, "UCKR = %8x\n", uckr);
+       }
+       seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR));
        if (cpu_has_upll())
-               seq_printf(s, "USB  = %8x\n", at91_sys_read(AT91_PMC_USB));
-       seq_printf(s, "SR   = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
+               seq_printf(s, "USB  = %8x\n", at91_pmc_read(AT91_PMC_USB));
+       seq_printf(s, "SR   = %8x\n", sr);
 
        seq_printf(s, "\n");
 
@@ -630,14 +638,14 @@ static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
        if (cpu_is_at91rm9200()) {
                uhpck.pmc_mask = AT91RM9200_PMC_UHP;
                udpck.pmc_mask = AT91RM9200_PMC_UDP;
-               at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
+               at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
        } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
                   cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
                   cpu_is_at91sam9g10()) {
                uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
                udpck.pmc_mask = AT91SAM926x_PMC_UDP;
        }
-       at91_sys_write(AT91_CKGR_PLLBR, 0);
+       at91_pmc_write(AT91_CKGR_PLLBR, 0);
 
        udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
        uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
@@ -654,13 +662,13 @@ static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
        /* Setup divider by 10 to reach 48 MHz */
        usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
 
-       at91_sys_write(AT91_PMC_USB, usbr);
+       at91_pmc_write(AT91_PMC_USB, usbr);
 
        /* Now set uhpck values */
        uhpck.parent = &utmi_clk;
        uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
        uhpck.rate_hz = utmi_clk.rate_hz;
-       uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
+       uhpck.rate_hz /= 1 + ((at91_pmc_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
 }
 
 int __init at91_clock_init(unsigned long main_clock)
@@ -669,6 +677,10 @@ int __init at91_clock_init(unsigned long main_clock)
        int i;
        int pll_overclock = false;
 
+       at91_pmc_base = ioremap(AT91_PMC, 256);
+       if (!at91_pmc_base)
+               panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC);
+
        /*
         * When the bootloader initialized the main oscillator correctly,
         * there's no problem using the cycle counter.  But if it didn't,
@@ -677,14 +689,14 @@ int __init at91_clock_init(unsigned long main_clock)
         */
        if (!main_clock) {
                do {
-                       tmp = at91_sys_read(AT91_CKGR_MCFR);
+                       tmp = at91_pmc_read(AT91_CKGR_MCFR);
                } while (!(tmp & AT91_PMC_MAINRDY));
                main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
        }
        main_clk.rate_hz = main_clock;
 
        /* report if PLLA is more than mildly overclocked */
-       plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
+       plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR));
        if (cpu_has_300M_plla()) {
                if (plla.rate_hz > 300000000)
                        pll_overclock = true;
@@ -699,7 +711,7 @@ int __init at91_clock_init(unsigned long main_clock)
                pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
 
        if (cpu_has_plladiv2()) {
-               mckr = at91_sys_read(AT91_PMC_MCKR);
+               mckr = at91_pmc_read(AT91_PMC_MCKR);
                plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12));      /* plla divisor by 2 */
        }
 
@@ -739,7 +751,7 @@ int __init at91_clock_init(unsigned long main_clock)
         * MCK and CPU derive from one of those primary clocks.
         * For now, assume this parentage won't change.
         */
-       mckr = at91_sys_read(AT91_PMC_MCKR);
+       mckr = at91_pmc_read(AT91_PMC_MCKR);
        mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
        freq = mck.parent->rate_hz;
        freq /= pmc_prescaler_divider(mckr);                                    /* prescale */
@@ -812,9 +824,15 @@ static int __init at91_clock_reset(void)
                pr_debug("Clocks: disable unused %s\n", clk->name);
        }
 
-       at91_sys_write(AT91_PMC_PCDR, pcdr);
-       at91_sys_write(AT91_PMC_SCDR, scdr);
+       at91_pmc_write(AT91_PMC_PCDR, pcdr);
+       at91_pmc_write(AT91_PMC_SCDR, scdr);
 
        return 0;
 }
 late_initcall(at91_clock_reset);
+
+void at91sam9_idle(void)
+{
+       at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
+       cpu_do_idle();
+}
index 7e8280e798c11620e7cb2eac404d37c8c506a1e7..459f01a4a54699755eda4a2601d3b7562c963335 100644 (file)
@@ -9,6 +9,7 @@
  */
 
 #include <linux/clkdev.h>
+#include <linux/of.h>
 
  /* Map io */
 extern void __init at91_map_io(void);
@@ -25,9 +26,13 @@ extern void __init at91_init_irq_default(void);
 extern void __init at91_init_interrupts(unsigned int priority[]);
 extern void __init at91x40_init_interrupts(unsigned int priority[]);
 extern void __init at91_aic_init(unsigned int priority[]);
+extern int  __init at91_aic_of_init(struct device_node *node,
+                                   struct device_node *parent);
+
 
  /* Timer */
 struct sys_timer;
+extern void at91rm9200_ioremap_st(u32 addr);
 extern struct sys_timer at91rm9200_timer;
 extern void at91sam926x_ioremap_pit(u32 addr);
 extern struct sys_timer at91sam926x_timer;
@@ -56,6 +61,9 @@ struct device;
 extern void at91_irq_suspend(void);
 extern void at91_irq_resume(void);
 
+/* idle */
+extern void at91sam9_idle(void);
+
 /* reset */
 extern void at91_ioremap_rstc(u32 base_addr);
 extern void at91sam9_alt_restart(char, const char *);
@@ -64,6 +72,12 @@ extern void at91sam9g45_restart(char, const char *);
 /* shutdown */
 extern void at91_ioremap_shdwc(u32 base_addr);
 
+/* Matrix */
+extern void at91_ioremap_matrix(u32 base_addr);
+
+/* Ram Controler */
+extern void at91_ioremap_ramc(int id, u32 addr, u32 size);
+
  /* GPIO */
 #define AT91RM9200_PQFP                3       /* AT91RM9200 PQFP package has 3 banks */
 #define AT91RM9200_BGA         4       /* AT91RM9200 BGA package has 4 banks */
@@ -74,5 +88,7 @@ struct at91_gpio_bank {
 };
 extern void __init at91_gpio_init(struct at91_gpio_bank *, int nr_banks);
 extern void __init at91_gpio_irq_setup(void);
+extern int  __init at91_gpio_of_irq_setup(struct device_node *node,
+                                         struct device_node *parent);
 
 extern int at91_extern_irq;
index 74d6783eeabbb976c4261d299fcfe11b70d83984..325837a264c930fdbe1787d3ed2e61d3f75d1772 100644 (file)
@@ -11,6 +11,7 @@
 
 #include <linux/clk.h>
 #include <linux/errno.h>
+#include <linux/device.h>
 #include <linux/gpio.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/list.h>
 #include <linux/module.h>
 #include <linux/io.h>
+#include <linux/irqdomain.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_gpio.h>
 
 #include <mach/hardware.h>
 #include <mach/at91_pio.h>
 struct at91_gpio_chip {
        struct gpio_chip        chip;
        struct at91_gpio_chip   *next;          /* Bank sharing same clock */
-       int                     id;             /* ID of register bank */
-       void __iomem            *regbase;       /* Base of register bank */
+       int                     pioc_hwirq;     /* PIO bank interrupt identifier on AIC */
+       int                     pioc_virq;      /* PIO bank Linux virtual interrupt */
+       int                     pioc_idx;       /* PIO bank index */
+       void __iomem            *regbase;       /* PIO bank virtual address */
        struct clk              *clock;         /* associated clock */
+       struct irq_domain       *domain;        /* associated irq domain */
 };
 
 #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
@@ -43,8 +51,9 @@ static int at91_gpiolib_direction_output(struct gpio_chip *chip,
                                         unsigned offset, int val);
 static int at91_gpiolib_direction_input(struct gpio_chip *chip,
                                        unsigned offset);
+static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset);
 
-#define AT91_GPIO_CHIP(name, base_gpio, nr_gpio)                       \
+#define AT91_GPIO_CHIP(name, nr_gpio)                                  \
        {                                                               \
                .chip = {                                               \
                        .label            = name,                       \
@@ -53,20 +62,28 @@ static int at91_gpiolib_direction_input(struct gpio_chip *chip,
                        .get              = at91_gpiolib_get,           \
                        .set              = at91_gpiolib_set,           \
                        .dbg_show         = at91_gpiolib_dbg_show,      \
-                       .base             = base_gpio,                  \
+                       .to_irq           = at91_gpiolib_to_irq,        \
                        .ngpio            = nr_gpio,                    \
                },                                                      \
        }
 
 static struct at91_gpio_chip gpio_chip[] = {
-       AT91_GPIO_CHIP("pioA", 0x00, 32),
-       AT91_GPIO_CHIP("pioB", 0x20, 32),
-       AT91_GPIO_CHIP("pioC", 0x40, 32),
-       AT91_GPIO_CHIP("pioD", 0x60, 32),
-       AT91_GPIO_CHIP("pioE", 0x80, 32),
+       AT91_GPIO_CHIP("pioA", 32),
+       AT91_GPIO_CHIP("pioB", 32),
+       AT91_GPIO_CHIP("pioC", 32),
+       AT91_GPIO_CHIP("pioD", 32),
+       AT91_GPIO_CHIP("pioE", 32),
 };
 
 static int gpio_banks;
+static unsigned long at91_gpio_caps;
+
+/* All PIO controllers support PIO3 features */
+#define AT91_GPIO_CAP_PIO3     (1 <<  0)
+
+#define has_pio3()     (at91_gpio_caps & AT91_GPIO_CAP_PIO3)
+
+/*--------------------------------------------------------------------------*/
 
 static inline void __iomem *pin_to_controller(unsigned pin)
 {
@@ -83,6 +100,25 @@ static inline unsigned pin_to_mask(unsigned pin)
 }
 
 
+static char peripheral_function(void __iomem *pio, unsigned mask)
+{
+       char    ret = 'X';
+       u8      select;
+
+       if (pio) {
+               if (has_pio3()) {
+                       select = !!(__raw_readl(pio + PIO_ABCDSR1) & mask);
+                       select |= (!!(__raw_readl(pio + PIO_ABCDSR2) & mask) << 1);
+                       ret = 'A' + select;
+               } else {
+                       ret = __raw_readl(pio + PIO_ABSR) & mask ?
+                                                       'B' : 'A';
+               }
+       }
+
+       return ret;
+}
+
 /*--------------------------------------------------------------------------*/
 
 /* Not all hardware capabilities are exposed through these calls; they
@@ -130,7 +166,14 @@ int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
 
        __raw_writel(mask, pio + PIO_IDR);
        __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
-       __raw_writel(mask, pio + PIO_ASR);
+       if (has_pio3()) {
+               __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask,
+                                                       pio + PIO_ABCDSR1);
+               __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
+                                                       pio + PIO_ABCDSR2);
+       } else {
+               __raw_writel(mask, pio + PIO_ASR);
+       }
        __raw_writel(mask, pio + PIO_PDR);
        return 0;
 }
@@ -150,7 +193,14 @@ int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
 
        __raw_writel(mask, pio + PIO_IDR);
        __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
-       __raw_writel(mask, pio + PIO_BSR);
+       if (has_pio3()) {
+               __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask,
+                                                       pio + PIO_ABCDSR1);
+               __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
+                                                       pio + PIO_ABCDSR2);
+       } else {
+               __raw_writel(mask, pio + PIO_BSR);
+       }
        __raw_writel(mask, pio + PIO_PDR);
        return 0;
 }
@@ -158,8 +208,50 @@ EXPORT_SYMBOL(at91_set_B_periph);
 
 
 /*
- * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
- * configure it for an input.
+ * mux the pin to the "C" internal peripheral role.
+ */
+int __init_or_module at91_set_C_periph(unsigned pin, int use_pullup)
+{
+       void __iomem    *pio = pin_to_controller(pin);
+       unsigned        mask = pin_to_mask(pin);
+
+       if (!pio || !has_pio3())
+               return -EINVAL;
+
+       __raw_writel(mask, pio + PIO_IDR);
+       __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
+       __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
+       __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
+       __raw_writel(mask, pio + PIO_PDR);
+       return 0;
+}
+EXPORT_SYMBOL(at91_set_C_periph);
+
+
+/*
+ * mux the pin to the "D" internal peripheral role.
+ */
+int __init_or_module at91_set_D_periph(unsigned pin, int use_pullup)
+{
+       void __iomem    *pio = pin_to_controller(pin);
+       unsigned        mask = pin_to_mask(pin);
+
+       if (!pio || !has_pio3())
+               return -EINVAL;
+
+       __raw_writel(mask, pio + PIO_IDR);
+       __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
+       __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
+       __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
+       __raw_writel(mask, pio + PIO_PDR);
+       return 0;
+}
+EXPORT_SYMBOL(at91_set_D_periph);
+
+
+/*
+ * mux the pin to the gpio controller (instead of "A", "B", "C"
+ * or "D" peripheral), and configure it for an input.
  */
 int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
 {
@@ -179,8 +271,8 @@ EXPORT_SYMBOL(at91_set_gpio_input);
 
 
 /*
- * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
- * and configure it for an output.
+ * mux the pin to the gpio controller (instead of "A", "B", "C"
+ * or "D" peripheral), and configure it for an output.
  */
 int __init_or_module at91_set_gpio_output(unsigned pin, int value)
 {
@@ -210,11 +302,36 @@ int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
 
        if (!pio)
                return -EINVAL;
+
+       if (has_pio3() && is_on)
+               __raw_writel(mask, pio + PIO_IFSCDR);
        __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
        return 0;
 }
 EXPORT_SYMBOL(at91_set_deglitch);
 
+/*
+ * enable/disable the debounce filter;
+ */
+int __init_or_module at91_set_debounce(unsigned pin, int is_on, int div)
+{
+       void __iomem    *pio = pin_to_controller(pin);
+       unsigned        mask = pin_to_mask(pin);
+
+       if (!pio || !has_pio3())
+               return -EINVAL;
+
+       if (is_on) {
+               __raw_writel(mask, pio + PIO_IFSCER);
+               __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
+               __raw_writel(mask, pio + PIO_IFER);
+       } else {
+               __raw_writel(mask, pio + PIO_IFDR);
+       }
+       return 0;
+}
+EXPORT_SYMBOL(at91_set_debounce);
+
 /*
  * enable/disable the multi-driver; This is only valid for output and
  * allows the output pin to run as an open collector output.
@@ -232,6 +349,41 @@ int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
 }
 EXPORT_SYMBOL(at91_set_multi_drive);
 
+/*
+ * enable/disable the pull-down.
+ * If pull-up already enabled while calling the function, we disable it.
+ */
+int __init_or_module at91_set_pulldown(unsigned pin, int is_on)
+{
+       void __iomem    *pio = pin_to_controller(pin);
+       unsigned        mask = pin_to_mask(pin);
+
+       if (!pio || !has_pio3())
+               return -EINVAL;
+
+       /* Disable pull-up anyway */
+       __raw_writel(mask, pio + PIO_PUDR);
+       __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
+       return 0;
+}
+EXPORT_SYMBOL(at91_set_pulldown);
+
+/*
+ * disable Schmitt trigger
+ */
+int __init_or_module at91_disable_schmitt_trig(unsigned pin)
+{
+       void __iomem    *pio = pin_to_controller(pin);
+       unsigned        mask = pin_to_mask(pin);
+
+       if (!pio || !has_pio3())
+               return -EINVAL;
+
+       __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
+       return 0;
+}
+EXPORT_SYMBOL(at91_disable_schmitt_trig);
+
 /*
  * assuming the pin is muxed as a gpio output, set its value.
  */
@@ -273,9 +425,9 @@ static u32 backups[MAX_GPIO_BANKS];
 
 static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
 {
-       unsigned        pin = irq_to_gpio(d->irq);
-       unsigned        mask = pin_to_mask(pin);
-       unsigned        bank = pin / 32;
+       struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
+       unsigned        mask = 1 << d->hwirq;
+       unsigned        bank = at91_gpio->pioc_idx;
 
        if (unlikely(bank >= MAX_GPIO_BANKS))
                return -EINVAL;
@@ -285,7 +437,7 @@ static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
        else
                wakeups[bank] &= ~mask;
 
-       irq_set_irq_wake(gpio_chip[bank].id, state);
+       irq_set_irq_wake(at91_gpio->pioc_virq, state);
 
        return 0;
 }
@@ -301,9 +453,10 @@ void at91_gpio_suspend(void)
                __raw_writel(backups[i], pio + PIO_IDR);
                __raw_writel(wakeups[i], pio + PIO_IER);
 
-               if (!wakeups[i])
+               if (!wakeups[i]) {
+                       clk_unprepare(gpio_chip[i].clock);
                        clk_disable(gpio_chip[i].clock);
-               else {
+               else {
 #ifdef CONFIG_PM_DEBUG
                        printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]);
 #endif
@@ -318,8 +471,10 @@ void at91_gpio_resume(void)
        for (i = 0; i < gpio_banks; i++) {
                void __iomem    *pio = gpio_chip[i].regbase;
 
-               if (!wakeups[i])
-                       clk_enable(gpio_chip[i].clock);
+               if (!wakeups[i]) {
+                       if (clk_prepare(gpio_chip[i].clock) == 0)
+                               clk_enable(gpio_chip[i].clock);
+               }
 
                __raw_writel(wakeups[i], pio + PIO_IDR);
                __raw_writel(backups[i], pio + PIO_IER);
@@ -335,7 +490,10 @@ void at91_gpio_resume(void)
  * To use any AT91_PIN_* as an externally triggered IRQ, first call
  * at91_set_gpio_input() then maybe enable its glitch filter.
  * Then just request_irq() with the pin ID; it works like any ARM IRQ
- * handler, though it always triggers on rising and falling edges.
+ * handler.
+ * First implementation always triggers on rising and falling edges
+ * whereas the newer PIO3 can be additionally configured to trigger on
+ * level, edge with any polarity.
  *
  * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
  * configuring them with at91_set_a_periph() or at91_set_b_periph().
@@ -344,9 +502,9 @@ void at91_gpio_resume(void)
 
 static void gpio_irq_mask(struct irq_data *d)
 {
-       unsigned        pin = irq_to_gpio(d->irq);
-       void __iomem    *pio = pin_to_controller(pin);
-       unsigned        mask = pin_to_mask(pin);
+       struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
+       void __iomem    *pio = at91_gpio->regbase;
+       unsigned        mask = 1 << d->hwirq;
 
        if (pio)
                __raw_writel(mask, pio + PIO_IDR);
@@ -354,9 +512,9 @@ static void gpio_irq_mask(struct irq_data *d)
 
 static void gpio_irq_unmask(struct irq_data *d)
 {
-       unsigned        pin = irq_to_gpio(d->irq);
-       void __iomem    *pio = pin_to_controller(pin);
-       unsigned        mask = pin_to_mask(pin);
+       struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
+       void __iomem    *pio = at91_gpio->regbase;
+       unsigned        mask = 1 << d->hwirq;
 
        if (pio)
                __raw_writel(mask, pio + PIO_IER);
@@ -373,23 +531,66 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
        }
 }
 
+/* Alternate irq type for PIO3 support */
+static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
+{
+       struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
+       void __iomem    *pio = at91_gpio->regbase;
+       unsigned        mask = 1 << d->hwirq;
+
+       switch (type) {
+       case IRQ_TYPE_EDGE_RISING:
+               __raw_writel(mask, pio + PIO_ESR);
+               __raw_writel(mask, pio + PIO_REHLSR);
+               break;
+       case IRQ_TYPE_EDGE_FALLING:
+               __raw_writel(mask, pio + PIO_ESR);
+               __raw_writel(mask, pio + PIO_FELLSR);
+               break;
+       case IRQ_TYPE_LEVEL_LOW:
+               __raw_writel(mask, pio + PIO_LSR);
+               __raw_writel(mask, pio + PIO_FELLSR);
+               break;
+       case IRQ_TYPE_LEVEL_HIGH:
+               __raw_writel(mask, pio + PIO_LSR);
+               __raw_writel(mask, pio + PIO_REHLSR);
+               break;
+       case IRQ_TYPE_EDGE_BOTH:
+               /*
+                * disable additional interrupt modes:
+                * fall back to default behavior
+                */
+               __raw_writel(mask, pio + PIO_AIMDR);
+               return 0;
+       case IRQ_TYPE_NONE:
+       default:
+               pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq));
+               return -EINVAL;
+       }
+
+       /* enable additional interrupt modes */
+       __raw_writel(mask, pio + PIO_AIMER);
+
+       return 0;
+}
+
 static struct irq_chip gpio_irqchip = {
        .name           = "GPIO",
        .irq_disable    = gpio_irq_mask,
        .irq_mask       = gpio_irq_mask,
        .irq_unmask     = gpio_irq_unmask,
-       .irq_set_type   = gpio_irq_type,
+       /* .irq_set_type is set dynamically */
        .irq_set_wake   = gpio_irq_set_wake,
 };
 
 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 {
-       unsigned        irq_pin;
        struct irq_data *idata = irq_desc_get_irq_data(desc);
        struct irq_chip *chip = irq_data_get_irq_chip(idata);
        struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
        void __iomem    *pio = at91_gpio->regbase;
-       u32             isr;
+       unsigned long   isr;
+       int             n;
 
        /* temporarily mask (level sensitive) parent IRQ */
        chip->irq_ack(idata);
@@ -407,13 +608,10 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
                        continue;
                }
 
-               irq_pin = gpio_to_irq(at91_gpio->chip.base);
-
-               while (isr) {
-                       if (isr & 1)
-                               generic_handle_irq(irq_pin);
-                       irq_pin++;
-                       isr >>= 1;
+               n = find_first_bit(&isr, BITS_PER_LONG);
+               while (n < BITS_PER_LONG) {
+                       generic_handle_irq(irq_find_mapping(at91_gpio->domain, n));
+                       n = find_next_bit(&isr, BITS_PER_LONG, n + 1);
                }
        }
        chip->irq_unmask(idata);
@@ -424,6 +622,33 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 
 #ifdef CONFIG_DEBUG_FS
 
+static void gpio_printf(struct seq_file *s, void __iomem *pio, unsigned mask)
+{
+       char    *trigger = NULL;
+       char    *polarity = NULL;
+
+       if (__raw_readl(pio + PIO_IMR) & mask) {
+               if (!has_pio3() || !(__raw_readl(pio + PIO_AIMMR) & mask )) {
+                       trigger = "edge";
+                       polarity = "both";
+               } else {
+                       if (__raw_readl(pio + PIO_ELSR) & mask) {
+                               trigger = "level";
+                               polarity = __raw_readl(pio + PIO_FRLHSR) & mask ?
+                                       "high" : "low";
+                       } else {
+                               trigger = "edge";
+                               polarity = __raw_readl(pio + PIO_FRLHSR) & mask ?
+                                               "rising" : "falling";
+                       }
+               }
+               seq_printf(s, "IRQ:%s-%s\t", trigger, polarity);
+       } else {
+               seq_printf(s, "GPIO:%s\t\t",
+                               __raw_readl(pio + PIO_PDSR) & mask ? "1" : "0");
+       }
+}
+
 static int at91_gpio_show(struct seq_file *s, void *unused)
 {
        int bank, j;
@@ -431,7 +656,7 @@ static int at91_gpio_show(struct seq_file *s, void *unused)
        /* print heading */
        seq_printf(s, "Pin\t");
        for (bank = 0; bank < gpio_banks; bank++) {
-               seq_printf(s, "PIO%c\t", 'A' + bank);
+               seq_printf(s, "PIO%c\t\t", 'A' + bank);
        };
        seq_printf(s, "\n\n");
 
@@ -445,11 +670,10 @@ static int at91_gpio_show(struct seq_file *s, void *unused)
                        unsigned        mask = pin_to_mask(pin);
 
                        if (__raw_readl(pio + PIO_PSR) & mask)
-                               seq_printf(s, "GPIO:%s", __raw_readl(pio + PIO_PDSR) & mask ? "1" : "0");
+                               gpio_printf(s, pio, mask);
                        else
-                               seq_printf(s, "%s", __raw_readl(pio + PIO_ABSR) & mask ? "B" : "A");
-
-                       seq_printf(s, "\t");
+                               seq_printf(s, "%c\t\t",
+                                               peripheral_function(pio, mask));
                }
 
                seq_printf(s, "\n");
@@ -488,46 +712,152 @@ postcore_initcall(at91_gpio_debugfs_init);
  */
 static struct lock_class_key gpio_lock_class;
 
+#if defined(CONFIG_OF)
+static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq,
+                                                       irq_hw_number_t hw)
+{
+       struct at91_gpio_chip   *at91_gpio = h->host_data;
+
+       irq_set_lockdep_class(virq, &gpio_lock_class);
+
+       /*
+        * Can use the "simple" and not "edge" handler since it's
+        * shorter, and the AIC handles interrupts sanely.
+        */
+       irq_set_chip_and_handler(virq, &gpio_irqchip,
+                                handle_simple_irq);
+       set_irq_flags(virq, IRQF_VALID);
+       irq_set_chip_data(virq, at91_gpio);
+
+       return 0;
+}
+
+static struct irq_domain_ops at91_gpio_ops = {
+       .map    = at91_gpio_irq_map,
+       .xlate  = irq_domain_xlate_twocell,
+};
+
+int __init at91_gpio_of_irq_setup(struct device_node *node,
+                                    struct device_node *parent)
+{
+       struct at91_gpio_chip   *prev = NULL;
+       int                     alias_idx = of_alias_get_id(node, "gpio");
+       struct at91_gpio_chip   *at91_gpio = &gpio_chip[alias_idx];
+
+       /* Setup proper .irq_set_type function */
+       if (has_pio3())
+               gpio_irqchip.irq_set_type = alt_gpio_irq_type;
+       else
+               gpio_irqchip.irq_set_type = gpio_irq_type;
+
+       /* Disable irqs of this PIO controller */
+       __raw_writel(~0, at91_gpio->regbase + PIO_IDR);
+
+       /* Setup irq domain */
+       at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio,
+                                               &at91_gpio_ops, at91_gpio);
+       if (!at91_gpio->domain)
+               panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
+                       at91_gpio->pioc_idx);
+
+       /* Setup chained handler */
+       if (at91_gpio->pioc_idx)
+               prev = &gpio_chip[at91_gpio->pioc_idx - 1];
+
+       /* The toplevel handler handles one bank of GPIOs, except
+        * on some SoC it can handles up to three...
+        * We only set up the handler for the first of the list.
+        */
+       if (prev && prev->next == at91_gpio)
+               return 0;
+
+       at91_gpio->pioc_virq = irq_create_mapping(irq_find_host(parent),
+                                                       at91_gpio->pioc_hwirq);
+       irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio);
+       irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler);
+
+       return 0;
+}
+#else
+int __init at91_gpio_of_irq_setup(struct device_node *node,
+                                    struct device_node *parent)
+{
+       return -EINVAL;
+}
+#endif
+
+/*
+ * irqdomain initialization: pile up irqdomains on top of AIC range
+ */
+static void __init at91_gpio_irqdomain(struct at91_gpio_chip *at91_gpio)
+{
+       int irq_base;
+
+       irq_base = irq_alloc_descs(-1, 0, at91_gpio->chip.ngpio, 0);
+       if (irq_base < 0)
+               panic("at91_gpio.%d: error %d: couldn't allocate IRQ numbers.\n",
+                       at91_gpio->pioc_idx, irq_base);
+       at91_gpio->domain = irq_domain_add_legacy(NULL, at91_gpio->chip.ngpio,
+                                                 irq_base, 0,
+                                                 &irq_domain_simple_ops, NULL);
+       if (!at91_gpio->domain)
+               panic("at91_gpio.%d: couldn't allocate irq domain.\n",
+                       at91_gpio->pioc_idx);
+}
+
 /*
  * Called from the processor-specific init to enable GPIO interrupt support.
  */
 void __init at91_gpio_irq_setup(void)
 {
-       unsigned                pioc, irq = gpio_to_irq(0);
+       unsigned                pioc;
+       int                     gpio_irqnbr = 0;
        struct at91_gpio_chip   *this, *prev;
 
+       /* Setup proper .irq_set_type function */
+       if (has_pio3())
+               gpio_irqchip.irq_set_type = alt_gpio_irq_type;
+       else
+               gpio_irqchip.irq_set_type = gpio_irq_type;
+
        for (pioc = 0, this = gpio_chip, prev = NULL;
                        pioc++ < gpio_banks;
                        prev = this, this++) {
-               unsigned        id = this->id;
-               unsigned        i;
+               int offset;
 
                __raw_writel(~0, this->regbase + PIO_IDR);
 
-               for (i = 0, irq = gpio_to_irq(this->chip.base); i < 32;
-                    i++, irq++) {
-                       irq_set_lockdep_class(irq, &gpio_lock_class);
+               /* setup irq domain for this GPIO controller */
+               at91_gpio_irqdomain(this);
+
+               for (offset = 0; offset < this->chip.ngpio; offset++) {
+                       unsigned int virq = irq_find_mapping(this->domain, offset);
+                       irq_set_lockdep_class(virq, &gpio_lock_class);
 
                        /*
                         * Can use the "simple" and not "edge" handler since it's
                         * shorter, and the AIC handles interrupts sanely.
                         */
-                       irq_set_chip_and_handler(irq, &gpio_irqchip,
+                       irq_set_chip_and_handler(virq, &gpio_irqchip,
                                                 handle_simple_irq);
-                       set_irq_flags(irq, IRQF_VALID);
+                       set_irq_flags(virq, IRQF_VALID);
+                       irq_set_chip_data(virq, this);
+
+                       gpio_irqnbr++;
                }
 
                /* The toplevel handler handles one bank of GPIOs, except
-                * AT91SAM9263_ID_PIOCDE handles three... PIOC is first in
-                * the list, so we only set up that handler.
+                * on some SoC it can handles up to three...
+                * We only set up the handler for the first of the list.
                 */
                if (prev && prev->next == this)
                        continue;
 
-               irq_set_chip_data(id, this);
-               irq_set_chained_handler(id, gpio_irq_handler);
+               this->pioc_virq = irq_create_mapping(NULL, this->pioc_hwirq);
+               irq_set_chip_data(this->pioc_virq, this);
+               irq_set_chained_handler(this->pioc_virq, gpio_irq_handler);
        }
-       pr_info("AT91: %d gpio irqs in %d banks\n", irq - gpio_to_irq(0), gpio_banks);
+       pr_info("AT91: %d gpio irqs in %d banks\n", gpio_irqnbr, gpio_banks);
 }
 
 /* gpiolib support */
@@ -593,48 +923,175 @@ static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
                                           at91_get_gpio_value(pin) ?
                                           "set" : "clear");
                        else
-                               seq_printf(s, "[periph %s]\n",
-                                          __raw_readl(pio + PIO_ABSR) &
-                                          mask ? "B" : "A");
+                               seq_printf(s, "[periph %c]\n",
+                                          peripheral_function(pio, mask));
                }
        }
 }
 
+static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+       struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
+       int virq;
+
+       if (offset < chip->ngpio)
+               virq = irq_create_mapping(at91_gpio->domain, offset);
+       else
+               virq = -ENXIO;
+
+       dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
+                               chip->label, offset + chip->base, virq);
+       return virq;
+}
+
+static int __init at91_gpio_setup_clk(int idx)
+{
+       struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
+
+       /* retreive PIO controller's clock */
+       at91_gpio->clock = clk_get_sys(NULL, at91_gpio->chip.label);
+       if (IS_ERR(at91_gpio->clock)) {
+               pr_err("at91_gpio.%d, failed to get clock, ignoring.\n", idx);
+               goto err;
+       }
+
+       if (clk_prepare(at91_gpio->clock))
+               goto clk_prep_err;
+
+       /* enable PIO controller's clock */
+       if (clk_enable(at91_gpio->clock)) {
+               pr_err("at91_gpio.%d, failed to enable clock, ignoring.\n", idx);
+               goto clk_err;
+       }
+
+       return 0;
+
+clk_err:
+       clk_unprepare(at91_gpio->clock);
+clk_prep_err:
+       clk_put(at91_gpio->clock);
+err:
+       return -EINVAL;
+}
+
+#ifdef CONFIG_OF_GPIO
+static void __init of_at91_gpio_init_one(struct device_node *np)
+{
+       int alias_idx;
+       struct at91_gpio_chip *at91_gpio;
+
+       if (!np)
+               return;
+
+       alias_idx = of_alias_get_id(np, "gpio");
+       if (alias_idx >= MAX_GPIO_BANKS) {
+               pr_err("at91_gpio, failed alias idx(%d) > MAX_GPIO_BANKS(%d), ignoring.\n",
+                                               alias_idx, MAX_GPIO_BANKS);
+               return;
+       }
+
+       at91_gpio = &gpio_chip[alias_idx];
+       at91_gpio->chip.base = alias_idx * at91_gpio->chip.ngpio;
+
+       at91_gpio->regbase = of_iomap(np, 0);
+       if (!at91_gpio->regbase) {
+               pr_err("at91_gpio.%d, failed to map registers, ignoring.\n",
+                                                               alias_idx);
+               return;
+       }
+
+       /* Get the interrupts property */
+       if (of_property_read_u32(np, "interrupts", &at91_gpio->pioc_hwirq)) {
+               pr_err("at91_gpio.%d, failed to get interrupts property, ignoring.\n",
+                                                               alias_idx);
+               goto ioremap_err;
+       }
+
+       /* Get capabilities from compatibility property */
+       if (of_device_is_compatible(np, "atmel,at91sam9x5-gpio"))
+               at91_gpio_caps |= AT91_GPIO_CAP_PIO3;
+
+       /* Setup clock */
+       if (at91_gpio_setup_clk(alias_idx))
+               goto ioremap_err;
+
+       at91_gpio->chip.of_node = np;
+       gpio_banks = max(gpio_banks, alias_idx + 1);
+       at91_gpio->pioc_idx = alias_idx;
+       return;
+
+ioremap_err:
+       iounmap(at91_gpio->regbase);
+}
+
+static int __init of_at91_gpio_init(void)
+{
+       struct device_node *np = NULL;
+
+       /*
+        * This isn't ideal, but it gets things hooked up until this
+        * driver is converted into a platform_device
+        */
+       for_each_compatible_node(np, NULL, "atmel,at91rm9200-gpio")
+               of_at91_gpio_init_one(np);
+
+       return gpio_banks > 0 ? 0 : -EINVAL;
+}
+#else
+static int __init of_at91_gpio_init(void)
+{
+       return -EINVAL;
+}
+#endif
+
+static void __init at91_gpio_init_one(int idx, u32 regbase, int pioc_hwirq)
+{
+       struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
+
+       at91_gpio->chip.base = idx * at91_gpio->chip.ngpio;
+       at91_gpio->pioc_hwirq = pioc_hwirq;
+       at91_gpio->pioc_idx = idx;
+
+       at91_gpio->regbase = ioremap(regbase, 512);
+       if (!at91_gpio->regbase) {
+               pr_err("at91_gpio.%d, failed to map registers, ignoring.\n", idx);
+               return;
+       }
+
+       if (at91_gpio_setup_clk(idx))
+               goto ioremap_err;
+
+       gpio_banks = max(gpio_banks, idx + 1);
+       return;
+
+ioremap_err:
+       iounmap(at91_gpio->regbase);
+}
+
 /*
  * Called from the processor-specific init to enable GPIO pin support.
  */
 void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
 {
-       unsigned                i;
+       unsigned i;
        struct at91_gpio_chip *at91_gpio, *last = NULL;
 
        BUG_ON(nr_banks > MAX_GPIO_BANKS);
 
-       gpio_banks = nr_banks;
+       if (of_at91_gpio_init() < 0) {
+               /* No GPIO controller found in device tree */
+               for (i = 0; i < nr_banks; i++)
+                       at91_gpio_init_one(i, data[i].regbase, data[i].id);
+       }
 
-       for (i = 0; i < nr_banks; i++) {
+       for (i = 0; i < gpio_banks; i++) {
                at91_gpio = &gpio_chip[i];
 
-               at91_gpio->id = data[i].id;
-               at91_gpio->chip.base = i * 32;
-
-               at91_gpio->regbase = ioremap(data[i].regbase, 512);
-               if (!at91_gpio->regbase) {
-                       pr_err("at91_gpio.%d, failed to map registers, ignoring.\n", i);
-                       continue;
-               }
-
-               at91_gpio->clock = clk_get_sys(NULL, at91_gpio->chip.label);
-               if (!at91_gpio->clock) {
-                       pr_err("at91_gpio.%d, failed to get clock, ignoring.\n", i);
-                       continue;
-               }
-
-               /* enable PIO controller's clock */
-               clk_enable(at91_gpio->clock);
-
-               /* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */
-               if (last && last->id == at91_gpio->id)
+               /*
+                * GPIO controller are grouped on some SoC:
+                * PIOC, PIOD and PIOE can share the same IRQ line
+                */
+               if (last && last->pioc_hwirq == at91_gpio->pioc_hwirq)
                        last->next = at91_gpio;
                last = at91_gpio;
 
diff --git a/arch/arm/mach-at91/include/mach/at91_matrix.h b/arch/arm/mach-at91/include/mach/at91_matrix.h
new file mode 100644 (file)
index 0000000..02fae9d
--- /dev/null
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Under GPLv2
+ */
+
+#ifndef __MACH_AT91_MATRIX_H__
+#define __MACH_AT91_MATRIX_H__
+
+#ifndef __ASSEMBLY__
+extern void __iomem *at91_matrix_base;
+
+#define at91_matrix_read(field) \
+       __raw_readl(at91_matrix_base + field)
+
+#define at91_matrix_write(field, value) \
+       __raw_writel(value, at91_matrix_base + field);
+
+#else
+.extern at91_matrix_base
+#endif
+
+#endif /* __MACH_AT91_MATRIX_H__ */
index c6a31bf8a5c6973b93ba8856191ca2bf04bde665..732b11c37f1a68f081508be3e6787ebb637a9540 100644 (file)
 #define PIO_PUER       0x64    /* Pull-up Enable Register */
 #define PIO_PUSR       0x68    /* Pull-up Status Register */
 #define PIO_ASR                0x70    /* Peripheral A Select Register */
+#define PIO_ABCDSR1    0x70    /* Peripheral ABCD Select Register 1 [some sam9 only] */
 #define PIO_BSR                0x74    /* Peripheral B Select Register */
+#define PIO_ABCDSR2    0x74    /* Peripheral ABCD Select Register 2 [some sam9 only] */
 #define PIO_ABSR       0x78    /* AB Status Register */
+#define PIO_IFSCDR     0x80    /* Input Filter Slow Clock Disable Register */
+#define PIO_IFSCER     0x84    /* Input Filter Slow Clock Enable Register */
+#define PIO_IFSCSR     0x88    /* Input Filter Slow Clock Status Register */
+#define PIO_SCDR       0x8c    /* Slow Clock Divider Debouncing Register */
+#define                PIO_SCDR_DIV    (0x3fff <<  0)          /* Slow Clock Divider Mask */
+#define PIO_PPDDR      0x90    /* Pad Pull-down Disable Register */
+#define PIO_PPDER      0x94    /* Pad Pull-down Enable Register */
+#define PIO_PPDSR      0x98    /* Pad Pull-down Status Register */
 #define PIO_OWER       0xa0    /* Output Write Enable Register */
 #define PIO_OWDR       0xa4    /* Output Write Disable Register */
 #define PIO_OWSR       0xa8    /* Output Write Status Register */
+#define PIO_AIMER      0xb0    /* Additional Interrupt Modes Enable Register */
+#define PIO_AIMDR      0xb4    /* Additional Interrupt Modes Disable Register */
+#define PIO_AIMMR      0xb8    /* Additional Interrupt Modes Mask Register */
+#define PIO_ESR                0xc0    /* Edge Select Register */
+#define PIO_LSR                0xc4    /* Level Select Register */
+#define PIO_ELSR       0xc8    /* Edge/Level Status Register */
+#define PIO_FELLSR     0xd0    /* Falling Edge/Low Level Select Register */
+#define PIO_REHLSR     0xd4    /* Rising Edge/ High Level Select Register */
+#define PIO_FRLHSR     0xd8    /* Fall/Rise - Low/High Status Register */
+#define PIO_SCHMITT    0x100   /* Schmitt Trigger Register */
+
+#define ABCDSR_PERIPH_A        0x0
+#define ABCDSR_PERIPH_B        0x1
+#define ABCDSR_PERIPH_C        0x2
+#define ABCDSR_PERIPH_D        0x3
 
 #endif
index f9fdbbe0c53a9d506759b541a201671c179fc05b..36604782a78f0e52d4bed0d6af21c787dacf418f 100644 (file)
 #ifndef AT91_PMC_H
 #define AT91_PMC_H
 
-#define        AT91_PMC_SCER           (AT91_PMC + 0x00)       /* System Clock Enable Register */
-#define        AT91_PMC_SCDR           (AT91_PMC + 0x04)       /* System Clock Disable Register */
+#ifndef __ASSEMBLY__
+extern void __iomem *at91_pmc_base;
 
-#define        AT91_PMC_SCSR           (AT91_PMC + 0x08)       /* System Clock Status Register */
+#define at91_pmc_read(field) \
+       __raw_readl(at91_pmc_base + field)
+
+#define at91_pmc_write(field, value) \
+       __raw_writel(value, at91_pmc_base + field)
+#else
+.extern at91_aic_base
+#endif
+
+#define        AT91_PMC_SCER           0x00                    /* System Clock Enable Register */
+#define        AT91_PMC_SCDR           0x04                    /* System Clock Disable Register */
+
+#define        AT91_PMC_SCSR           0x08                    /* System Clock Status Register */
 #define                AT91_PMC_PCK            (1 <<  0)               /* Processor Clock */
 #define                AT91RM9200_PMC_UDP      (1 <<  1)               /* USB Devcice Port Clock [AT91RM9200 only] */
 #define                AT91RM9200_PMC_MCKUDP   (1 <<  2)               /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
 #define                AT91_PMC_HCK0           (1 << 16)               /* AHB Clock (USB host) [AT91SAM9261 only] */
 #define                AT91_PMC_HCK1           (1 << 17)               /* AHB Clock (LCD) [AT91SAM9261 only] */
 
-#define        AT91_PMC_PCER           (AT91_PMC + 0x10)       /* Peripheral Clock Enable Register */
-#define        AT91_PMC_PCDR           (AT91_PMC + 0x14)       /* Peripheral Clock Disable Register */
-#define        AT91_PMC_PCSR           (AT91_PMC + 0x18)       /* Peripheral Clock Status Register */
+#define        AT91_PMC_PCER           0x10                    /* Peripheral Clock Enable Register */
+#define        AT91_PMC_PCDR           0x14                    /* Peripheral Clock Disable Register */
+#define        AT91_PMC_PCSR           0x18                    /* Peripheral Clock Status Register */
 
-#define        AT91_CKGR_UCKR          (AT91_PMC + 0x1C)       /* UTMI Clock Register [some SAM9] */
+#define        AT91_CKGR_UCKR          0x1C                    /* UTMI Clock Register [some SAM9] */
 #define                AT91_PMC_UPLLEN         (1   << 16)             /* UTMI PLL Enable */
 #define                AT91_PMC_UPLLCOUNT      (0xf << 20)             /* UTMI PLL Start-up Time */
 #define                AT91_PMC_BIASEN         (1   << 24)             /* UTMI BIAS Enable */
 #define                AT91_PMC_BIASCOUNT      (0xf << 28)             /* UTMI BIAS Start-up Time */
 
-#define        AT91_CKGR_MOR           (AT91_PMC + 0x20)       /* Main Oscillator Register [not on SAM9RL] */
+#define        AT91_CKGR_MOR           0x20                    /* Main Oscillator Register [not on SAM9RL] */
 #define                AT91_PMC_MOSCEN         (1    <<  0)            /* Main Oscillator Enable */
 #define                AT91_PMC_OSCBYPASS      (1    <<  1)            /* Oscillator Bypass */
 #define                AT91_PMC_MOSCRCEN       (1    <<  3)            /* Main On-Chip RC Oscillator Enable [some SAM9] */
 #define                AT91_PMC_MOSCSEL        (1    << 24)            /* Main Oscillator Selection [some SAM9] */
 #define                AT91_PMC_CFDEN          (1    << 25)            /* Clock Failure Detector Enable [some SAM9] */
 
-#define        AT91_CKGR_MCFR          (AT91_PMC + 0x24)       /* Main Clock Frequency Register */
+#define        AT91_CKGR_MCFR          0x24                    /* Main Clock Frequency Register */
 #define                AT91_PMC_MAINF          (0xffff <<  0)          /* Main Clock Frequency */
 #define                AT91_PMC_MAINRDY        (1      << 16)          /* Main Clock Ready */
 
-#define        AT91_CKGR_PLLAR         (AT91_PMC + 0x28)       /* PLL A Register */
-#define        AT91_CKGR_PLLBR         (AT91_PMC + 0x2c)       /* PLL B Register */
+#define        AT91_CKGR_PLLAR         0x28                    /* PLL A Register */
+#define        AT91_CKGR_PLLBR         0x2c                    /* PLL B Register */
 #define                AT91_PMC_DIV            (0xff  <<  0)           /* Divider */
 #define                AT91_PMC_PLLCOUNT       (0x3f  <<  8)           /* PLL Counter */
 #define                AT91_PMC_OUT            (3     << 14)           /* PLL Clock Frequency Range */
@@ -69,7 +81,7 @@
 #define                        AT91_PMC_USBDIV_4           &nbs