Merge branch 'sh/sdio' into sh-latest
authorPaul Mundt <lethal@linux-sh.org>
Wed, 12 Jan 2011 05:37:42 +0000 (14:37 +0900)
committerPaul Mundt <lethal@linux-sh.org>
Wed, 12 Jan 2011 05:37:42 +0000 (14:37 +0900)
885 files changed:
Documentation/i2c/muxes/gpio-i2cmux [new file with mode: 0644]
Documentation/kernel-parameters.txt
Documentation/networking/dccp.txt
Documentation/powerpc/booting-without-of.txt
Documentation/powerpc/dts-bindings/4xx/cpm.txt [new file with mode: 0644]
MAINTAINERS
arch/arm/mach-dove/common.c
arch/arm/mach-tegra/include/mach/sdhci.h [new file with mode: 0644]
arch/blackfin/Makefile
arch/blackfin/boot/Makefile
arch/blackfin/configs/BF561-EZKIT-SMP_defconfig [new file with mode: 0644]
arch/blackfin/configs/DNP5370_defconfig [new file with mode: 0644]
arch/blackfin/include/asm/bfin_dma.h [new file with mode: 0644]
arch/blackfin/include/asm/bfin_serial.h [new file with mode: 0644]
arch/blackfin/include/asm/bitops.h
arch/blackfin/include/asm/cache.h
arch/blackfin/include/asm/cacheflush.h
arch/blackfin/include/asm/dma.h
arch/blackfin/include/asm/dpmc.h
arch/blackfin/include/asm/io.h
arch/blackfin/include/asm/irqflags.h
arch/blackfin/include/asm/processor.h
arch/blackfin/include/asm/spinlock.h
arch/blackfin/include/mach-common/pll.h [new file with mode: 0644]
arch/blackfin/include/mach-common/ports-a.h [new file with mode: 0644]
arch/blackfin/include/mach-common/ports-b.h [new file with mode: 0644]
arch/blackfin/include/mach-common/ports-c.h [new file with mode: 0644]
arch/blackfin/include/mach-common/ports-d.h [new file with mode: 0644]
arch/blackfin/include/mach-common/ports-e.h [new file with mode: 0644]
arch/blackfin/include/mach-common/ports-f.h [new file with mode: 0644]
arch/blackfin/include/mach-common/ports-g.h [new file with mode: 0644]
arch/blackfin/include/mach-common/ports-h.h [new file with mode: 0644]
arch/blackfin/include/mach-common/ports-i.h [new file with mode: 0644]
arch/blackfin/include/mach-common/ports-j.h [new file with mode: 0644]
arch/blackfin/kernel/cplb-nompu/cplbinit.c
arch/blackfin/kernel/kgdb.c
arch/blackfin/kernel/kgdb_test.c
arch/blackfin/mach-bf518/boards/ezbrd.c
arch/blackfin/mach-bf518/boards/tcm-bf518.c
arch/blackfin/mach-bf518/dma.c
arch/blackfin/mach-bf518/include/mach/bfin_serial.h [new file with mode: 0644]
arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
arch/blackfin/mach-bf518/include/mach/blackfin.h
arch/blackfin/mach-bf518/include/mach/cdefBF512.h
arch/blackfin/mach-bf518/include/mach/cdefBF514.h
arch/blackfin/mach-bf518/include/mach/cdefBF516.h
arch/blackfin/mach-bf518/include/mach/cdefBF518.h
arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h [deleted file]
arch/blackfin/mach-bf518/include/mach/defBF512.h
arch/blackfin/mach-bf518/include/mach/defBF51x_base.h [deleted file]
arch/blackfin/mach-bf518/include/mach/gpio.h
arch/blackfin/mach-bf518/include/mach/pll.h
arch/blackfin/mach-bf527/boards/ad7160eval.c
arch/blackfin/mach-bf527/boards/cm_bf527.c
arch/blackfin/mach-bf527/boards/ezbrd.c
arch/blackfin/mach-bf527/boards/ezkit.c
arch/blackfin/mach-bf527/boards/tll6527m.c
arch/blackfin/mach-bf527/dma.c
arch/blackfin/mach-bf527/include/mach/bfin_serial.h [new file with mode: 0644]
arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
arch/blackfin/mach-bf527/include/mach/blackfin.h
arch/blackfin/mach-bf527/include/mach/cdefBF522.h
arch/blackfin/mach-bf527/include/mach/cdefBF525.h
arch/blackfin/mach-bf527/include/mach/cdefBF527.h
arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h [deleted file]
arch/blackfin/mach-bf527/include/mach/defBF522.h
arch/blackfin/mach-bf527/include/mach/defBF525.h
arch/blackfin/mach-bf527/include/mach/defBF527.h
arch/blackfin/mach-bf527/include/mach/defBF52x_base.h [deleted file]
arch/blackfin/mach-bf527/include/mach/gpio.h
arch/blackfin/mach-bf527/include/mach/pll.h
arch/blackfin/mach-bf533/boards/H8606.c
arch/blackfin/mach-bf533/boards/blackstamp.c
arch/blackfin/mach-bf533/boards/cm_bf533.c
arch/blackfin/mach-bf533/boards/ezkit.c
arch/blackfin/mach-bf533/boards/ip0x.c
arch/blackfin/mach-bf533/boards/stamp.c
arch/blackfin/mach-bf533/dma.c
arch/blackfin/mach-bf533/include/mach/bfin_serial.h [new file with mode: 0644]
arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
arch/blackfin/mach-bf533/include/mach/blackfin.h
arch/blackfin/mach-bf533/include/mach/cdefBF532.h
arch/blackfin/mach-bf533/include/mach/defBF532.h
arch/blackfin/mach-bf533/include/mach/fio_flag.h [deleted file]
arch/blackfin/mach-bf533/include/mach/gpio.h
arch/blackfin/mach-bf533/include/mach/pll.h
arch/blackfin/mach-bf537/boards/Kconfig
arch/blackfin/mach-bf537/boards/Makefile
arch/blackfin/mach-bf537/boards/cm_bf537e.c
arch/blackfin/mach-bf537/boards/cm_bf537u.c
arch/blackfin/mach-bf537/boards/dnp5370.c [new file with mode: 0644]
arch/blackfin/mach-bf537/boards/minotaur.c
arch/blackfin/mach-bf537/boards/pnav10.c
arch/blackfin/mach-bf537/boards/stamp.c
arch/blackfin/mach-bf537/boards/tcm_bf537.c
arch/blackfin/mach-bf537/dma.c
arch/blackfin/mach-bf537/include/mach/bfin_serial.h [new file with mode: 0644]
arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
arch/blackfin/mach-bf537/include/mach/blackfin.h
arch/blackfin/mach-bf537/include/mach/cdefBF534.h
arch/blackfin/mach-bf537/include/mach/cdefBF537.h
arch/blackfin/mach-bf537/include/mach/defBF534.h
arch/blackfin/mach-bf537/include/mach/defBF537.h
arch/blackfin/mach-bf537/include/mach/gpio.h
arch/blackfin/mach-bf537/include/mach/pll.h
arch/blackfin/mach-bf538/boards/ezkit.c
arch/blackfin/mach-bf538/dma.c
arch/blackfin/mach-bf538/include/mach/bfin_serial.h [new file with mode: 0644]
arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
arch/blackfin/mach-bf538/include/mach/blackfin.h
arch/blackfin/mach-bf538/include/mach/cdefBF538.h
arch/blackfin/mach-bf538/include/mach/cdefBF539.h
arch/blackfin/mach-bf538/include/mach/defBF538.h [new file with mode: 0644]
arch/blackfin/mach-bf538/include/mach/defBF539.h
arch/blackfin/mach-bf538/include/mach/gpio.h
arch/blackfin/mach-bf538/include/mach/pll.h
arch/blackfin/mach-bf548/boards/cm_bf548.c
arch/blackfin/mach-bf548/boards/ezkit.c
arch/blackfin/mach-bf548/dma.c
arch/blackfin/mach-bf548/include/mach/bfin_serial.h [new file with mode: 0644]
arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
arch/blackfin/mach-bf548/include/mach/blackfin.h
arch/blackfin/mach-bf548/include/mach/cdefBF542.h
arch/blackfin/mach-bf548/include/mach/cdefBF544.h
arch/blackfin/mach-bf548/include/mach/cdefBF547.h
arch/blackfin/mach-bf548/include/mach/cdefBF548.h
arch/blackfin/mach-bf548/include/mach/cdefBF549.h
arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
arch/blackfin/mach-bf548/include/mach/defBF542.h
arch/blackfin/mach-bf548/include/mach/defBF544.h
arch/blackfin/mach-bf548/include/mach/defBF547.h
arch/blackfin/mach-bf548/include/mach/defBF548.h
arch/blackfin/mach-bf548/include/mach/defBF549.h
arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
arch/blackfin/mach-bf548/include/mach/gpio.h
arch/blackfin/mach-bf548/include/mach/irq.h
arch/blackfin/mach-bf548/include/mach/pll.h
arch/blackfin/mach-bf561/atomic.S
arch/blackfin/mach-bf561/boards/acvilon.c
arch/blackfin/mach-bf561/boards/cm_bf561.c
arch/blackfin/mach-bf561/boards/ezkit.c
arch/blackfin/mach-bf561/boards/tepla.c
arch/blackfin/mach-bf561/dma.c
arch/blackfin/mach-bf561/hotplug.c
arch/blackfin/mach-bf561/include/mach/anomaly.h
arch/blackfin/mach-bf561/include/mach/bfin_serial.h [new file with mode: 0644]
arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
arch/blackfin/mach-bf561/include/mach/blackfin.h
arch/blackfin/mach-bf561/include/mach/cdefBF561.h
arch/blackfin/mach-bf561/include/mach/defBF561.h
arch/blackfin/mach-bf561/include/mach/gpio.h
arch/blackfin/mach-bf561/include/mach/mem_map.h
arch/blackfin/mach-bf561/include/mach/pll.h
arch/blackfin/mach-bf561/include/mach/smp.h
arch/blackfin/mach-bf561/smp.c
arch/blackfin/mach-common/entry.S
arch/blackfin/mach-common/ints-priority.c
arch/blackfin/mach-common/pm.c
arch/blackfin/mach-common/smp.c
arch/blackfin/mm/sram-alloc.c
arch/microblaze/Kconfig.debug
arch/microblaze/Makefile
arch/microblaze/configs/mmu_defconfig
arch/microblaze/include/asm/pvr.h
arch/microblaze/kernel/cpu/cpuinfo.c
arch/microblaze/kernel/entry.S
arch/microblaze/kernel/exceptions.c
arch/microblaze/kernel/hw_exception_handler.S
arch/microblaze/kernel/prom.c
arch/microblaze/kernel/vmlinux.lds.S
arch/microblaze/lib/memmove.c
arch/microblaze/lib/muldi3.S [deleted file]
arch/microblaze/lib/muldi3.c [new file with mode: 0644]
arch/powerpc/Kconfig
arch/powerpc/boot/dts/canyonlands.dts
arch/powerpc/boot/dts/kilauea.dts
arch/powerpc/boot/dts/mpc8308_p1m.dts
arch/powerpc/boot/dts/mpc8308rdb.dts
arch/powerpc/configs/40x/kilauea_defconfig
arch/powerpc/configs/44x/canyonlands_defconfig
arch/powerpc/include/asm/bitops.h
arch/powerpc/include/asm/cputable.h
arch/powerpc/include/asm/cputhreads.h
arch/powerpc/include/asm/device.h
arch/powerpc/include/asm/firmware.h
arch/powerpc/include/asm/hvcall.h
arch/powerpc/include/asm/lppaca.h
arch/powerpc/include/asm/machdep.h
arch/powerpc/include/asm/mmzone.h
arch/powerpc/include/asm/nvram.h
arch/powerpc/include/asm/ppc-opcode.h
arch/powerpc/include/asm/processor.h
arch/powerpc/include/asm/topology.h
arch/powerpc/include/asm/vdso_datapage.h
arch/powerpc/kernel/Makefile
arch/powerpc/kernel/asm-offsets.c
arch/powerpc/kernel/cputable.c
arch/powerpc/kernel/crash_dump.c
arch/powerpc/kernel/dma-iommu.c
arch/powerpc/kernel/entry_32.S
arch/powerpc/kernel/exceptions-64s.S
arch/powerpc/kernel/fpu.S
arch/powerpc/kernel/head_40x.S
arch/powerpc/kernel/head_44x.S
arch/powerpc/kernel/head_64.S
arch/powerpc/kernel/head_8xx.S
arch/powerpc/kernel/head_fsl_booke.S
arch/powerpc/kernel/iommu.c
arch/powerpc/kernel/misc.S
arch/powerpc/kernel/misc_32.S
arch/powerpc/kernel/misc_64.S
arch/powerpc/kernel/nvram_64.c
arch/powerpc/kernel/pci_64.c
arch/powerpc/kernel/ppc_ksyms.c
arch/powerpc/kernel/ppc_save_regs.S
arch/powerpc/kernel/ptrace.c
arch/powerpc/kernel/ptrace32.c
arch/powerpc/kernel/rtas.c
arch/powerpc/kernel/setup_64.c
arch/powerpc/kernel/smp.c
arch/powerpc/kernel/time.c
arch/powerpc/kernel/vector.S
arch/powerpc/kernel/vio.c
arch/powerpc/lib/Makefile
arch/powerpc/lib/hweight_64.S [new file with mode: 0644]
arch/powerpc/mm/hash_utils_64.c
arch/powerpc/mm/mmu_context_nohash.c
arch/powerpc/mm/numa.c
arch/powerpc/mm/pgtable_32.c
arch/powerpc/mm/pgtable_64.c
arch/powerpc/platforms/44x/Makefile
arch/powerpc/platforms/Kconfig
arch/powerpc/platforms/cell/beat_iommu.c
arch/powerpc/platforms/cell/spufs/lscsa_alloc.c
arch/powerpc/platforms/chrp/time.c
arch/powerpc/platforms/iseries/mf.c
arch/powerpc/platforms/pasemi/iommu.c
arch/powerpc/platforms/powermac/setup.c
arch/powerpc/platforms/pseries/Kconfig
arch/powerpc/platforms/pseries/Makefile
arch/powerpc/platforms/pseries/firmware.c
arch/powerpc/platforms/pseries/hvCall.S
arch/powerpc/platforms/pseries/iommu.c
arch/powerpc/platforms/pseries/lpar.c
arch/powerpc/platforms/pseries/nvram.c
arch/powerpc/platforms/pseries/pseries_energy.c [new file with mode: 0644]
arch/powerpc/sysdev/Makefile
arch/powerpc/sysdev/dart_iommu.c
arch/powerpc/sysdev/mpc8xxx_gpio.c
arch/powerpc/sysdev/ppc4xx_cpm.c [new file with mode: 0644]
arch/powerpc/sysdev/tsi108_dev.c
arch/sh/boards/mach-ap325rxa/setup.c
arch/sh/boards/mach-ecovec24/setup.c
arch/sh/boards/mach-kfr2r09/setup.c
arch/sh/boards/mach-migor/setup.c
arch/sh/boards/mach-se/7724/setup.c
arch/sh/kernel/cpu/sh4a/setup-sh7343.c
arch/sh/kernel/cpu/sh4a/setup-sh7366.c
arch/sh/kernel/cpu/sh4a/setup-sh7722.c
arch/sh/kernel/cpu/sh4a/setup-sh7723.c
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
arch/sparc/kernel/cpu.c
arch/sparc/kernel/pcr.c
arch/x86/include/asm/acpi.h
arch/x86/include/asm/amd_nb.h
arch/x86/include/asm/fixmap.h
arch/x86/include/asm/gpio.h
arch/x86/include/asm/kdebug.h
arch/x86/include/asm/mach_traps.h
arch/x86/include/asm/nmi.h
arch/x86/include/asm/numa_64.h
arch/x86/include/asm/perf_event_p4.h
arch/x86/kernel/amd_nb.c
arch/x86/kernel/aperture_64.c
arch/x86/kernel/apic/apic.c
arch/x86/kernel/apic/hw_nmi.c
arch/x86/kernel/apic/x2apic_uv_x.c
arch/x86/kernel/cpu/mcheck/mce-inject.c
arch/x86/kernel/cpu/perf_event.c
arch/x86/kernel/cpu/perf_event_p4.c
arch/x86/kernel/dumpstack.c
arch/x86/kernel/entry_64.S
arch/x86/kernel/kgdb.c
arch/x86/kernel/reboot.c
arch/x86/kernel/smpboot.c
arch/x86/kernel/traps.c
arch/x86/kernel/tsc.c
arch/x86/mm/amdtopology_64.c
arch/x86/mm/numa_64.c
arch/x86/mm/srat_64.c
arch/x86/oprofile/nmi_int.c
arch/x86/oprofile/nmi_timer_int.c
arch/x86/pci/amd_bus.c
drivers/atm/ambassador.c
drivers/char/agp/agp.h
drivers/char/agp/compat_ioctl.c
drivers/char/agp/compat_ioctl.h
drivers/char/agp/frontend.c
drivers/char/agp/generic.c
drivers/char/agp/intel-agp.c
drivers/char/agp/intel-agp.h
drivers/char/agp/intel-gtt.c
drivers/char/hvc_vio.c
drivers/char/ipmi/ipmi_watchdog.c
drivers/dma/Kconfig
drivers/dma/mpc512x_dma.c
drivers/gpu/drm/drm_agpsupport.c
drivers/gpu/drm/drm_crtc_helper.c
drivers/gpu/drm/drm_fb_helper.c
drivers/gpu/drm/drm_fops.c
drivers/gpu/drm/drm_irq.c
drivers/gpu/drm/drm_mm.c
drivers/gpu/drm/drm_stub.c
drivers/gpu/drm/i915/Makefile
drivers/gpu/drm/i915/i915_debugfs.c
drivers/gpu/drm/i915/i915_dma.c
drivers/gpu/drm/i915/i915_drv.c
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_gem.c
drivers/gpu/drm/i915/i915_gem_debug.c
drivers/gpu/drm/i915/i915_gem_evict.c
drivers/gpu/drm/i915/i915_gem_execbuffer.c [new file with mode: 0644]
drivers/gpu/drm/i915/i915_gem_gtt.c [new file with mode: 0644]
drivers/gpu/drm/i915/i915_gem_tiling.c
drivers/gpu/drm/i915/i915_irq.c
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/i915_suspend.c
drivers/gpu/drm/i915/i915_trace.h
drivers/gpu/drm/i915/intel_display.c
drivers/gpu/drm/i915/intel_dp.c
drivers/gpu/drm/i915/intel_drv.h
drivers/gpu/drm/i915/intel_fb.c
drivers/gpu/drm/i915/intel_i2c.c
drivers/gpu/drm/i915/intel_lvds.c
drivers/gpu/drm/i915/intel_opregion.c
drivers/gpu/drm/i915/intel_overlay.c
drivers/gpu/drm/i915/intel_panel.c
drivers/gpu/drm/i915/intel_ringbuffer.c
drivers/gpu/drm/i915/intel_ringbuffer.h
drivers/gpu/drm/i915/intel_sdvo.c
drivers/gpu/drm/i915/intel_tv.c
drivers/gpu/drm/nouveau/Kconfig
drivers/gpu/drm/nouveau/Makefile
drivers/gpu/drm/nouveau/nouveau_acpi.c
drivers/gpu/drm/nouveau/nouveau_bios.c
drivers/gpu/drm/nouveau/nouveau_bo.c
drivers/gpu/drm/nouveau/nouveau_channel.c
drivers/gpu/drm/nouveau/nouveau_connector.c
drivers/gpu/drm/nouveau/nouveau_display.c
drivers/gpu/drm/nouveau/nouveau_dma.c
drivers/gpu/drm/nouveau/nouveau_dma.h
drivers/gpu/drm/nouveau/nouveau_dp.c
drivers/gpu/drm/nouveau/nouveau_drv.c
drivers/gpu/drm/nouveau/nouveau_drv.h
drivers/gpu/drm/nouveau/nouveau_fbcon.c
drivers/gpu/drm/nouveau/nouveau_fbcon.h
drivers/gpu/drm/nouveau/nouveau_fence.c
drivers/gpu/drm/nouveau/nouveau_gem.c
drivers/gpu/drm/nouveau/nouveau_hw.c
drivers/gpu/drm/nouveau/nouveau_irq.c
drivers/gpu/drm/nouveau/nouveau_mem.c
drivers/gpu/drm/nouveau/nouveau_mm.c [new file with mode: 0644]
drivers/gpu/drm/nouveau/nouveau_mm.h [new file with mode: 0644]
drivers/gpu/drm/nouveau/nouveau_notifier.c
drivers/gpu/drm/nouveau/nouveau_object.c
drivers/gpu/drm/nouveau/nouveau_pm.c
drivers/gpu/drm/nouveau/nouveau_ramht.c
drivers/gpu/drm/nouveau/nouveau_ramht.h
drivers/gpu/drm/nouveau/nouveau_reg.h
drivers/gpu/drm/nouveau/nouveau_sgdma.c
drivers/gpu/drm/nouveau/nouveau_state.c
drivers/gpu/drm/nouveau/nouveau_util.c [new file with mode: 0644]
drivers/gpu/drm/nouveau/nouveau_util.h [new file with mode: 0644]
drivers/gpu/drm/nouveau/nouveau_vm.c [new file with mode: 0644]
drivers/gpu/drm/nouveau/nouveau_vm.h [new file with mode: 0644]
drivers/gpu/drm/nouveau/nv04_crtc.c
drivers/gpu/drm/nouveau/nv04_dac.c
drivers/gpu/drm/nouveau/nv04_display.c
drivers/gpu/drm/nouveau/nv04_fbcon.c
drivers/gpu/drm/nouveau/nv04_fifo.c
drivers/gpu/drm/nouveau/nv04_graph.c
drivers/gpu/drm/nouveau/nv04_instmem.c
drivers/gpu/drm/nouveau/nv10_fb.c
drivers/gpu/drm/nouveau/nv10_fifo.c
drivers/gpu/drm/nouveau/nv10_graph.c
drivers/gpu/drm/nouveau/nv20_graph.c
drivers/gpu/drm/nouveau/nv30_fb.c
drivers/gpu/drm/nouveau/nv40_fb.c
drivers/gpu/drm/nouveau/nv40_fifo.c
drivers/gpu/drm/nouveau/nv40_graph.c
drivers/gpu/drm/nouveau/nv50_crtc.c
drivers/gpu/drm/nouveau/nv50_display.c
drivers/gpu/drm/nouveau/nv50_display.h
drivers/gpu/drm/nouveau/nv50_evo.c [new file with mode: 0644]
drivers/gpu/drm/nouveau/nv50_evo.h
drivers/gpu/drm/nouveau/nv50_fb.c
drivers/gpu/drm/nouveau/nv50_fbcon.c
drivers/gpu/drm/nouveau/nv50_fifo.c
drivers/gpu/drm/nouveau/nv50_gpio.c
drivers/gpu/drm/nouveau/nv50_graph.c
drivers/gpu/drm/nouveau/nv50_instmem.c
drivers/gpu/drm/nouveau/nv50_vm.c [new file with mode: 0644]
drivers/gpu/drm/nouveau/nv50_vram.c [new file with mode: 0644]
drivers/gpu/drm/nouveau/nv84_crypt.c [new file with mode: 0644]
drivers/gpu/drm/nouveau/nvc0_fbcon.c [new file with mode: 0644]
drivers/gpu/drm/nouveau/nvc0_fifo.c
drivers/gpu/drm/nouveau/nvc0_graph.c
drivers/gpu/drm/nouveau/nvc0_graph.h [new file with mode: 0644]
drivers/gpu/drm/nouveau/nvc0_grctx.c [new file with mode: 0644]
drivers/gpu/drm/nouveau/nvc0_instmem.c
drivers/gpu/drm/nouveau/nvc0_vm.c [new file with mode: 0644]
drivers/gpu/drm/nouveau/nvc0_vram.c [new file with mode: 0644]
drivers/gpu/drm/nouveau/nvreg.h
drivers/gpu/drm/radeon/Makefile
drivers/gpu/drm/radeon/ObjectID.h
drivers/gpu/drm/radeon/atom.c
drivers/gpu/drm/radeon/atombios.h
drivers/gpu/drm/radeon/atombios_crtc.c
drivers/gpu/drm/radeon/evergreen.c
drivers/gpu/drm/radeon/evergreen_blit_kms.c
drivers/gpu/drm/radeon/evergreen_reg.h
drivers/gpu/drm/radeon/evergreend.h
drivers/gpu/drm/radeon/ni.c [new file with mode: 0644]
drivers/gpu/drm/radeon/ni_reg.h [new file with mode: 0644]
drivers/gpu/drm/radeon/nid.h [new file with mode: 0644]
drivers/gpu/drm/radeon/r100.c
drivers/gpu/drm/radeon/r100d.h
drivers/gpu/drm/radeon/r300.c
drivers/gpu/drm/radeon/r300d.h
drivers/gpu/drm/radeon/r500_reg.h
drivers/gpu/drm/radeon/r600.c
drivers/gpu/drm/radeon/r600d.h
drivers/gpu/drm/radeon/radeon.h
drivers/gpu/drm/radeon/radeon_asic.c
drivers/gpu/drm/radeon/radeon_asic.h
drivers/gpu/drm/radeon/radeon_atombios.c
drivers/gpu/drm/radeon/radeon_bios.c
drivers/gpu/drm/radeon/radeon_combios.c
drivers/gpu/drm/radeon/radeon_connectors.c
drivers/gpu/drm/radeon/radeon_cs.c
drivers/gpu/drm/radeon/radeon_device.c
drivers/gpu/drm/radeon/radeon_display.c
drivers/gpu/drm/radeon/radeon_drv.c
drivers/gpu/drm/radeon/radeon_encoders.c
drivers/gpu/drm/radeon/radeon_family.h
drivers/gpu/drm/radeon/radeon_fb.c
drivers/gpu/drm/radeon/radeon_fence.c
drivers/gpu/drm/radeon/radeon_irq_kms.c
drivers/gpu/drm/radeon/radeon_kms.c
drivers/gpu/drm/radeon/radeon_mode.h
drivers/gpu/drm/radeon/radeon_object.c
drivers/gpu/drm/radeon/radeon_object.h
drivers/gpu/drm/radeon/radeon_pm.c
drivers/gpu/drm/radeon/radeon_reg.h
drivers/gpu/drm/radeon/radeon_trace.h [new file with mode: 0644]
drivers/gpu/drm/radeon/radeon_trace_points.c [new file with mode: 0644]
drivers/gpu/drm/radeon/reg_srcs/rv515
drivers/gpu/drm/radeon/rs600.c
drivers/gpu/drm/radeon/rv770.c
drivers/gpu/drm/radeon/rv770d.h
drivers/gpu/drm/ttm/ttm_bo.c
drivers/gpu/drm/ttm/ttm_bo_util.c
drivers/gpu/drm/ttm/ttm_bo_vm.c
drivers/gpu/drm/ttm/ttm_execbuf_util.c
drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
drivers/gpu/vga/vga_switcheroo.c
drivers/i2c/algos/i2c-algo-bit.c
drivers/i2c/busses/i2c-i801.c
drivers/i2c/busses/i2c-nforce2.c
drivers/i2c/i2c-core.c
drivers/i2c/muxes/Kconfig
drivers/i2c/muxes/Makefile
drivers/i2c/muxes/gpio-i2cmux.c [new file with mode: 0644]
drivers/infiniband/hw/cxgb3/cxio_hal.c
drivers/infiniband/hw/cxgb3/iwch_provider.h
drivers/infiniband/hw/cxgb3/iwch_qp.c
drivers/infiniband/hw/cxgb4/iw_cxgb4.h
drivers/infiniband/hw/cxgb4/qp.c
drivers/infiniband/hw/ipath/ipath_driver.c
drivers/infiniband/hw/mlx4/cq.c
drivers/infiniband/hw/mlx4/mad.c
drivers/infiniband/hw/mthca/mthca_mad.c
drivers/infiniband/hw/nes/nes_nic.c
drivers/infiniband/hw/qib/qib.h
drivers/infiniband/hw/qib/qib_cq.c
drivers/infiniband/hw/qib/qib_driver.c
drivers/infiniband/hw/qib/qib_file_ops.c
drivers/infiniband/hw/qib/qib_iba6120.c
drivers/infiniband/hw/qib/qib_iba7220.c
drivers/infiniband/hw/qib/qib_iba7322.c
drivers/infiniband/hw/qib/qib_init.c
drivers/infiniband/hw/qib/qib_intr.c
drivers/infiniband/hw/qib/qib_keys.c
drivers/infiniband/hw/qib/qib_mad.c
drivers/infiniband/hw/qib/qib_mr.c
drivers/infiniband/hw/qib/qib_qp.c
drivers/infiniband/hw/qib/qib_rc.c
drivers/infiniband/hw/qib/qib_ud.c
drivers/infiniband/hw/qib/qib_user_sdma.c
drivers/infiniband/hw/qib/qib_verbs.h
drivers/infiniband/ulp/ipoib/Kconfig
drivers/infiniband/ulp/ipoib/ipoib.h
drivers/infiniband/ulp/ipoib/ipoib_cm.c
drivers/infiniband/ulp/ipoib/ipoib_ethtool.c
drivers/infiniband/ulp/ipoib/ipoib_ib.c
drivers/infiniband/ulp/ipoib/ipoib_main.c
drivers/infiniband/ulp/srp/ib_srp.c
drivers/infiniband/ulp/srp/ib_srp.h
drivers/macintosh/macio_asic.c
drivers/macintosh/therm_pm72.c
drivers/mfd/sh_mobile_sdhi.c
drivers/mmc/card/Kconfig
drivers/mmc/core/Kconfig
drivers/mmc/core/bus.c
drivers/mmc/core/core.c
drivers/mmc/core/core.h
drivers/mmc/core/debugfs.c
drivers/mmc/core/host.c
drivers/mmc/core/host.h
drivers/mmc/core/mmc.c
drivers/mmc/core/mmc_ops.c
drivers/mmc/core/mmc_ops.h
drivers/mmc/core/sd.c
drivers/mmc/core/sdio.c
drivers/mmc/core/sdio_bus.c
drivers/mmc/host/Kconfig
drivers/mmc/host/Makefile
drivers/mmc/host/davinci_mmc.c
drivers/mmc/host/dw_mmc.c [new file with mode: 0644]
drivers/mmc/host/dw_mmc.h [new file with mode: 0644]
drivers/mmc/host/mxcmmc.c
drivers/mmc/host/sdhci-dove.c [new file with mode: 0644]
drivers/mmc/host/sdhci-pci.c
drivers/mmc/host/sdhci-pltfm.c
drivers/mmc/host/sdhci-pltfm.h
drivers/mmc/host/sdhci-s3c.c
drivers/mmc/host/sdhci-tegra.c [new file with mode: 0644]
drivers/mmc/host/sdhci.c
drivers/mmc/host/sdhci.h
drivers/mmc/host/tmio_mmc.c
drivers/mmc/host/tmio_mmc.h [deleted file]
drivers/net/Kconfig
drivers/net/bfin_mac.c
drivers/net/bfin_mac.h
drivers/net/bnx2x/bnx2x.h
drivers/net/bnx2x/bnx2x_dump.h
drivers/net/bnx2x/bnx2x_ethtool.c
drivers/net/bnx2x/bnx2x_init.h
drivers/net/bnx2x/bnx2x_main.c
drivers/net/bnx2x/bnx2x_reg.h
drivers/net/bnx2x/bnx2x_stats.c
drivers/net/cxgb4vf/cxgb4vf_main.c
drivers/net/cxgb4vf/t4vf_hw.c
drivers/net/e1000/e1000_hw.c
drivers/net/e1000/e1000_hw.h
drivers/net/e1000/e1000_main.c
drivers/net/e1000/e1000_osdep.h
drivers/net/e1000e/82571.c
drivers/net/e1000e/e1000.h
drivers/net/e1000e/es2lan.c
drivers/net/e1000e/ethtool.c
drivers/net/e1000e/hw.h
drivers/net/e1000e/ich8lan.c
drivers/net/e1000e/lib.c
drivers/net/e1000e/netdev.c
drivers/net/e1000e/phy.c
drivers/net/ehea/ehea.h
drivers/net/ehea/ehea_main.c
drivers/net/fec.c
drivers/net/fec.h
drivers/net/forcedeth.c
drivers/net/hamradio/yam.c
drivers/net/irda/bfin_sir.h
drivers/net/ixgbe/ixgbe.h
drivers/net/ixgbe/ixgbe_82599.c
drivers/net/ixgbe/ixgbe_ethtool.c
drivers/net/ixgbe/ixgbe_main.c
drivers/net/ixgbe/ixgbe_type.h
drivers/net/mlx4/alloc.c
drivers/net/mlx4/en_netdev.c
drivers/net/mlx4/fw.c
drivers/net/pcmcia/pcnet_cs.c
drivers/net/ppp_async.c
drivers/net/ppp_deflate.c
drivers/net/ppp_generic.c
drivers/net/ppp_mppe.c
drivers/net/ppp_synctty.c
drivers/net/qlcnic/qlcnic.h
drivers/net/qlcnic/qlcnic_ethtool.c
drivers/net/qlcnic/qlcnic_init.c
drivers/net/qlcnic/qlcnic_main.c
drivers/net/r8169.c
drivers/net/sky2.c
drivers/net/sky2.h
drivers/net/xen-netfront.c
drivers/ps3/Makefile
drivers/rtc/class.c
drivers/rtc/interface.c
drivers/rtc/rtc-cmos.c
drivers/rtc/rtc-dev.c
drivers/rtc/rtc-ds1307.c
drivers/rtc/rtc-lib.c
drivers/serial/Kconfig
drivers/serial/bfin_5xx.c
drivers/watchdog/hpwdt.c
fs/9p/Kconfig
fs/9p/Makefile
fs/9p/acl.c
fs/9p/v9fs.h
fs/9p/vfs_inode.c
fs/9p/vfs_inode_dotl.c [new file with mode: 0644]
fs/9p/xattr.c
fs/ext2/dir.c
fs/ext2/namei.c
fs/ext2/super.c
fs/ext2/xattr.c
fs/ext3/balloc.c
fs/ext3/dir.c
fs/ext3/inode.c
fs/ext3/ioctl.c
fs/ext3/namei.c
fs/ext3/resize.c
fs/ext3/super.c
fs/ext3/xattr.c
fs/ext4/balloc.c
fs/ext4/dir.c
fs/ext4/ext4.h
fs/ext4/ext4_extents.h
fs/ext4/ext4_jbd2.h
fs/ext4/extents.c
fs/ext4/file.c
fs/ext4/fsync.c
fs/ext4/ialloc.c
fs/ext4/inode.c
fs/ext4/mballoc.c
fs/ext4/migrate.c
fs/ext4/namei.c
fs/ext4/page-io.c
fs/ext4/resize.c
fs/ext4/super.c
fs/ext4/xattr.c
fs/jbd2/journal.c
fs/jbd2/recovery.c
fs/jbd2/transaction.c
fs/lockd/Makefile
fs/lockd/clnt4xdr.c [new file with mode: 0644]
fs/lockd/clntlock.c
fs/lockd/clntproc.c
fs/lockd/clntxdr.c [new file with mode: 0644]
fs/lockd/host.c
fs/lockd/mon.c
fs/lockd/svc4proc.c
fs/lockd/svclock.c
fs/lockd/svcproc.c
fs/lockd/xdr.c
fs/lockd/xdr4.c
fs/mbcache.c
fs/nfs/callback.c
fs/nfs/callback.h
fs/nfs/callback_proc.c
fs/nfs/callback_xdr.c
fs/nfs/client.c
fs/nfs/delegation.c
fs/nfs/delegation.h
fs/nfs/dir.c
fs/nfs/idmap.c
fs/nfs/inode.c
fs/nfs/internal.h
fs/nfs/mount_clnt.c
fs/nfs/nfs2xdr.c
fs/nfs/nfs3xdr.c
fs/nfs/nfs4_fs.h
fs/nfs/nfs4filelayout.c
fs/nfs/nfs4proc.c
fs/nfs/nfs4renewd.c
fs/nfs/nfs4state.c
fs/nfs/nfs4xdr.c
fs/nfs/pagelist.c
fs/nfs/pnfs.c
fs/nfs/pnfs.h
fs/nfs/proc.c
fs/nfs/super.c
fs/nfs/unlink.c
fs/nfsd/nfs4callback.c
fs/ocfs2/Kconfig
fs/ocfs2/alloc.c
fs/ocfs2/alloc.h
fs/ocfs2/aops.c
fs/ocfs2/cluster/heartbeat.c
fs/ocfs2/cluster/netdebug.c
fs/ocfs2/cluster/tcp.c
fs/ocfs2/cluster/tcp_internal.h
fs/ocfs2/dlm/dlmast.c
fs/ocfs2/dlm/dlmcommon.h
fs/ocfs2/dlm/dlmdebug.c
fs/ocfs2/dlm/dlmdebug.h
fs/ocfs2/dlm/dlmdomain.c
fs/ocfs2/dlm/dlmlock.c
fs/ocfs2/dlm/dlmthread.c
fs/ocfs2/namei.c
fs/ocfs2/ocfs2.h
fs/quota/dquot.c
fs/quota/quota_tree.c
fs/udf/Kconfig
fs/udf/balloc.c
fs/udf/dir.c
fs/udf/file.c
fs/udf/ialloc.c
fs/udf/inode.c
fs/udf/namei.c
fs/udf/partition.c
fs/udf/super.c
fs/udf/symlink.c
fs/udf/udf_i.h
fs/udf/udf_sb.h
fs/udf/udfdecl.h
fs/xfs/linux-2.6/sv.h [deleted file]
fs/xfs/linux-2.6/xfs_aops.c
fs/xfs/linux-2.6/xfs_aops.h
fs/xfs/linux-2.6/xfs_buf.c
fs/xfs/linux-2.6/xfs_buf.h
fs/xfs/linux-2.6/xfs_export.c
fs/xfs/linux-2.6/xfs_linux.h
fs/xfs/linux-2.6/xfs_super.c
fs/xfs/linux-2.6/xfs_sync.c
fs/xfs/linux-2.6/xfs_trace.h
fs/xfs/quota/xfs_dquot.c
fs/xfs/xfs_ag.h
fs/xfs/xfs_alloc.c
fs/xfs/xfs_attr_leaf.c
fs/xfs/xfs_btree.c
fs/xfs/xfs_buf_item.c
fs/xfs/xfs_buf_item.h
fs/xfs/xfs_extfree_item.c
fs/xfs/xfs_extfree_item.h
fs/xfs/xfs_fsops.c
fs/xfs/xfs_iget.c
fs/xfs/xfs_inode.c
fs/xfs/xfs_inode.h
fs/xfs/xfs_inode_item.c
fs/xfs/xfs_iomap.c
fs/xfs/xfs_iomap.h
fs/xfs/xfs_log.c
fs/xfs/xfs_log_cil.c
fs/xfs/xfs_log_priv.h
fs/xfs/xfs_log_recover.c
fs/xfs/xfs_mount.c
fs/xfs/xfs_mount.h
fs/xfs/xfs_trans.c
fs/xfs/xfs_trans.h
fs/xfs/xfs_trans_ail.c
fs/xfs/xfs_trans_extfree.c
fs/xfs/xfs_trans_priv.h
fs/xfs/xfs_vnodeops.c
include/asm-generic/io.h
include/drm/drmP.h
include/drm/drm_crtc.h
include/drm/drm_fb_helper.h
include/drm/drm_mm.h
include/drm/drm_pciids.h
include/drm/i915_drm.h
include/drm/intel-gtt.h
include/drm/nouveau_drm.h
include/drm/radeon_drm.h
include/drm/ttm/ttm_bo_api.h
include/drm/ttm/ttm_bo_driver.h
include/drm/ttm/ttm_execbuf_util.h
include/linux/agp_backend.h
include/linux/bfin_mac.h
include/linux/dynamic_debug.h
include/linux/etherdevice.h
include/linux/ext3_fs.h
include/linux/fec.h
include/linux/gpio-i2cmux.h [new file with mode: 0644]
include/linux/i2c.h
include/linux/if_bridge.h
include/linux/intel-gtt.h [deleted file]
include/linux/jbd2.h
include/linux/kref.h
include/linux/lockd/debug.h
include/linux/lockd/lockd.h
include/linux/mbcache.h
include/linux/mfd/tmio.h
include/linux/mmc/dw_mmc.h [new file with mode: 0644]
include/linux/mmc/host.h
include/linux/mmc/mmc.h
include/linux/mmc/sdhci.h
include/linux/netdevice.h
include/linux/netfilter/x_tables.h
include/linux/nfs3.h
include/linux/nfs4.h
include/linux/nfs_fs_sb.h
include/linux/nfs_xdr.h
include/linux/pci_ids.h
include/linux/quotaops.h
include/linux/rtc.h
include/linux/sunrpc/auth.h
include/linux/sunrpc/bc_xprt.h
include/linux/sunrpc/clnt.h
include/linux/sunrpc/svc.h
include/linux/sunrpc/svc_xprt.h
include/linux/sunrpc/xdr.h
include/linux/tracepoint.h
include/linux/vga_switcheroo.h
include/net/ah.h
include/net/arp.h
include/net/phonet/phonet.h
include/net/sch_generic.h
include/net/sock.h
include/trace/define_trace.h
include/trace/events/skb.h
kernel/Makefile
kernel/exit.c
kernel/perf_event.c
kernel/trace/Makefile
kernel/trace/trace.c
lib/dynamic_debug.c
lib/kref.c
net/9p/protocol.c
net/caif/caif_socket.c
net/caif/chnl_net.c
net/core/dev.c
net/core/filter.c
net/core/rtnetlink.c
net/dccp/dccp.h
net/dccp/input.c
net/dccp/sysctl.c
net/ethernet/eth.c
net/ipv4/ah4.c
net/ipv4/arp.c
net/ipv4/inet_connection_sock.c
net/ipv4/inet_diag.c
net/ipv4/netfilter/arp_tables.c
net/ipv4/netfilter/ip_tables.c
net/ipv6/ah6.c
net/ipv6/inet6_connection_sock.c
net/ipv6/netfilter/ip6_tables.c
net/netfilter/nf_conntrack_netlink.c
net/netfilter/x_tables.c
net/netlink/genetlink.c
net/phonet/af_phonet.c
net/sched/act_csum.c
net/sched/act_ipt.c
net/sched/act_mirred.c
net/sched/act_nat.c
net/sched/act_pedit.c
net/sched/act_police.c
net/sched/act_simple.c
net/sched/act_skbedit.c
net/sched/sch_atm.c
net/sched/sch_cbq.c
net/sched/sch_drr.c
net/sched/sch_dsmark.c
net/sched/sch_hfsc.c
net/sched/sch_htb.c
net/sched/sch_ingress.c
net/sched/sch_multiq.c
net/sched/sch_netem.c
net/sched/sch_prio.c
net/sched/sch_red.c
net/sched/sch_sfq.c
net/sched/sch_tbf.c
net/sched/sch_teql.c
net/sunrpc/auth.c
net/sunrpc/auth_gss/auth_gss.c
net/sunrpc/bc_svc.c
net/sunrpc/clnt.c
net/sunrpc/rpc_pipe.c
net/sunrpc/rpcb_clnt.c
net/sunrpc/svc.c
net/sunrpc/svcsock.c
net/sunrpc/xdr.c
net/xfrm/xfrm_user.c
tools/perf/Makefile
tools/perf/builtin-record.c
tools/perf/builtin-sched.c
tools/perf/builtin-stat.c
tools/perf/builtin-test.c
tools/perf/builtin-top.c
tools/perf/util/evsel.c
tools/perf/util/evsel.h
tools/perf/util/parse-events.c
tools/perf/util/session.c

diff --git a/Documentation/i2c/muxes/gpio-i2cmux b/Documentation/i2c/muxes/gpio-i2cmux
new file mode 100644 (file)
index 0000000..811cd78
--- /dev/null
@@ -0,0 +1,65 @@
+Kernel driver gpio-i2cmux
+
+Author: Peter Korsgaard <peter.korsgaard@barco.com>
+
+Description
+-----------
+
+gpio-i2cmux is an i2c mux driver providing access to I2C bus segments
+from a master I2C bus and a hardware MUX controlled through GPIO pins.
+
+E.G.:
+
+  ----------              ----------  Bus segment 1   - - - - -
+ |          | SCL/SDA    |          |-------------- |           |
+ |          |------------|          |
+ |          |            |          | Bus segment 2 |           |
+ |  Linux   | GPIO 1..N  |   MUX    |---------------   Devices
+ |          |------------|          |               |           |
+ |          |            |          | Bus segment M
+ |          |            |          |---------------|           |
+  ----------              ----------                  - - - - -
+
+SCL/SDA of the master I2C bus is multiplexed to bus segment 1..M
+according to the settings of the GPIO pins 1..N.
+
+Usage
+-----
+
+gpio-i2cmux uses the platform bus, so you need to provide a struct
+platform_device with the platform_data pointing to a struct
+gpio_i2cmux_platform_data with the I2C adapter number of the master
+bus, the number of bus segments to create and the GPIO pins used
+to control it. See include/linux/gpio-i2cmux.h for details.
+
+E.G. something like this for a MUX providing 4 bus segments
+controlled through 3 GPIO pins:
+
+#include <linux/gpio-i2cmux.h>
+#include <linux/platform_device.h>
+
+static const unsigned myboard_gpiomux_gpios[] = {
+       AT91_PIN_PC26, AT91_PIN_PC25, AT91_PIN_PC24
+};
+
+static const unsigned myboard_gpiomux_values[] = {
+       0, 1, 2, 3
+};
+
+static struct gpio_i2cmux_platform_data myboard_i2cmux_data = {
+       .parent         = 1,
+       .base_nr        = 2, /* optional */
+       .values         = myboard_gpiomux_values,
+       .n_values       = ARRAY_SIZE(myboard_gpiomux_values),
+       .gpios          = myboard_gpiomux_gpios,
+       .n_gpios        = ARRAY_SIZE(myboard_gpiomux_gpios),
+       .idle           = 4, /* optional */
+};
+
+static struct platform_device myboard_i2cmux = {
+       .name           = "gpio-i2cmux",
+       .id             = 0,
+       .dev            = {
+               .platform_data  = &myboard_i2cmux_data,
+       },
+};
index f3dc951e949f04255d90f35b5da4b78c7d015a67..ed3708f8d0dbae4ec5ad73bd3056aeda1c06b73d 100644 (file)
@@ -403,6 +403,10 @@ and is between 256 and 4096 characters. It is defined in the file
        bttv.pll=       See Documentation/video4linux/bttv/Insmod-options
        bttv.tuner=     and Documentation/video4linux/bttv/CARDLIST
 
+       bulk_remove=off [PPC]  This parameter disables the use of the pSeries
+                       firmware feature for flushing multiple hpte entries
+                       at a time.
+
        c101=           [NET] Moxa C101 synchronous serial card
 
        cachesize=      [BUGS=X86-32] Override level 2 CPU cache size detection.
@@ -1490,6 +1494,10 @@ and is between 256 and 4096 characters. It is defined in the file
        mtdparts=       [MTD]
                        See drivers/mtd/cmdlinepart.c.
 
+       multitce=off    [PPC]  This parameter disables the use of the pSeries
+                       firmware feature for updating multiple TCE entries
+                       at a time.
+
        onenand.bdry=   [HW,MTD] Flex-OneNAND Boundary Configuration
 
                        Format: [die0_boundary][,die0_lock][,die1_boundary][,die1_lock]
index b395ca6a49f296e7b1ddda4e6a580f8691b22532..811872b45beee140a7d1a561b9cee9eadf211b48 100644 (file)
@@ -167,6 +167,7 @@ rx_ccid = 2
 seq_window = 100
        The initial sequence window (sec. 7.5.2) of the sender. This influences
        the local ackno validity and the remote seqno validity windows (7.5.1).
+       Values in the range Wmin = 32 (RFC 4340, 7.5.2) up to 2^32-1 can be set.
 
 tx_qlen = 5
        The size of the transmit buffer in packets. A value of 0 corresponds
index 302db5da49b37812eb19bf79ea0e2952e5f3a21f..3272ed59dec7d5e05f82054324ffa0ea335dc430 100644 (file)
@@ -131,7 +131,7 @@ order to avoid the degeneration that had become the ppc32 kernel entry
 point and the way a new platform should be added to the kernel. The
 legacy iSeries platform breaks those rules as it predates this scheme,
 but no new board support will be accepted in the main tree that
-doesn't follows them properly.  In addition, since the advent of the
+doesn't follow them properly.  In addition, since the advent of the
 arch/powerpc merged architecture for ppc32 and ppc64, new 32-bit
 platforms and 32-bit platforms which move into arch/powerpc will be
 required to use these rules as well.
@@ -1025,7 +1025,7 @@ dtc source code can be found at
 
 WARNING: This version is still in early development stage; the
 resulting device-tree "blobs" have not yet been validated with the
-kernel. The current generated bloc lacks a useful reserve map (it will
+kernel. The current generated block lacks a useful reserve map (it will
 be fixed to generate an empty one, it's up to the bootloader to fill
 it up) among others. The error handling needs work, bugs are lurking,
 etc...
diff --git a/Documentation/powerpc/dts-bindings/4xx/cpm.txt b/Documentation/powerpc/dts-bindings/4xx/cpm.txt
new file mode 100644 (file)
index 0000000..ee45980
--- /dev/null
@@ -0,0 +1,52 @@
+PPC4xx Clock Power Management (CPM) node
+
+Required properties:
+       - compatible            : compatible list, currently only "ibm,cpm"
+       - dcr-access-method     : "native"
+       - dcr-reg               : < DCR register range >
+
+Optional properties:
+       - er-offset             : All 4xx SoCs with a CPM controller have
+                                 one of two different order for the CPM
+                                 registers. Some have the CPM registers
+                                 in the following order (ER,FR,SR). The
+                                 others have them in the following order
+                                 (SR,ER,FR). For the second case set
+                                 er-offset = <1>.
+       - unused-units          : specifier consist of one cell. For each
+                                 bit in the cell, the corresponding bit
+                                 in CPM will be set to turn off unused
+                                 devices.
+       - idle-doze             : specifier consist of one cell. For each
+                                 bit in the cell, the corresponding bit
+                                 in CPM will be set to turn off unused
+                                 devices. This is usually just CPM[CPU].
+       - standby               : specifier consist of one cell. For each
+                                 bit in the cell, the corresponding bit
+                                 in CPM will be set on standby and
+                                 restored on resume.
+       - suspend               : specifier consist of one cell. For each
+                                 bit in the cell, the corresponding bit
+                                 in CPM will be set on suspend (mem) and
+                                 restored on resume. Note, for standby
+                                 and suspend the corresponding bits can
+                                 be different or the same. Usually for
+                                 standby only class 2 and 3 units are set.
+                                 However, the interface does not care.
+                                 If they are the same, the additional
+                                 power saving will be seeing if support
+                                 is available to put the DDR in self
+                                 refresh mode and any additional power
+                                 saving techniques for the specific SoC.
+
+Example:
+       CPM0: cpm {
+               compatible = "ibm,cpm";
+               dcr-access-method = "native";
+               dcr-reg = <0x160 0x003>;
+               er-offset = <0>;
+               unused-units = <0x00000100>;
+               idle-doze = <0x02000000>;
+               standby = <0xfeff0000>;
+               suspend = <0xfeff791d>;
+};
index aca102f758ba711f8da2471ae149e929c207fd3c..42f991e5a85d7626d0e0b531aa9c933f7c4282ca 100644 (file)
@@ -285,6 +285,41 @@ L: linux-parisc@vger.kernel.org
 S:     Maintained
 F:     sound/pci/ad1889.*
 
+AD525X ANALOG DEVICES DIGITAL POTENTIOMETERS DRIVER
+M:     Michael Hennerich <michael.hennerich@analog.com>
+L:     device-driver-devel@blackfin.uclinux.org
+W:     http://wiki-analog.com/AD5254
+S:     Supported
+F:     drivers/misc/ad525x_dpot.c
+
+AD5398 CURRENT REGULATOR DRIVER (AD5398/AD5821)
+M:     Michael Hennerich <michael.hennerich@analog.com>
+L:     device-driver-devel@blackfin.uclinux.org
+W:     http://wiki-analog.com/AD5398
+S:     Supported
+F:     drivers/regulator/ad5398.c
+
+AD714X CAPACITANCE TOUCH SENSOR DRIVER (AD7142/3/7/8/7A)
+M:     Michael Hennerich <michael.hennerich@analog.com>
+L:     device-driver-devel@blackfin.uclinux.org
+W:     http://wiki-analog.com/AD7142
+S:     Supported
+F:     drivers/input/misc/ad714x.c
+
+AD7877 TOUCHSCREEN DRIVER
+M:     Michael Hennerich <michael.hennerich@analog.com>
+L:     device-driver-devel@blackfin.uclinux.org
+W:     http://wiki-analog.com/AD7877
+S:     Supported
+F:     drivers/input/touchscreen/ad7877.c
+
+AD7879 TOUCHSCREEN DRIVER (AD7879/AD7889)
+M:     Michael Hennerich <michael.hennerich@analog.com>
+L:     device-driver-devel@blackfin.uclinux.org
+W:     http://wiki-analog.com/AD7879
+S:     Supported
+F:     drivers/input/touchscreen/ad7879.c
+
 ADM1025 HARDWARE MONITOR DRIVER
 M:     Jean Delvare <khali@linux-fr.org>
 L:     lm-sensors@lm-sensors.org
@@ -304,6 +339,32 @@ W: http://linuxwireless.org/
 S:     Orphan
 F:     drivers/net/wireless/adm8211.*
 
+ADP5520 BACKLIGHT DRIVER WITH IO EXPANDER (ADP5520/ADP5501)
+M:     Michael Hennerich <michael.hennerich@analog.com>
+L:     device-driver-devel@blackfin.uclinux.org
+W:     http://wiki-analog.com/ADP5520
+S:     Supported
+F:     drivers/mfd/adp5520.c
+F:     drivers/video/backlight/adp5520_bl.c
+F:     drivers/led/leds-adp5520.c
+F:     drivers/gpio/adp5520-gpio.c
+F:     drivers/input/keyboard/adp5520-keys.c
+
+ADP5588 QWERTY KEYPAD AND IO EXPANDER DRIVER (ADP5588/ADP5587)
+M:     Michael Hennerich <michael.hennerich@analog.com>
+L:     device-driver-devel@blackfin.uclinux.org
+W:     http://wiki-analog.com/ADP5588
+S:     Supported
+F:     drivers/input/keyboard/adp5588-keys.c
+F:     drivers/gpio/adp5588-gpio.c
+
+ADP8860 BACKLIGHT DRIVER (ADP8860/ADP8861/ADP8863)
+M:     Michael Hennerich <michael.hennerich@analog.com>
+L:     device-driver-devel@blackfin.uclinux.org
+W:     http://wiki-analog.com/ADP8860
+S:     Supported
+F:     drivers/video/backlight/adp8860_bl.c
+
 ADT746X FAN DRIVER
 M:     Colin Leroy <colin@colino.net>
 S:     Maintained
@@ -316,6 +377,13 @@ S: Maintained
 F:     Documentation/hwmon/adt7475
 F:     drivers/hwmon/adt7475.c
 
+ADXL34X THREE-AXIS DIGITAL ACCELEROMETER DRIVER (ADXL345/ADXL346)
+M:     Michael Hennerich <michael.hennerich@analog.com>
+L:     device-driver-devel@blackfin.uclinux.org
+W:     http://wiki-analog.com/ADXL345
+S:     Supported
+F:     drivers/input/misc/adxl34x.c
+
 ADVANSYS SCSI DRIVER
 M:     Matthew Wilcox <matthew@wil.cx>
 L:     linux-scsi@vger.kernel.org
@@ -440,17 +508,23 @@ L:        linux-rdma@vger.kernel.org
 S:     Maintained
 F:     drivers/infiniband/hw/amso1100/
 
-ANALOG DEVICES INC ASOC DRIVERS
-L:     uclinux-dist-devel@blackfin.uclinux.org
+ANALOG DEVICES INC ASOC CODEC DRIVERS
+L:     device-driver-devel@blackfin.uclinux.org
 L:     alsa-devel@alsa-project.org (moderated for non-subscribers)
-W:     http://blackfin.uclinux.org/
+W:     http://wiki-analog.com/
 S:     Supported
-F:     sound/soc/blackfin/*
 F:     sound/soc/codecs/ad1*
 F:     sound/soc/codecs/adau*
 F:     sound/soc/codecs/adav*
 F:     sound/soc/codecs/ssm*
 
+ANALOG DEVICES INC ASOC DRIVERS
+L:     uclinux-dist-devel@blackfin.uclinux.org
+L:     alsa-devel@alsa-project.org (moderated for non-subscribers)
+W:     http://blackfin.uclinux.org/
+S:     Supported
+F:     sound/soc/blackfin/*
+
 AOA (Apple Onboard Audio) ALSA DRIVER
 M:     Johannes Berg <johannes@sipsolutions.net>
 L:     linuxppc-dev@lists.ozlabs.org
@@ -1711,7 +1785,8 @@ S:        Maintained
 F:     drivers/usb/atm/cxacru.c
 
 CONFIGFS
-M:     Joel Becker <joel.becker@oracle.com>
+M:     Joel Becker <jlbec@evilplan.org>
+T:     git git://git.kernel.org/pub/scm/linux/kernel/git/jlbec/configfs.git
 S:     Supported
 F:     fs/configfs/
 F:     include/linux/configfs.h
@@ -2618,6 +2693,14 @@ S:       Supported
 F:     drivers/i2c/busses/i2c-gpio.c
 F:     include/linux/i2c-gpio.h
 
+GENERIC GPIO I2C MULTIPLEXER DRIVER
+M:     Peter Korsgaard <peter.korsgaard@barco.com>
+L:     linux-i2c@vger.kernel.org
+S:     Supported
+F:     drivers/i2c/muxes/gpio-i2cmux.c
+F:     include/linux/gpio-i2cmux.h
+F:     Documentation/i2c/muxes/gpio-i2cmux
+
 GENERIC HDLC (WAN) DRIVERS
 M:     Krzysztof Halasa <khc@pm.waw.pl>
 W:     http://www.kernel.org/pub/linux/utils/net/hdlc/
@@ -4467,7 +4550,7 @@ F:        include/linux/oprofile.h
 
 ORACLE CLUSTER FILESYSTEM 2 (OCFS2)
 M:     Mark Fasheh <mfasheh@suse.com>
-M:     Joel Becker <joel.becker@oracle.com>
+M:     Joel Becker <jlbec@evilplan.org>
 L:     ocfs2-devel@oss.oracle.com (moderated for non-subscribers)
 W:     http://oss.oracle.com/projects/ocfs2/
 T:     git git://git.kernel.org/pub/scm/linux/kernel/git/jlbec/ocfs2.git
index f7a12586a1f5eaf9c1b0316b6efc2b914a63fa30..fe627aba6da7e5ffc90b98122b4ef53e540d1220 100644 (file)
@@ -770,7 +770,7 @@ static struct resource dove_sdio0_resources[] = {
 };
 
 static struct platform_device dove_sdio0 = {
-       .name           = "sdhci-mv",
+       .name           = "sdhci-dove",
        .id             = 0,
        .dev            = {
                .dma_mask               = &sdio_dmamask,
@@ -798,7 +798,7 @@ static struct resource dove_sdio1_resources[] = {
 };
 
 static struct platform_device dove_sdio1 = {
-       .name           = "sdhci-mv",
+       .name           = "sdhci-dove",
        .id             = 1,
        .dev            = {
                .dma_mask               = &sdio_dmamask,
diff --git a/arch/arm/mach-tegra/include/mach/sdhci.h b/arch/arm/mach-tegra/include/mach/sdhci.h
new file mode 100644 (file)
index 0000000..3ad086e
--- /dev/null
@@ -0,0 +1,29 @@
+/*
+ * include/asm-arm/arch-tegra/include/mach/sdhci.h
+ *
+ * Copyright (C) 2009 Palm, Inc.
+ * Author: Yvonne Yip <y@palm.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __ASM_ARM_ARCH_TEGRA_SDHCI_H
+#define __ASM_ARM_ARCH_TEGRA_SDHCI_H
+
+#include <linux/mmc/host.h>
+
+struct tegra_sdhci_platform_data {
+       int cd_gpio;
+       int wp_gpio;
+       int power_gpio;
+       int is_8bit;
+};
+
+#endif
index 46738d49b7c8ee9da7933c05fa976c4806188c2a..46f42b2066e5bc674ebdc23a7443f5c20545f33f 100644 (file)
@@ -19,7 +19,7 @@ KBUILD_CFLAGS           += -mlong-calls
 endif
 KBUILD_AFLAGS           += $(call cc-option,-mno-fdpic)
 KBUILD_CFLAGS_MODULE    += -mlong-calls
-KBUILD_LDFLAGS_MODULE   += -m elf32bfin
+LDFLAGS                 += -m elf32bfin
 KALLSYMS         += --symbol-prefix=_
 
 KBUILD_DEFCONFIG := BF537-STAMP_defconfig
@@ -97,8 +97,11 @@ rev-$(CONFIG_BF_REV_0_6)  := 0.6
 rev-$(CONFIG_BF_REV_NONE) := none
 rev-$(CONFIG_BF_REV_ANY)  := any
 
-KBUILD_CFLAGS += -mcpu=$(cpu-y)-$(rev-y)
-KBUILD_AFLAGS += -mcpu=$(cpu-y)-$(rev-y)
+CPU_REV := $(cpu-y)-$(rev-y)
+export CPU_REV
+
+KBUILD_CFLAGS += -mcpu=$(CPU_REV)
+KBUILD_AFLAGS += -mcpu=$(CPU_REV)
 
 # - we utilize the silicon rev from the toolchain, so move it over to the checkflags
 CHECKFLAGS_SILICON = $(shell echo "" | $(CPP) $(KBUILD_CFLAGS) -dD - 2>/dev/null | awk '$$2 == "__SILICON_REVISION__" { print $$3 }')
index 13d2dbd658e31432e1d3a8c35bbfb6c7cbadd4da..0a49279e3428418f9cb1e04ada32e8371620139b 100644 (file)
@@ -17,7 +17,7 @@ UIMAGE_OPTS-$(CONFIG_ROMKERNEL) += -a $(CONFIG_ROM_BASE) -x
 
 quiet_cmd_uimage = UIMAGE  $@
       cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(ARCH) -O linux -T kernel \
-                   -C $(2) -n '$(MACHINE)-$(KERNELRELEASE)' \
+                   -C $(2) -n '$(CPU_REV)-$(KERNELRELEASE)' \
                    -e $(shell $(NM) vmlinux | awk '$$NF == "__start" {print $$1}') \
                    $(UIMAGE_OPTS-y) -d $< $@
 
diff --git a/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig b/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig
new file mode 100644 (file)
index 0000000..4cf4510
--- /dev/null
@@ -0,0 +1,113 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_EMBEDDED=y
+# CONFIG_SYSCTL_SYSCALL is not set
+# CONFIG_ELF_CORE is not set
+# CONFIG_FUTEX is not set
+# CONFIG_SIGNALFD is not set
+# CONFIG_TIMERFD is not set
+# CONFIG_EVENTFD is not set
+# CONFIG_AIO is not set
+CONFIG_SLAB=y
+CONFIG_MMAP_ALLOW_UNINITIALIZED=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_PREEMPT_VOLUNTARY=y
+CONFIG_BF561=y
+CONFIG_SMP=y
+CONFIG_IRQ_TIMER0=10
+CONFIG_CLKIN_HZ=30000000
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
+CONFIG_BFIN_GPTIMERS=m
+CONFIG_C_CDPRIO=y
+CONFIG_BANK_3=0xAAC2
+CONFIG_BINFMT_FLAT=y
+CONFIG_BINFMT_ZFLAT=y
+CONFIG_PM=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+CONFIG_IRDA=m
+CONFIG_IRLAN=m
+CONFIG_IRCOMM=m
+CONFIG_IRDA_CACHE_LAST_LSAP=y
+CONFIG_IRTTY_SIR=m
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_FW_LOADER is not set
+CONFIG_MTD=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=m
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=m
+CONFIG_MTD_CFI_AMDSTD=m
+CONFIG_MTD_RAM=y
+CONFIG_MTD_ROM=m
+CONFIG_MTD_PHYSMAP=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_NETDEVICES=y
+CONFIG_NET_ETHERNET=y
+CONFIG_SMC91X=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+CONFIG_INPUT=m
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=m
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_BFIN_JTAG_COMM=m
+CONFIG_SERIAL_BFIN=y
+CONFIG_SERIAL_BFIN_CONSOLE=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_HW_RANDOM is not set
+CONFIG_SPI=y
+CONFIG_SPI_BFIN=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_BFIN_WDT=y
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_JFFS2_FS=m
+CONFIG_NFS_FS=m
+CONFIG_NFS_V3=y
+CONFIG_SMB_FS=m
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_MMRS=y
+CONFIG_DEBUG_HWERR=y
+CONFIG_EXACT_HWERR=y
+CONFIG_DEBUG_DOUBLEFAULT=y
+CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_CPLB_INFO=y
+CONFIG_CRYPTO=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/DNP5370_defconfig b/arch/blackfin/configs/DNP5370_defconfig
new file mode 100644 (file)
index 0000000..0ebc7d9
--- /dev/null
@@ -0,0 +1,121 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_LOCALVERSION="DNP5370"
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLOB=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_BF537=y
+CONFIG_BF_REV_0_3=y
+CONFIG_DNP5370=y
+CONFIG_IRQ_ERROR=7
+# CONFIG_CYCLES_CLOCKSOURCE is not set
+CONFIG_C_CDPRIO=y
+CONFIG_C_AMBEN_B0_B1_B2=y
+CONFIG_PM=y
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+CONFIG_LLC2=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_DEBUG=y
+CONFIG_MTD_DEBUG_VERBOSE=1
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_NFTL=y
+CONFIG_NFTL_RW=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_UCLINUX=y
+CONFIG_MTD_PLATRAM=y
+CONFIG_MTD_DATAFLASH=y
+CONFIG_MTD_BLOCK2MTD=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_PLATFORM=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+# CONFIG_MISC_DEVICES is not set
+CONFIG_NETDEVICES=y
+CONFIG_DAVICOM_PHY=y
+CONFIG_NET_ETHERNET=y
+CONFIG_BFIN_MAC=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_BFIN_DMA_INTERFACE is not set
+# CONFIG_VT is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_BFIN_JTAG_COMM=y
+CONFIG_BFIN_JTAG_COMM_CONSOLE=y
+CONFIG_SERIAL_BFIN=y
+CONFIG_SERIAL_BFIN_CONSOLE=y
+CONFIG_SERIAL_BFIN_UART0=y
+CONFIG_LEGACY_PTY_COUNT=64
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_BLACKFIN_TWI=y
+CONFIG_SPI=y
+CONFIG_SPI_BFIN=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_SENSORS_LM75=y
+# CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+CONFIG_MMC_SPI=y
+CONFIG_DMADEVICES=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+# CONFIG_DNOTIFY is not set
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=850
+CONFIG_JFFS2_FS=y
+CONFIG_CRAMFS=y
+CONFIG_ROMFS_FS=y
+CONFIG_ROMFS_BACKED_BY_BOTH=y
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEBUG_OBJECTS=y
+CONFIG_DEBUG_LOCK_ALLOC=y
+CONFIG_DEBUG_KOBJECT=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_VM=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DEBUG_LIST=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_PAGE_POISONING=y
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_DOUBLEFAULT=y
+CONFIG_CPLB_INFO=y
+CONFIG_CRC_CCITT=y
diff --git a/arch/blackfin/include/asm/bfin_dma.h b/arch/blackfin/include/asm/bfin_dma.h
new file mode 100644 (file)
index 0000000..d511207
--- /dev/null
@@ -0,0 +1,91 @@
+/*
+ * bfin_dma.h - Blackfin DMA defines/structures/etc...
+ *
+ * Copyright 2004-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __ASM_BFIN_DMA_H__
+#define __ASM_BFIN_DMA_H__
+
+#include <linux/types.h>
+
+/* DMA_CONFIG Masks */
+#define DMAEN                  0x0001  /* DMA Channel Enable */
+#define WNR                            0x0002  /* Channel Direction (W/R*) */
+#define WDSIZE_8               0x0000  /* Transfer Word Size = 8 */
+#define WDSIZE_16              0x0004  /* Transfer Word Size = 16 */
+#define WDSIZE_32              0x0008  /* Transfer Word Size = 32 */
+#define DMA2D                  0x0010  /* DMA Mode (2D/1D*) */
+#define RESTART                        0x0020  /* DMA Buffer Clear */
+#define DI_SEL                 0x0040  /* Data Interrupt Timing Select */
+#define DI_EN                  0x0080  /* Data Interrupt Enable */
+#define NDSIZE_0               0x0000  /* Next Descriptor Size = 0 (Stop/Autobuffer) */
+#define NDSIZE_1               0x0100  /* Next Descriptor Size = 1 */
+#define NDSIZE_2               0x0200  /* Next Descriptor Size = 2 */
+#define NDSIZE_3               0x0300  /* Next Descriptor Size = 3 */
+#define NDSIZE_4               0x0400  /* Next Descriptor Size = 4 */
+#define NDSIZE_5               0x0500  /* Next Descriptor Size = 5 */
+#define NDSIZE_6               0x0600  /* Next Descriptor Size = 6 */
+#define NDSIZE_7               0x0700  /* Next Descriptor Size = 7 */
+#define NDSIZE_8               0x0800  /* Next Descriptor Size = 8 */
+#define NDSIZE_9               0x0900  /* Next Descriptor Size = 9 */
+#define NDSIZE                 0x0f00  /* Next Descriptor Size */
+#define DMAFLOW                        0x7000  /* Flow Control */
+#define DMAFLOW_STOP   0x0000  /* Stop Mode */
+#define DMAFLOW_AUTO   0x1000  /* Autobuffer Mode */
+#define DMAFLOW_ARRAY  0x4000  /* Descriptor Array Mode */
+#define DMAFLOW_SMALL  0x6000  /* Small Model Descriptor List Mode */
+#define DMAFLOW_LARGE  0x7000  /* Large Model Descriptor List Mode */
+
+/* DMA_IRQ_STATUS Masks */
+#define DMA_DONE               0x0001  /* DMA Completion Interrupt Status */
+#define DMA_ERR                        0x0002  /* DMA Error Interrupt Status */
+#define DFETCH                 0x0004  /* DMA Descriptor Fetch Indicator */
+#define DMA_RUN                        0x0008  /* DMA Channel Running Indicator */
+
+/*
+ * All Blackfin system MMRs are padded to 32bits even if the register
+ * itself is only 16bits.  So use a helper macro to streamline this.
+ */
+#define __BFP(m) u16 m; u16 __pad_##m
+
+/*
+ * bfin dma registers layout
+ */
+struct bfin_dma_regs {
+       u32 next_desc_ptr;
+       u32 start_addr;
+       __BFP(config);
+       u32 __pad0;
+       __BFP(x_count);
+       __BFP(x_modify);
+       __BFP(y_count);
+       __BFP(y_modify);
+       u32 curr_desc_ptr;
+       u32 curr_addr;
+       __BFP(irq_status);
+       __BFP(peripheral_map);
+       __BFP(curr_x_count);
+       u32 __pad1;
+       __BFP(curr_y_count);
+       u32 __pad2;
+};
+
+/*
+ * bfin handshake mdma registers layout
+ */
+struct bfin_hmdma_regs {
+       __BFP(control);
+       __BFP(ecinit);
+       __BFP(bcinit);
+       __BFP(ecurgent);
+       __BFP(ecoverflow);
+       __BFP(ecount);
+       __BFP(bcount);
+};
+
+#undef __BFP
+
+#endif
diff --git a/arch/blackfin/include/asm/bfin_serial.h b/arch/blackfin/include/asm/bfin_serial.h
new file mode 100644 (file)
index 0000000..1ff9f14
--- /dev/null
@@ -0,0 +1,275 @@
+/*
+ * bfin_serial.h - Blackfin UART/Serial definitions
+ *
+ * Copyright 2006-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_ASM_SERIAL_H__
+#define __BFIN_ASM_SERIAL_H__
+
+#include <linux/serial_core.h>
+#include <mach/anomaly.h>
+#include <mach/bfin_serial.h>
+
+#if defined(CONFIG_BFIN_UART0_CTSRTS) || \
+    defined(CONFIG_BFIN_UART1_CTSRTS) || \
+    defined(CONFIG_BFIN_UART2_CTSRTS) || \
+    defined(CONFIG_BFIN_UART3_CTSRTS)
+# ifdef BFIN_UART_BF54X_STYLE
+#  define CONFIG_SERIAL_BFIN_HARD_CTSRTS
+# else
+#  define CONFIG_SERIAL_BFIN_CTSRTS
+# endif
+#endif
+
+struct circ_buf;
+struct timer_list;
+struct work_struct;
+
+struct bfin_serial_port {
+       struct uart_port port;
+       unsigned int old_status;
+       int status_irq;
+#ifndef BFIN_UART_BF54X_STYLE
+       unsigned int lsr;
+#endif
+#ifdef CONFIG_SERIAL_BFIN_DMA
+       int tx_done;
+       int tx_count;
+       struct circ_buf rx_dma_buf;
+       struct timer_list rx_dma_timer;
+       int rx_dma_nrows;
+       unsigned int tx_dma_channel;
+       unsigned int rx_dma_channel;
+       struct work_struct tx_dma_workqueue;
+#elif ANOMALY_05000363
+       unsigned int anomaly_threshold;
+#endif
+#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
+       int scts;
+#endif
+#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
+       defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
+       int cts_pin;
+       int rts_pin;
+#endif
+};
+
+/* UART_LCR Masks */
+#define WLS(x)                   (((x)-5) & 0x03)  /* Word Length Select */
+#define STB                      0x04  /* Stop Bits */
+#define PEN                      0x08  /* Parity Enable */
+#define EPS                      0x10  /* Even Parity Select */
+#define STP                      0x20  /* Stick Parity */
+#define SB                       0x40  /* Set Break */
+#define DLAB                     0x80  /* Divisor Latch Access */
+
+/* UART_LSR Masks */
+#define DR                       0x01  /* Data Ready */
+#define OE                       0x02  /* Overrun Error */
+#define PE                       0x04  /* Parity Error */
+#define FE                       0x08  /* Framing Error */
+#define BI                       0x10  /* Break Interrupt */
+#define THRE                     0x20  /* THR Empty */
+#define TEMT                     0x40  /* TSR and UART_THR Empty */
+#define TFI                      0x80  /* Transmission Finished Indicator */
+
+/* UART_IER Masks */
+#define ERBFI                    0x01  /* Enable Receive Buffer Full Interrupt */
+#define ETBEI                    0x02  /* Enable Transmit Buffer Empty Interrupt */
+#define ELSI                     0x04  /* Enable RX Status Interrupt */
+#define EDSSI                    0x08  /* Enable Modem Status Interrupt */
+#define EDTPTI                   0x10  /* Enable DMA Transmit PIRQ Interrupt */
+#define ETFI                     0x20  /* Enable Transmission Finished Interrupt */
+#define ERFCI                    0x40  /* Enable Receive FIFO Count Interrupt */
+
+/* UART_MCR Masks */
+#define XOFF                     0x01  /* Transmitter Off */
+#define MRTS                     0x02  /* Manual Request To Send */
+#define RFIT                     0x04  /* Receive FIFO IRQ Threshold */
+#define RFRT                     0x08  /* Receive FIFO RTS Threshold */
+#define LOOP_ENA                 0x10  /* Loopback Mode Enable */
+#define FCPOL                    0x20  /* Flow Control Pin Polarity */
+#define ARTS                     0x40  /* Automatic Request To Send */
+#define ACTS                     0x80  /* Automatic Clear To Send */
+
+/* UART_MSR Masks */
+#define SCTS                     0x01  /* Sticky CTS */
+#define CTS                      0x10  /* Clear To Send */
+#define RFCS                     0x20  /* Receive FIFO Count Status */
+
+/* UART_GCTL Masks */
+#define UCEN                     0x01  /* Enable UARTx Clocks */
+#define IREN                     0x02  /* Enable IrDA Mode */
+#define TPOLC                    0x04  /* IrDA TX Polarity Change */
+#define RPOLC                    0x08  /* IrDA RX Polarity Change */
+#define FPE                      0x10  /* Force Parity Error On Transmit */
+#define FFE                      0x20  /* Force Framing Error On Transmit */
+
+#ifdef BFIN_UART_BF54X_STYLE
+# define OFFSET_DLL              0x00  /* Divisor Latch (Low-Byte)        */
+# define OFFSET_DLH              0x04  /* Divisor Latch (High-Byte)       */
+# define OFFSET_GCTL             0x08  /* Global Control Register         */
+# define OFFSET_LCR              0x0C  /* Line Control Register           */
+# define OFFSET_MCR              0x10  /* Modem Control Register          */
+# define OFFSET_LSR              0x14  /* Line Status Register            */
+# define OFFSET_MSR              0x18  /* Modem Status Register           */
+# define OFFSET_SCR              0x1C  /* SCR Scratch Register            */
+# define OFFSET_IER_SET          0x20  /* Set Interrupt Enable Register   */
+# define OFFSET_IER_CLEAR        0x24  /* Clear Interrupt Enable Register */
+# define OFFSET_THR              0x28  /* Transmit Holding register       */
+# define OFFSET_RBR              0x2C  /* Receive Buffer register         */
+#else /* BF533 style */
+# define OFFSET_THR              0x00  /* Transmit Holding register         */
+# define OFFSET_RBR              0x00  /* Receive Buffer register           */
+# define OFFSET_DLL              0x00  /* Divisor Latch (Low-Byte)          */
+# define OFFSET_DLH              0x04  /* Divisor Latch (High-Byte)         */
+# define OFFSET_IER              0x04  /* Interrupt Enable Register         */
+# define OFFSET_IIR              0x08  /* Interrupt Identification Register */
+# define OFFSET_LCR              0x0C  /* Line Control Register             */
+# define OFFSET_MCR              0x10  /* Modem Control Register            */
+# define OFFSET_LSR              0x14  /* Line Status Register              */
+# define OFFSET_MSR              0x18  /* Modem Status Register             */
+# define OFFSET_SCR              0x1C  /* SCR Scratch Register              */
+# define OFFSET_GCTL             0x24  /* Global Control Register           */
+/* code should not need IIR, so force build error if they use it */
+# undef OFFSET_IIR
+#endif
+
+/*
+ * All Blackfin system MMRs are padded to 32bits even if the register
+ * itself is only 16bits.  So use a helper macro to streamline this.
+ */
+#define __BFP(m) u16 m; u16 __pad_##m
+struct bfin_uart_regs {
+#ifdef BFIN_UART_BF54X_STYLE
+       __BFP(dll);
+       __BFP(dlh);
+       __BFP(gctl);
+       __BFP(lcr);
+       __BFP(mcr);
+       __BFP(lsr);
+       __BFP(msr);
+       __BFP(scr);
+       __BFP(ier_set);
+       __BFP(ier_clear);
+       __BFP(thr);
+       __BFP(rbr);
+#else
+       union {
+               u16 dll;
+               u16 thr;
+               const u16 rbr;
+       };
+       const u16 __pad0;
+       union {
+               u16 dlh;
+               u16 ier;
+       };
+       const u16 __pad1;
+       const __BFP(iir);
+       __BFP(lcr);
+       __BFP(mcr);
+       __BFP(lsr);
+       __BFP(msr);
+       __BFP(scr);
+       const u32 __pad2;
+       __BFP(gctl);
+#endif
+};
+#undef __BFP
+
+#ifndef port_membase
+# define port_membase(p) (((struct bfin_serial_port *)(p))->port.membase)
+#endif
+
+#define UART_GET_CHAR(p)      bfin_read16(port_membase(p) + OFFSET_RBR)
+#define UART_GET_DLL(p)       bfin_read16(port_membase(p) + OFFSET_DLL)
+#define UART_GET_DLH(p)       bfin_read16(port_membase(p) + OFFSET_DLH)
+#define UART_GET_GCTL(p)      bfin_read16(port_membase(p) + OFFSET_GCTL)
+#define UART_GET_LCR(p)       bfin_read16(port_membase(p) + OFFSET_LCR)
+#define UART_GET_MCR(p)       bfin_read16(port_membase(p) + OFFSET_MCR)
+#define UART_GET_MSR(p)       bfin_read16(port_membase(p) + OFFSET_MSR)
+
+#define UART_PUT_CHAR(p, v)   bfin_write16(port_membase(p) + OFFSET_THR, v)
+#define UART_PUT_DLL(p, v)    bfin_write16(port_membase(p) + OFFSET_DLL, v)
+#define UART_PUT_DLH(p, v)    bfin_write16(port_membase(p) + OFFSET_DLH, v)
+#define UART_PUT_GCTL(p, v)   bfin_write16(port_membase(p) + OFFSET_GCTL, v)
+#define UART_PUT_LCR(p, v)    bfin_write16(port_membase(p) + OFFSET_LCR, v)
+#define UART_PUT_MCR(p, v)    bfin_write16(port_membase(p) + OFFSET_MCR, v)
+
+#ifdef BFIN_UART_BF54X_STYLE
+
+#define UART_CLEAR_IER(p, v)  bfin_write16(port_membase(p) + OFFSET_IER_CLEAR, v)
+#define UART_GET_IER(p)       bfin_read16(port_membase(p) + OFFSET_IER_SET)
+#define UART_SET_IER(p, v)    bfin_write16(port_membase(p) + OFFSET_IER_SET, v)
+
+#define UART_CLEAR_DLAB(p)    /* MMRs not muxed on BF54x */
+#define UART_SET_DLAB(p)      /* MMRs not muxed on BF54x */
+
+#define UART_CLEAR_LSR(p)     bfin_write16(port_membase(p) + OFFSET_LSR, -1)
+#define UART_GET_LSR(p)       bfin_read16(port_membase(p) + OFFSET_LSR)
+#define UART_PUT_LSR(p, v)    bfin_write16(port_membase(p) + OFFSET_LSR, v)
+
+/* This handles hard CTS/RTS */
+#define BFIN_UART_CTSRTS_HARD
+#define UART_CLEAR_SCTS(p)      bfin_write16((port_membase(p) + OFFSET_MSR), SCTS)
+#define UART_GET_CTS(x)         (UART_GET_MSR(x) & CTS)
+#define UART_DISABLE_RTS(x)     UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS))
+#define UART_ENABLE_RTS(x)      UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
+#define UART_ENABLE_INTS(x, v)  UART_SET_IER(x, v)
+#define UART_DISABLE_INTS(x)    UART_CLEAR_IER(x, 0xF)
+
+#else /* BF533 style */
+
+#define UART_CLEAR_IER(p, v)  UART_PUT_IER(p, UART_GET_IER(p) & ~(v))
+#define UART_GET_IER(p)       bfin_read16(port_membase(p) + OFFSET_IER)
+#define UART_PUT_IER(p, v)    bfin_write16(port_membase(p) + OFFSET_IER, v)
+#define UART_SET_IER(p, v)    UART_PUT_IER(p, UART_GET_IER(p) | (v))
+
+#define UART_CLEAR_DLAB(p)    do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0)
+#define UART_SET_DLAB(p)      do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0)
+
+#ifndef put_lsr_cache
+# define put_lsr_cache(p, v) (((struct bfin_serial_port *)(p))->lsr = (v))
+#endif
+#ifndef get_lsr_cache
+# define get_lsr_cache(p)    (((struct bfin_serial_port *)(p))->lsr)
+#endif
+
+/* The hardware clears the LSR bits upon read, so we need to cache
+ * some of the more fun bits in software so they don't get lost
+ * when checking the LSR in other code paths (TX).
+ */
+static inline void UART_CLEAR_LSR(void *p)
+{
+       put_lsr_cache(p, 0);
+       bfin_write16(port_membase(p) + OFFSET_LSR, -1);
+}
+static inline unsigned int UART_GET_LSR(void *p)
+{
+       unsigned int lsr = bfin_read16(port_membase(p) + OFFSET_LSR);
+       put_lsr_cache(p, get_lsr_cache(p) | (lsr & (BI|FE|PE|OE)));
+       return lsr | get_lsr_cache(p);
+}
+static inline void UART_PUT_LSR(void *p, uint16_t val)
+{
+       put_lsr_cache(p, get_lsr_cache(p) & ~val);
+}
+
+/* This handles soft CTS/RTS */
+#define UART_GET_CTS(x)        gpio_get_value((x)->cts_pin)
+#define UART_DISABLE_RTS(x)    gpio_set_value((x)->rts_pin, 1)
+#define UART_ENABLE_RTS(x)     gpio_set_value((x)->rts_pin, 0)
+#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
+#define UART_DISABLE_INTS(x)   UART_PUT_IER(x, 0)
+
+#endif
+
+#ifndef BFIN_UART_TX_FIFO_SIZE
+# define BFIN_UART_TX_FIFO_SIZE 2
+#endif
+
+#endif /* __BFIN_ASM_SERIAL_H__ */
index 3f7ef4d97791514c9d4eab13d17baffc78efb5f3..29f4fd8861748892cb1192860519f0e6355c8e97 100644 (file)
@@ -108,7 +108,9 @@ static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
 #define smp_mb__before_clear_bit()     barrier()
 #define smp_mb__after_clear_bit()      barrier()
 
+#define test_bit __skip_test_bit
 #include <asm-generic/bitops/non-atomic.h>
+#undef test_bit
 
 #endif /* CONFIG_SMP */
 
index bd0641a267f1f144d8332050aab4d607361d513f..568885a2c2862bc12699207515650d5342ddb6fd 100644 (file)
@@ -7,6 +7,8 @@
 #ifndef __ARCH_BLACKFIN_CACHE_H
 #define __ARCH_BLACKFIN_CACHE_H
 
+#include <linux/linkage.h>     /* for asmlinkage */
+
 /*
  * Bytes per L1 cache line
  * Blackfin loads 32 bytes for cache
index 2666ff8ea9522907b7aa80dc3ea63de161f76b98..77135b62818e16794db3d441debbec3c0cfb7254 100644 (file)
@@ -11,6 +11,9 @@
 
 #include <asm/blackfin.h>      /* for SSYNC() */
 #include <asm/sections.h>      /* for _ramend */
+#ifdef CONFIG_SMP
+#include <asm/smp.h>
+#endif
 
 extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address);
 extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address);
index eedf3ca65ba22270e8405b47e914a891463917a0..d9dbc1a5353440bb6dc2e12e8fed21e25d034fb9 100644 (file)
 #include <asm/blackfin.h>
 #include <asm/page.h>
 #include <asm-generic/dma.h>
-
-/* DMA_CONFIG Masks */
-#define DMAEN                  0x0001  /* DMA Channel Enable */
-#define WNR                            0x0002  /* Channel Direction (W/R*) */
-#define WDSIZE_8               0x0000  /* Transfer Word Size = 8 */
-#define WDSIZE_16              0x0004  /* Transfer Word Size = 16 */
-#define WDSIZE_32              0x0008  /* Transfer Word Size = 32 */
-#define DMA2D                  0x0010  /* DMA Mode (2D/1D*) */
-#define RESTART                        0x0020  /* DMA Buffer Clear */
-#define DI_SEL                 0x0040  /* Data Interrupt Timing Select */
-#define DI_EN                  0x0080  /* Data Interrupt Enable */
-#define NDSIZE_0               0x0000  /* Next Descriptor Size = 0 (Stop/Autobuffer) */
-#define NDSIZE_1               0x0100  /* Next Descriptor Size = 1 */
-#define NDSIZE_2               0x0200  /* Next Descriptor Size = 2 */
-#define NDSIZE_3               0x0300  /* Next Descriptor Size = 3 */
-#define NDSIZE_4               0x0400  /* Next Descriptor Size = 4 */
-#define NDSIZE_5               0x0500  /* Next Descriptor Size = 5 */
-#define NDSIZE_6               0x0600  /* Next Descriptor Size = 6 */
-#define NDSIZE_7               0x0700  /* Next Descriptor Size = 7 */
-#define NDSIZE_8               0x0800  /* Next Descriptor Size = 8 */
-#define NDSIZE_9               0x0900  /* Next Descriptor Size = 9 */
-#define NDSIZE                 0x0f00  /* Next Descriptor Size */
-#define DMAFLOW                        0x7000  /* Flow Control */
-#define DMAFLOW_STOP   0x0000  /* Stop Mode */
-#define DMAFLOW_AUTO   0x1000  /* Autobuffer Mode */
-#define DMAFLOW_ARRAY  0x4000  /* Descriptor Array Mode */
-#define DMAFLOW_SMALL  0x6000  /* Small Model Descriptor List Mode */
-#define DMAFLOW_LARGE  0x7000  /* Large Model Descriptor List Mode */
-
-/* DMA_IRQ_STATUS Masks */
-#define DMA_DONE               0x0001  /* DMA Completion Interrupt Status */
-#define DMA_ERR                        0x0002  /* DMA Error Interrupt Status */
-#define DFETCH                 0x0004  /* DMA Descriptor Fetch Indicator */
-#define DMA_RUN                        0x0008  /* DMA Channel Running Indicator */
+#include <asm/bfin_dma.h>
 
 /*-------------------------
  * config reg bits value
@@ -149,7 +116,7 @@ void blackfin_dma_resume(void);
 *      DMA API's
 *******************************************************************************/
 extern struct dma_channel dma_ch[MAX_DMA_CHANNELS];
-extern struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS];
+extern struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS];
 extern int channel2irq(unsigned int channel);
 
 static inline void set_dma_start_addr(unsigned int channel, unsigned long addr)
index efcc3aebeae428aec5f43ca0b1fc9ee8ceee91cf..3047120cfcff4b5ce9a7e8bca467a6df820f4aef 100644 (file)
@@ -9,6 +9,8 @@
 #ifndef _BLACKFIN_DPMC_H_
 #define _BLACKFIN_DPMC_H_
 
+#include <mach/pll.h>
+
 /* PLL_CTL Masks */
 #define DF                     0x0001  /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
 #define PLL_OFF                        0x0002  /* PLL Not Powered */
index 234fbac17ec115a6357ae88d05b395ddf80478d3..dccae26805b0a38c4b09ecd836a12de422bb1a52 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004-2009 Analog Devices Inc.
+ * Copyright 2004-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
 #ifndef _BFIN_IO_H
 #define _BFIN_IO_H
 
-#ifdef __KERNEL__
-
-#ifndef __ASSEMBLY__
-#include <linux/types.h>
-#endif
 #include <linux/compiler.h>
-
-/*
- * These are for ISA/PCI shared memory _only_ and should never be used
- * on any other type of memory, including Zorro memory. They are meant to
- * access the bus in the bus byte order which is little-endian!.
- *
- * readX/writeX() are used to access memory mapped devices. On some
- * architectures the memory mapped IO stuff needs to be accessed
- * differently. On the bfin architecture, we just read/write the
- * memory location directly.
- */
-#ifndef __ASSEMBLY__
-
-static inline unsigned char readb(const volatile void __iomem *addr)
-{
-       unsigned int val;
-       int tmp;
-
-       __asm__ __volatile__ (
-               "cli %1;"
-               "NOP; NOP; SSYNC;"
-               "%0 = b [%2] (z);"
-               "sti %1;"
-               : "=d"(val), "=d"(tmp)
-               : "a"(addr)
-       );
-
-       return (unsigned char) val;
-}
-
-static inline unsigned short readw(const volatile void __iomem *addr)
-{
-       unsigned int val;
-       int tmp;
-
-       __asm__ __volatile__ (
-               "cli %1;"
-               "NOP; NOP; SSYNC;"
-               "%0 = w [%2] (z);"
-               "sti %1;"
-               : "=d"(val), "=d"(tmp)
-               : "a"(addr)
-       );
-
-       return (unsigned short) val;
-}
-
-static inline unsigned int readl(const volatile void __iomem *addr)
-{
-       unsigned int val;
-       int tmp;
-
-       __asm__ __volatile__ (
-               "cli %1;"
-               "NOP; NOP; SSYNC;"
-               "%0 = [%2];"
-               "sti %1;"
-               : "=d"(val), "=d"(tmp)
-               : "a"(addr)
-       );
-
-       return val;
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+#define DECLARE_BFIN_RAW_READX(size, type, asm, asm_sign) \
+static inline type __raw_read##size(const volatile void __iomem *addr) \
+{ \
+       unsigned int val; \
+       int tmp; \
+       __asm__ __volatile__ ( \
+               "cli %1;" \
+               "NOP; NOP; SSYNC;" \
+               "%0 = "#asm" [%2] "#asm_sign";" \
+               "sti %1;" \
+               : "=d"(val), "=d"(tmp) \
+               : "a"(addr) \
+       ); \
+       return (type) val; \
 }
-
-#endif /*  __ASSEMBLY__ */
-
-#define writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b))
-#define writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b))
-#define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b))
-
-#define __raw_readb readb
-#define __raw_readw readw
-#define __raw_readl readl
-#define __raw_writeb writeb
-#define __raw_writew writew
-#define __raw_writel writel
-#define memset_io(a, b, c)     memset((void *)(a), (b), (c))
-#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c))
-#define memcpy_toio(a, b, c)   memcpy((void *)(a), (b), (c))
-
-/* Convert "I/O port addresses" to actual addresses.  i.e. ugly casts. */
-#define __io(port) ((void *)(unsigned long)(port))
-
-#define inb(port)    readb(__io(port))
-#define inw(port)    readw(__io(port))
-#define inl(port)    readl(__io(port))
-#define outb(x, port) writeb(x, __io(port))
-#define outw(x, port) writew(x, __io(port))
-#define outl(x, port) writel(x, __io(port))
-
-#define inb_p(port)    inb(__io(port))
-#define inw_p(port)    inw(__io(port))
-#define inl_p(port)    inl(__io(port))
-#define outb_p(x, port) outb(x, __io(port))
-#define outw_p(x, port) outw(x, __io(port))
-#define outl_p(x, port) outl(x, __io(port))
-
-#define ioread8_rep(a, d, c)   readsb(a, d, c)
-#define ioread16_rep(a, d, c)  readsw(a, d, c)
-#define ioread32_rep(a, d, c)  readsl(a, d, c)
-#define iowrite8_rep(a, s, c)  writesb(a, s, c)
-#define iowrite16_rep(a, s, c) writesw(a, s, c)
-#define iowrite32_rep(a, s, c) writesl(a, s, c)
-
-#define ioread8(x)                     readb(x)
-#define ioread16(x)                    readw(x)
-#define ioread32(x)                    readl(x)
-#define iowrite8(val, x)               writeb(val, x)
-#define iowrite16(val, x)              writew(val, x)
-#define iowrite32(val, x)              writel(val, x)
-
-/**
- * I/O write barrier
- *
- * Ensure ordering of I/O space writes. This will make sure that writes
- * following the barrier will arrive after all previous writes.
- */
-#define mmiowb() do { SSYNC(); wmb(); } while (0)
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/* Values for nocacheflag and cmode */
-#define IOMAP_NOCACHE_SER              1
-
-#ifndef __ASSEMBLY__
+DECLARE_BFIN_RAW_READX(b, u8, b, (z))
+#define __raw_readb __raw_readb
+DECLARE_BFIN_RAW_READX(w, u16, w, (z))
+#define __raw_readw __raw_readw
+DECLARE_BFIN_RAW_READX(l, u32, , )
+#define __raw_readl __raw_readl
 
 extern void outsb(unsigned long port, const void *addr, unsigned long count);
 extern void outsw(unsigned long port, const void *addr, unsigned long count);
 extern void outsw_8(unsigned long port, const void *addr, unsigned long count);
 extern void outsl(unsigned long port, const void *addr, unsigned long count);
+#define outsb outsb
+#define outsw outsw
+#define outsl outsl
 
 extern void insb(unsigned long port, void *addr, unsigned long count);
 extern void insw(unsigned long port, void *addr, unsigned long count);
 extern void insw_8(unsigned long port, void *addr, unsigned long count);
 extern void insl(unsigned long port, void *addr, unsigned long count);
 extern void insl_16(unsigned long port, void *addr, unsigned long count);
+#define insb insb
+#define insw insw
+#define insl insl
 
 extern void dma_outsb(unsigned long port, const void *addr, unsigned short count);
 extern void dma_outsw(unsigned long port, const void *addr, unsigned short count);
@@ -158,108 +58,14 @@ extern void dma_insb(unsigned long port, void *addr, unsigned short count);
 extern void dma_insw(unsigned long port, void *addr, unsigned short count);
 extern void dma_insl(unsigned long port, void *addr, unsigned short count);
 
-static inline void readsl(const void __iomem *addr, void *buf, int len)
-{
-       insl((unsigned long)addr, buf, len);
-}
-
-static inline void readsw(const void __iomem *addr, void *buf, int len)
-{
-       insw((unsigned long)addr, buf, len);
-}
-
-static inline void readsb(const void __iomem *addr, void *buf, int len)
-{
-       insb((unsigned long)addr, buf, len);
-}
-
-static inline void writesl(const void __iomem *addr, const void *buf, int len)
-{
-       outsl((unsigned long)addr, buf, len);
-}
-
-static inline void writesw(const void __iomem *addr, const void *buf, int len)
-{
-       outsw((unsigned long)addr, buf, len);
-}
-
-static inline void writesb(const void __iomem *addr, const void *buf, int len)
-{
-       outsb((unsigned long)addr, buf, len);
-}
-
-/*
- * Map some physical address range into the kernel address space.
- */
-static inline void __iomem *__ioremap(unsigned long physaddr, unsigned long size,
-                               int cacheflag)
-{
-       return (void __iomem *)physaddr;
-}
-
-/*
- * Unmap a ioremap()ed region again
- */
-static inline void iounmap(void *addr)
-{
-}
-
-/*
- * __iounmap unmaps nearly everything, so be careful
- * it doesn't free currently pointer/page tables anymore but it
- * wans't used anyway and might be added later.
- */
-static inline void __iounmap(void *addr, unsigned long size)
-{
-}
-
-/*
- * Set new cache mode for some kernel address space.
- * The caller must push data for that range itself, if such data may already
- * be in the cache.
+/**
+ * I/O write barrier
+ *
+ * Ensure ordering of I/O space writes. This will make sure that writes
+ * following the barrier will arrive after all previous writes.
  */
-static inline void kernel_set_cachemode(void *addr, unsigned long size,
-                                       int cmode)
-{
-}
-
-static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size)
-{
-       return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
-}
-static inline void __iomem *ioremap_nocache(unsigned long physaddr,
-                                           unsigned long size)
-{
-       return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
-}
+#define mmiowb() do { SSYNC(); wmb(); } while (0)
 
-extern void blkfin_inv_cache_all(void);
+#include <asm-generic/io.h>
 
 #endif
-
-#define        ioport_map(port, nr)            ((void __iomem*)(port))
-#define        ioport_unmap(addr)
-
-/* Pages to physical address... */
-#define page_to_bus(page)       ((page - mem_map) << PAGE_SHIFT)
-
-#define phys_to_virt(vaddr)    ((void *) (vaddr))
-#define virt_to_phys(vaddr)    ((unsigned long) (vaddr))
-
-#define virt_to_bus virt_to_phys
-#define bus_to_virt phys_to_virt
-
-/*
- * Convert a physical pointer to a virtual kernel pointer for /dev/mem
- * access
- */
-#define xlate_dev_mem_ptr(p)   __va(p)
-
-/*
- * Convert a virtual cached pointer to an uncached pointer
- */
-#define xlate_dev_kmem_ptr(p)  p
-
-#endif                         /* __KERNEL__ */
-
-#endif                         /* _BFIN_IO_H */
index 41c4d70544ef4811cd23c85f03c68122221f7aae..3365cb97f539a7ede6d2a6e225b2ec69b579b4b6 100644 (file)
@@ -13,9 +13,6 @@
 #ifdef CONFIG_SMP
 # include <asm/pda.h>
 # include <asm/processor.h>
-/* Forward decl needed due to cdef inter dependencies */
-static inline uint32_t __pure bfin_dspid(void);
-# define blackfin_core_id() (bfin_dspid() & 0xff)
 # define bfin_irq_flags cpu_pda[blackfin_core_id()].imask
 #else
 extern unsigned long bfin_irq_flags;
index aea880274de7223f99c5049425c8c5a1b64b603a..8af7772e84ccfdcfbba38d1b11eca4cad1926d45 100644 (file)
@@ -14,7 +14,7 @@
 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
 
 #include <asm/ptrace.h>
-#include <asm/blackfin.h>
+#include <mach/blackfin.h>
 
 static inline unsigned long rdusp(void)
 {
@@ -134,6 +134,8 @@ static inline uint32_t __pure bfin_dspid(void)
        return bfin_read_DSPID();
 }
 
+#define blackfin_core_id() (bfin_dspid() & 0xff)
+
 static inline uint32_t __pure bfin_compiled_revid(void)
 {
 #if defined(CONFIG_BF_REV_0_0)
index 1942ccfedbe01fc0b9dfe5681aec33e5e2258a8b..1f286e71c21fb3fd3944b8656c2789b9fe5865b5 100644 (file)
@@ -17,12 +17,12 @@ asmlinkage int __raw_spin_is_locked_asm(volatile int *ptr);
 asmlinkage void __raw_spin_lock_asm(volatile int *ptr);
 asmlinkage int __raw_spin_trylock_asm(volatile int *ptr);
 asmlinkage void __raw_spin_unlock_asm(volatile int *ptr);
-asmlinkage void arch_read_lock_asm(volatile int *ptr);
-asmlinkage int arch_read_trylock_asm(volatile int *ptr);
-asmlinkage void arch_read_unlock_asm(volatile int *ptr);
-asmlinkage void arch_write_lock_asm(volatile int *ptr);
-asmlinkage int arch_write_trylock_asm(volatile int *ptr);
-asmlinkage void arch_write_unlock_asm(volatile int *ptr);
+asmlinkage void __raw_read_lock_asm(volatile int *ptr);
+asmlinkage int __raw_read_trylock_asm(volatile int *ptr);
+asmlinkage void __raw_read_unlock_asm(volatile int *ptr);
+asmlinkage void __raw_write_lock_asm(volatile int *ptr);
+asmlinkage int __raw_write_trylock_asm(volatile int *ptr);
+asmlinkage void __raw_write_unlock_asm(volatile int *ptr);
 
 static inline int arch_spin_is_locked(arch_spinlock_t *lock)
 {
@@ -64,32 +64,36 @@ static inline int arch_write_can_lock(arch_rwlock_t *rw)
 
 static inline void arch_read_lock(arch_rwlock_t *rw)
 {
-       arch_read_lock_asm(&rw->lock);
+       __raw_read_lock_asm(&rw->lock);
 }
 
+#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
+
 static inline int arch_read_trylock(arch_rwlock_t *rw)
 {
-       return arch_read_trylock_asm(&rw->lock);
+       return __raw_read_trylock_asm(&rw->lock);
 }
 
 static inline void arch_read_unlock(arch_rwlock_t *rw)
 {
-       arch_read_unlock_asm(&rw->lock);
+       __raw_read_unlock_asm(&rw->lock);
 }
 
 static inline void arch_write_lock(arch_rwlock_t *rw)
 {
-       arch_write_lock_asm(&rw->lock);
+       __raw_write_lock_asm(&rw->lock);
 }
 
+#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
+
 static inline int arch_write_trylock(arch_rwlock_t *rw)
 {
-       return arch_write_trylock_asm(&rw->lock);
+       return __raw_write_trylock_asm(&rw->lock);
 }
 
 static inline void arch_write_unlock(arch_rwlock_t *rw)
 {
-       arch_write_unlock_asm(&rw->lock);
+       __raw_write_unlock_asm(&rw->lock);
 }
 
 #define arch_spin_relax(lock)          cpu_relax()
diff --git a/arch/blackfin/include/mach-common/pll.h b/arch/blackfin/include/mach-common/pll.h
new file mode 100644 (file)
index 0000000..382178b
--- /dev/null
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2005-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _MACH_COMMON_PLL_H
+#define _MACH_COMMON_PLL_H
+
+#ifndef __ASSEMBLY__
+
+#include <asm/blackfin.h>
+#include <asm/irqflags.h>
+
+#ifndef bfin_iwr_restore
+static inline void
+bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2)
+{
+#ifdef SIC_IWR
+       bfin_write_SIC_IWR(iwr0);
+#else
+       bfin_write_SIC_IWR0(iwr0);
+# ifdef SIC_IWR1
+       bfin_write_SIC_IWR1(iwr1);
+# endif
+# ifdef SIC_IWR2
+       bfin_write_SIC_IWR2(iwr2);
+# endif
+#endif
+}
+#endif
+
+#ifndef bfin_iwr_save
+static inline void
+bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2,
+              unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
+{
+#ifdef SIC_IWR
+       *iwr0 = bfin_read_SIC_IWR();
+#else
+       *iwr0 = bfin_read_SIC_IWR0();
+# ifdef SIC_IWR1
+       *iwr1 = bfin_read_SIC_IWR1();
+# endif
+# ifdef SIC_IWR2
+       *iwr2 = bfin_read_SIC_IWR2();
+# endif
+#endif
+       bfin_iwr_restore(niwr0, niwr1, niwr2);
+}
+#endif
+
+static inline void _bfin_write_pll_relock(u32 addr, unsigned int val)
+{
+       unsigned long flags, iwr0, iwr1, iwr2;
+
+       if (val == bfin_read_PLL_CTL())
+               return;
+
+       flags = hard_local_irq_save();
+       /* Enable the PLL Wakeup bit in SIC IWR */
+       bfin_iwr_save(IWR_ENABLE(0), 0, 0, &iwr0, &iwr1, &iwr2);
+
+       bfin_write16(addr, val);
+       SSYNC();
+       asm("IDLE;");
+
+       bfin_iwr_restore(iwr0, iwr1, iwr2);
+       hard_local_irq_restore(flags);
+}
+
+/* Writing to PLL_CTL initiates a PLL relock sequence */
+static inline void bfin_write_PLL_CTL(unsigned int val)
+{
+       _bfin_write_pll_relock(PLL_CTL, val);
+}
+
+/* Writing to VR_CTL initiates a PLL relock sequence */
+static inline void bfin_write_VR_CTL(unsigned int val)
+{
+       _bfin_write_pll_relock(VR_CTL, val);
+}
+
+#endif
+
+#endif
diff --git a/arch/blackfin/include/mach-common/ports-a.h b/arch/blackfin/include/mach-common/ports-a.h
new file mode 100644 (file)
index 0000000..9f78a76
--- /dev/null
@@ -0,0 +1,25 @@
+/*
+ * Port A Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_A__
+#define __BFIN_PERIPHERAL_PORT_A__
+
+#define PA0            (1 << 0)
+#define PA1            (1 << 1)
+#define PA2            (1 << 2)
+#define PA3            (1 << 3)
+#define PA4            (1 << 4)
+#define PA5            (1 << 5)
+#define PA6            (1 << 6)
+#define PA7            (1 << 7)
+#define PA8            (1 << 8)
+#define PA9            (1 << 9)
+#define PA10           (1 << 10)
+#define PA11           (1 << 11)
+#define PA12           (1 << 12)
+#define PA13           (1 << 13)
+#define PA14           (1 << 14)
+#define PA15           (1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/mach-common/ports-b.h b/arch/blackfin/include/mach-common/ports-b.h
new file mode 100644 (file)
index 0000000..b81702f
--- /dev/null
@@ -0,0 +1,25 @@
+/*
+ * Port B Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_B__
+#define __BFIN_PERIPHERAL_PORT_B__
+
+#define PB0            (1 << 0)
+#define PB1            (1 << 1)
+#define PB2            (1 << 2)
+#define PB3            (1 << 3)
+#define PB4            (1 << 4)
+#define PB5            (1 << 5)
+#define PB6            (1 << 6)
+#define PB7            (1 << 7)
+#define PB8            (1 << 8)
+#define PB9            (1 << 9)
+#define PB10           (1 << 10)
+#define PB11           (1 << 11)
+#define PB12           (1 << 12)
+#define PB13           (1 << 13)
+#define PB14           (1 << 14)
+#define PB15           (1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/mach-common/ports-c.h b/arch/blackfin/include/mach-common/ports-c.h
new file mode 100644 (file)
index 0000000..3cc665e
--- /dev/null
@@ -0,0 +1,25 @@
+/*
+ * Port C Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_C__
+#define __BFIN_PERIPHERAL_PORT_C__
+
+#define PC0            (1 << 0)
+#define PC1            (1 << 1)
+#define PC2            (1 << 2)
+#define PC3            (1 << 3)
+#define PC4            (1 << 4)
+#define PC5            (1 << 5)
+#define PC6            (1 << 6)
+#define PC7            (1 << 7)
+#define PC8            (1 << 8)
+#define PC9            (1 << 9)
+#define PC10           (1 << 10)
+#define PC11           (1 << 11)
+#define PC12           (1 << 12)
+#define PC13           (1 << 13)
+#define PC14           (1 << 14)
+#define PC15           (1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/mach-common/ports-d.h b/arch/blackfin/include/mach-common/ports-d.h
new file mode 100644 (file)
index 0000000..868c6a0
--- /dev/null
@@ -0,0 +1,25 @@
+/*
+ * Port D Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_D__
+#define __BFIN_PERIPHERAL_PORT_D__
+
+#define PD0            (1 << 0)
+#define PD1            (1 << 1)
+#define PD2            (1 << 2)
+#define PD3            (1 << 3)
+#define PD4            (1 << 4)
+#define PD5            (1 << 5)
+#define PD6            (1 << 6)
+#define PD7            (1 << 7)
+#define PD8            (1 << 8)
+#define PD9            (1 << 9)
+#define PD10           (1 << 10)
+#define PD11           (1 << 11)
+#define PD12           (1 << 12)
+#define PD13           (1 << 13)
+#define PD14           (1 << 14)
+#define PD15           (1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/mach-common/ports-e.h b/arch/blackfin/include/mach-common/ports-e.h
new file mode 100644 (file)
index 0000000..c88b0d0
--- /dev/null
@@ -0,0 +1,25 @@
+/*
+ * Port E Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_E__
+#define __BFIN_PERIPHERAL_PORT_E__
+
+#define PE0            (1 << 0)
+#define PE1            (1 << 1)
+#define PE2            (1 << 2)
+#define PE3            (1 << 3)
+#define PE4            (1 << 4)
+#define PE5            (1 << 5)
+#define PE6            (1 << 6)
+#define PE7            (1 << 7)
+#define PE8            (1 << 8)
+#define PE9            (1 << 9)
+#define PE10           (1 << 10)
+#define PE11           (1 << 11)
+#define PE12           (1 << 12)
+#define PE13           (1 << 13)
+#define PE14           (1 << 14)
+#define PE15           (1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/mach-common/ports-f.h b/arch/blackfin/include/mach-common/ports-f.h
new file mode 100644 (file)
index 0000000..d6af206
--- /dev/null
@@ -0,0 +1,25 @@
+/*
+ * Port F Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_F__
+#define __BFIN_PERIPHERAL_PORT_F__
+
+#define PF0            (1 << 0)
+#define PF1            (1 << 1)
+#define PF2            (1 << 2)
+#define PF3            (1 << 3)
+#define PF4            (1 << 4)
+#define PF5            (1 << 5)
+#define PF6            (1 << 6)
+#define PF7            (1 << 7)
+#define PF8            (1 << 8)
+#define PF9            (1 << 9)
+#define PF10           (1 << 10)
+#define PF11           (1 << 11)
+#define PF12           (1 << 12)
+#define PF13           (1 << 13)
+#define PF14           (1 << 14)
+#define PF15           (1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/mach-common/ports-g.h b/arch/blackfin/include/mach-common/ports-g.h
new file mode 100644 (file)
index 0000000..09355d3
--- /dev/null
@@ -0,0 +1,25 @@
+/*
+ * Port G Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_G__
+#define __BFIN_PERIPHERAL_PORT_G__
+
+#define PG0            (1 << 0)
+#define PG1            (1 << 1)
+#define PG2            (1 << 2)
+#define PG3            (1 << 3)
+#define PG4            (1 << 4)
+#define PG5            (1 << 5)
+#define PG6            (1 << 6)
+#define PG7            (1 << 7)
+#define PG8            (1 << 8)
+#define PG9            (1 << 9)
+#define PG10           (1 << 10)
+#define PG11           (1 << 11)
+#define PG12           (1 << 12)
+#define PG13           (1 << 13)
+#define PG14           (1 << 14)
+#define PG15           (1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/mach-common/ports-h.h b/arch/blackfin/include/mach-common/ports-h.h
new file mode 100644 (file)
index 0000000..fa3910c
--- /dev/null
@@ -0,0 +1,25 @@
+/*
+ * Port H Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_H__
+#define __BFIN_PERIPHERAL_PORT_H__
+
+#define PH0            (1 << 0)
+#define PH1            (1 << 1)
+#define PH2            (1 << 2)
+#define PH3            (1 << 3)
+#define PH4            (1 << 4)
+#define PH5            (1 << 5)
+#define PH6            (1 << 6)
+#define PH7            (1 << 7)
+#define PH8            (1 << 8)
+#define PH9            (1 << 9)
+#define PH10           (1 << 10)
+#define PH11           (1 << 11)
+#define PH12           (1 << 12)
+#define PH13           (1 << 13)
+#define PH14           (1 << 14)
+#define PH15           (1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/mach-common/ports-i.h b/arch/blackfin/include/mach-common/ports-i.h
new file mode 100644 (file)
index 0000000..f176f08
--- /dev/null
@@ -0,0 +1,25 @@
+/*
+ * Port I Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_I__
+#define __BFIN_PERIPHERAL_PORT_I__
+
+#define PI0            (1 << 0)
+#define PI1            (1 << 1)
+#define PI2            (1 << 2)
+#define PI3            (1 << 3)
+#define PI4            (1 << 4)
+#define PI5            (1 << 5)
+#define PI6            (1 << 6)
+#define PI7            (1 << 7)
+#define PI8            (1 << 8)
+#define PI9            (1 << 9)
+#define PI10           (1 << 10)
+#define PI11           (1 << 11)
+#define PI12           (1 << 12)
+#define PI13           (1 << 13)
+#define PI14           (1 << 14)
+#define PI15           (1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/mach-common/ports-j.h b/arch/blackfin/include/mach-common/ports-j.h
new file mode 100644 (file)
index 0000000..924123e
--- /dev/null
@@ -0,0 +1,25 @@
+/*
+ * Port J Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_J__
+#define __BFIN_PERIPHERAL_PORT_J__
+
+#define PJ0            (1 << 0)
+#define PJ1            (1 << 1)
+#define PJ2            (1 << 2)
+#define PJ3            (1 << 3)
+#define PJ4            (1 << 4)
+#define PJ5            (1 << 5)
+#define PJ6            (1 << 6)
+#define PJ7            (1 << 7)
+#define PJ8            (1 << 8)
+#define PJ9            (1 << 9)
+#define PJ10           (1 << 10)
+#define PJ11           (1 << 11)
+#define PJ12           (1 << 12)
+#define PJ13           (1 << 13)
+#define PJ14           (1 << 14)
+#define PJ15           (1 << 15)
+
+#endif
index bfe75af4e8bd71db8fbe50c7bfe2a30c8ba00723..886e00014d7514a5a83fa3f5b31c064f53ba12f8 100644 (file)
@@ -116,7 +116,7 @@ void __init generate_cplb_tables_all(void)
            ((_ramend - uncached_end) >= 1 * 1024 * 1024))
                dcplb_bounds[i_d].eaddr = uncached_end;
        else
-               dcplb_bounds[i_d].eaddr = uncached_end & ~(1 * 1024 * 1024);
+               dcplb_bounds[i_d].eaddr = uncached_end & ~(1 * 1024 * 1024 - 1);
        dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
        /* DMA uncached region.  */
        if (DMA_UNCACHED_REGION) {
index edae461b1c545d4f02e3c91ac664ec55012b9c4c..eb92592fd80ccb4beddb6ee828179c05f03d3d90 100644 (file)
@@ -345,6 +345,23 @@ void kgdb_roundup_cpu(int cpu, unsigned long flags)
 }
 #endif
 
+#ifdef CONFIG_IPIPE
+static unsigned long kgdb_arch_imask;
+#endif
+
+void kgdb_post_primary_code(struct pt_regs *regs, int e_vector, int err_code)
+{
+       if (kgdb_single_step)
+               preempt_enable();
+
+#ifdef CONFIG_IPIPE
+       if (kgdb_arch_imask) {
+               cpu_pda[raw_smp_processor_id()].ex_imask = kgdb_arch_imask;
+               kgdb_arch_imask = 0;
+       }
+#endif
+}
+
 int kgdb_arch_handle_exception(int vector, int signo,
                               int err_code, char *remcom_in_buffer,
                               char *remcom_out_buffer,
@@ -388,6 +405,12 @@ int kgdb_arch_handle_exception(int vector, int signo,
                         * kgdb_single_step > 0 means in single step mode
                         */
                        kgdb_single_step = i + 1;
+
+                       preempt_disable();
+#ifdef CONFIG_IPIPE
+                       kgdb_arch_imask = cpu_pda[raw_smp_processor_id()].ex_imask;
+                       cpu_pda[raw_smp_processor_id()].ex_imask = 0;
+#endif
                }
 
                bfin_correct_hw_break();
@@ -448,6 +471,9 @@ void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long ip)
 int kgdb_arch_init(void)
 {
        kgdb_single_step = 0;
+#ifdef CONFIG_IPIPE
+       kgdb_arch_imask = 0;
+#endif
 
        bfin_remove_all_hw_break();
        return 0;
index 08c0236acf3c5ab903d5e863b17f8290bd4a8e7a..2a6e9dbb62a5d9eeb28e15f5817136058764bdc4 100644 (file)
@@ -95,6 +95,10 @@ static int __init kgdbtest_init(void)
 {
        struct proc_dir_entry *entry;
 
+#if L2_LENGTH
+       num2 = 0;
+#endif
+
        entry = proc_create("kgdbtest", 0, NULL, &kgdb_test_proc_fops);
        if (entry == NULL)
                return -ENOMEM;
index b894c8abe7ecaa8734a1fca6e8d643054bd9dfab..c0ccadcfa44e7a73fa7ee1e48f8aa1e287f0e4e9 100644 (file)
@@ -104,24 +104,23 @@ static const unsigned short bfin_mac_peripherals[] = {
 
 static struct bfin_phydev_platform_data bfin_phydev_data[] = {
        {
-               .addr = 1,
-               .irq = IRQ_MAC_PHYINT,
-       },
-       {
-               .addr = 2,
-               .irq = IRQ_MAC_PHYINT,
-       },
-       {
+#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
                .addr = 3,
+#else
+               .addr = 1,
+#endif
                .irq = IRQ_MAC_PHYINT,
        },
 };
 
 static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
-       .phydev_number = 3,
+       .phydev_number = 1,
        .phydev_data = bfin_phydev_data,
        .phy_mode = PHY_INTERFACE_MODE_MII,
        .mac_peripherals = bfin_mac_peripherals,
+#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
+       .phy_mask = 0xfff7, /* Only probe the port phy connect to the on chip MAC */
+#endif
 };
 
 static struct platform_device bfin_mii_bus = {
@@ -453,7 +452,7 @@ static struct resource bfin_uart0_resources[] = {
        },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
        P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -496,7 +495,7 @@ static struct resource bfin_uart1_resources[] = {
        },
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
        P_UART1_TX, P_UART1_RX, 0
 };
 
@@ -636,9 +635,9 @@ static struct resource bfin_sport0_uart_resources[] = {
        },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
        P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-       P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+       P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -670,9 +669,9 @@ static struct resource bfin_sport1_uart_resources[] = {
        },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
        P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-       P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+       P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
index e6ce1d7c523a4ef6d222f88e9646645ea44f9446..50fc5c89e3790803d2f1cd7ce6bbe327a75fed15 100644 (file)
@@ -377,7 +377,7 @@ static struct resource bfin_uart0_resources[] = {
        },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
        P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -420,7 +420,7 @@ static struct resource bfin_uart1_resources[] = {
        },
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
        P_UART1_TX, P_UART1_RX, 0
 };
 
@@ -547,9 +547,9 @@ static struct resource bfin_sport0_uart_resources[] = {
        },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
        P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-       P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+       P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -581,9 +581,9 @@ static struct resource bfin_sport1_uart_resources[] = {
        },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
        P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-       P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+       P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
index 78b43605a0b55ebf7a3b628c47fe85cf06ef67ef..bcd1fbc8c543a18b409eda532f6b4ec027efbffe 100644 (file)
@@ -11,7 +11,7 @@
 #include <asm/blackfin.h>
 #include <asm/dma.h>
 
-struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
+struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
        (struct dma_register *) DMA0_NEXT_DESC_PTR,
        (struct dma_register *) DMA1_NEXT_DESC_PTR,
        (struct dma_register *) DMA2_NEXT_DESC_PTR,
diff --git a/arch/blackfin/mach-bf518/include/mach/bfin_serial.h b/arch/blackfin/mach-bf518/include/mach/bfin_serial.h
new file mode 100644 (file)
index 0000000..00c603f
--- /dev/null
@@ -0,0 +1,14 @@
+/*
+ * mach/bfin_serial.h - Blackfin UART/Serial definitions
+ *
+ * Copyright 2006-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_MACH_SERIAL_H__
+#define __BFIN_MACH_SERIAL_H__
+
+#define BFIN_UART_NR_PORTS     2
+
+#endif
index 970d310021e73639e7861e75b91aeeaccac549d4..f6d924ac0c44ff76619c3925bb77735e08ac5bf2 100644 (file)
@@ -4,36 +4,9 @@
  * Licensed under the GPL-2 or later
  */
 
-#include <linux/serial.h>
 #include <asm/dma.h>
 #include <asm/portmux.h>
 
-#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
-#define UART_GET_DLL(uart)     bfin_read16(((uart)->port.membase + OFFSET_DLL))
-#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
-#define UART_GET_DLH(uart)     bfin_read16(((uart)->port.membase + OFFSET_DLH))
-#define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
-#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
-#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
-
-#define UART_PUT_CHAR(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_THR), v)
-#define UART_PUT_DLL(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
-#define UART_PUT_IER(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_IER), v)
-#define UART_SET_IER(uart, v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
-#define UART_CLEAR_IER(uart, v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
-#define UART_PUT_DLH(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
-#define UART_PUT_LCR(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
-#define UART_PUT_GCTL(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
-
-#define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
-#define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
-
-#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
-#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
-#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
-#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
-
 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
 # define CONFIG_SERIAL_BFIN_CTSRTS
 
 # endif
 #endif
 
-#define BFIN_UART_TX_FIFO_SIZE 2
-
-/*
- * The pin configuration is different from schematic
- */
-struct bfin_serial_port {
-       struct uart_port port;
-       unsigned int old_status;
-       int status_irq;
-       unsigned int lsr;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-       int tx_done;
-       int tx_count;
-       struct circ_buf rx_dma_buf;
-       struct timer_list rx_dma_timer;
-       int rx_dma_nrows;
-       unsigned int tx_dma_channel;
-       unsigned int rx_dma_channel;
-       struct work_struct tx_dma_workqueue;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-       struct timer_list cts_timer;
-       int cts_pin;
-       int rts_pin;
-#endif
-};
-
-/* The hardware clears the LSR bits upon read, so we need to cache
- * some of the more fun bits in software so they don't get lost
- * when checking the LSR in other code paths (TX).
- */
-static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
-{
-       unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
-       uart->lsr |= (lsr & (BI|FE|PE|OE));
-       return lsr | uart->lsr;
-}
-
-static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
-{
-       uart->lsr = 0;
-       bfin_write16(uart->port.membase + OFFSET_LSR, -1);
-}
-
 struct bfin_serial_res {
        unsigned long uart_base_addr;
        int uart_irq;
@@ -146,3 +75,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
 };
 
 #define DRIVER_NAME "bfin-uart"
+
+#include <asm/bfin_serial.h>
index 9053462be4b169068b8fdf3b3fdfc75e10e4ee74..a8828863226e4b07d74eb5b94a6bacd5fde4f785 100644 (file)
@@ -1,61 +1,43 @@
 /*
- * Copyright 2008-2009 Analog Devices Inc.
+ * Copyright 2008-2010 Analog Devices Inc.
  *
- * Licensed under the GPL-2 or later
+ * Licensed under the GPL-2 or later.
  */
 
 #ifndef _MACH_BLACKFIN_H_
 #define _MACH_BLACKFIN_H_
 
 #include "bf518.h"
-#include "defBF512.h"
 #include "anomaly.h"
 
-#if defined(CONFIG_BF518)
-#include "defBF518.h"
+#include <asm/def_LPBlackfin.h>
+#ifdef CONFIG_BF512
+# include "defBF512.h"
 #endif
-
-#if defined(CONFIG_BF516)
-#include "defBF516.h"
-#endif
-
-#if defined(CONFIG_BF514)
-#include "defBF514.h"
+#ifdef CONFIG_BF514
+# include "defBF514.h"
 #endif
-
-#if defined(CONFIG_BF512)
-#include "defBF512.h"
+#ifdef CONFIG_BF516
+# include "defBF516.h"
 #endif
-
-#if !defined(__ASSEMBLY__)
-#include "cdefBF512.h"
-
-#if defined(CONFIG_BF518)
-#include "cdefBF518.h"
+#ifdef CONFIG_BF518
+# include "defBF518.h"
 #endif
 
-#if defined(CONFIG_BF516)
-#include "cdefBF516.h"
+#ifndef __ASSEMBLY__
+# include <asm/cdef_LPBlackfin.h>
+# ifdef CONFIG_BF512
+#  include "cdefBF512.h"
+# endif
+# ifdef CONFIG_BF514
+#  include "cdefBF514.h"
+# endif
+# ifdef CONFIG_BF516
+#  include "cdefBF516.h"
+# endif
+# ifdef CONFIG_BF518
+#  include "cdefBF518.h"
+# endif
 #endif
 
-#if defined(CONFIG_BF514)
-#include "cdefBF514.h"
-#endif
-#endif
-
-#define BFIN_UART_NR_PORTS     2
-
-#define OFFSET_THR              0x00   /* Transmit Holding register            */
-#define OFFSET_RBR              0x00   /* Receive Buffer register              */
-#define OFFSET_DLL              0x00   /* Divisor Latch (Low-Byte)             */
-#define OFFSET_IER              0x04   /* Interrupt Enable Register            */
-#define OFFSET_DLH              0x04   /* Divisor Latch (High-Byte)            */
-#define OFFSET_IIR              0x08   /* Interrupt Identification Register    */
-#define OFFSET_LCR              0x0C   /* Line Control Register                */
-#define OFFSET_MCR              0x10   /* Modem Control Register               */
-#define OFFSET_LSR              0x14   /* Line Status Register                 */
-#define OFFSET_MSR              0x18   /* Modem Status Register                */
-#define OFFSET_SCR              0x1C   /* SCR Scratch Register                 */
-#define OFFSET_GCTL             0x24   /* Global Control Register              */
-
 #endif
index 493020d0a65ae39495289390246c84b6d5a16ad8..b657d37a3402d094b3191c5a1e4bba1a0f65a6c7 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2009 Analog Devices Inc.
+ * Copyright 2008-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
 #ifndef _CDEF_BF512_H
 #define _CDEF_BF512_H
 
-/* include all Core registers and bit definitions */
-#include "defBF512.h"
+/* Clock and System Control    (0xFFC00000 - 0xFFC000FF)                                                               */
+#define bfin_read_PLL_CTL()                    bfin_read16(PLL_CTL)
+#define bfin_read_PLL_DIV()                    bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)                        bfin_write16(PLL_DIV, val)
+#define bfin_read_VR_CTL()                     bfin_read16(VR_CTL)
+#define bfin_read_PLL_STAT()                   bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)               bfin_write16(PLL_STAT, val)
+#define bfin_read_PLL_LOCKCNT()                        bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)            bfin_write16(PLL_LOCKCNT, val)
+#define bfin_read_CHIPID()                     bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)                 bfin_write32(CHIPID, val)
 
-/* include core specific register pointer definitions */
-#include <asm/cdef_LPBlackfin.h>
 
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF512 */
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)                                                       */
+#define bfin_read_SWRST()                      bfin_read16(SWRST)
+#define bfin_write_SWRST(val)                  bfin_write16(SWRST, val)
+#define bfin_read_SYSCR()                      bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)                  bfin_write16(SYSCR, val)
 
-/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
-#include "cdefBF51x_base.h"
+#define bfin_read_SIC_RVECT()                  bfin_read32(SIC_RVECT)
+#define bfin_write_SIC_RVECT(val)              bfin_write32(SIC_RVECT, val)
+#define bfin_read_SIC_IMASK0()                 bfin_read32(SIC_IMASK0)
+#define bfin_write_SIC_IMASK0(val)             bfin_write32(SIC_IMASK0, val)
+#define bfin_read_SIC_IMASK(x)                 bfin_read32(SIC_IMASK0 + (x << 6))
+#define bfin_write_SIC_IMASK(x, val)           bfin_write32((SIC_IMASK0 + (x << 6)), val)
+
+#define bfin_read_SIC_IAR0()                   bfin_read32(SIC_IAR0)
+#define bfin_write_SIC_IAR0(val)               bfin_write32(SIC_IAR0, val)
+#define bfin_read_SIC_IAR1()                   bfin_read32(SIC_IAR1)
+#define bfin_write_SIC_IAR1(val)               bfin_write32(SIC_IAR1, val)
+#define bfin_read_SIC_IAR2()                   bfin_read32(SIC_IAR2)
+#define bfin_write_SIC_IAR2(val)               bfin_write32(SIC_IAR2, val)
+#define bfin_read_SIC_IAR3()                   bfin_read32(SIC_IAR3)
+#define bfin_write_SIC_IAR3(val)               bfin_write32(SIC_IAR3, val)
+
+#define bfin_read_SIC_ISR0()                   bfin_read32(SIC_ISR0)
+#define bfin_write_SIC_ISR0(val)               bfin_write32(SIC_ISR0, val)
+#define bfin_read_SIC_ISR(x)                   bfin_read32(SIC_ISR0 + (x << 6))
+#define bfin_write_SIC_ISR(x, val)             bfin_write32((SIC_ISR0 + (x << 6)), val)
+
+#define bfin_read_SIC_IWR0()                   bfin_read32(SIC_IWR0)
+#define bfin_write_SIC_IWR0(val)               bfin_write32(SIC_IWR0, val)
+#define bfin_read_SIC_IWR(x)                   bfin_read32(SIC_IWR0 + (x << 6))
+#define bfin_write_SIC_IWR(x, val)             bfin_write32((SIC_IWR0 + (x << 6)), val)
+
+/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */
+
+#define bfin_read_SIC_IMASK1()                 bfin_read32(SIC_IMASK1)
+#define bfin_write_SIC_IMASK1(val)             bfin_write32(SIC_IMASK1, val)
+#define bfin_read_SIC_IAR4()                   bfin_read32(SIC_IAR4)
+#define bfin_write_SIC_IAR4(val)               bfin_write32(SIC_IAR4, val)
+#define bfin_read_SIC_IAR5()                   bfin_read32(SIC_IAR5)
+#define bfin_write_SIC_IAR5(val)               bfin_write32(SIC_IAR5, val)
+#define bfin_read_SIC_IAR6()                   bfin_read32(SIC_IAR6)
+#define bfin_write_SIC_IAR6(val)               bfin_write32(SIC_IAR6, val)
+#define bfin_read_SIC_IAR7()                   bfin_read32(SIC_IAR7)
+#define bfin_write_SIC_IAR7(val)               bfin_write32(SIC_IAR7, val)
+#define bfin_read_SIC_ISR1()                   bfin_read32(SIC_ISR1)
+#define bfin_write_SIC_ISR1(val)               bfin_write32(SIC_ISR1, val)
+#define bfin_read_SIC_IWR1()                   bfin_read32(SIC_IWR1)
+#define bfin_write_SIC_IWR1(val)               bfin_write32(SIC_IWR1, val)
+
+/* Watchdog Timer              (0xFFC00200 - 0xFFC002FF)                                                                       */
+#define bfin_read_WDOG_CTL()                   bfin_read16(WDOG_CTL)
+#define bfin_write_WDOG_CTL(val)               bfin_write16(WDOG_CTL, val)
+#define bfin_read_WDOG_CNT()                   bfin_read32(WDOG_CNT)
+#define bfin_write_WDOG_CNT(val)               bfin_write32(WDOG_CNT, val)
+#define bfin_read_WDOG_STAT()                  bfin_read32(WDOG_STAT)
+#define bfin_write_WDOG_STAT(val)              bfin_write32(WDOG_STAT, val)
+
+
+/* Real Time Clock             (0xFFC00300 - 0xFFC003FF)                                                                       */
+#define bfin_read_RTC_STAT()                   bfin_read32(RTC_STAT)
+#define bfin_write_RTC_STAT(val)               bfin_write32(RTC_STAT, val)
+#define bfin_read_RTC_ICTL()                   bfin_read16(RTC_ICTL)
+#define bfin_write_RTC_ICTL(val)               bfin_write16(RTC_ICTL, val)
+#define bfin_read_RTC_ISTAT()                  bfin_read16(RTC_ISTAT)
+#define bfin_write_RTC_ISTAT(val)              bfin_write16(RTC_ISTAT, val)
+#define bfin_read_RTC_SWCNT()                  bfin_read16(RTC_SWCNT)
+#define bfin_write_RTC_SWCNT(val)              bfin_write16(RTC_SWCNT, val)
+#define bfin_read_RTC_ALARM()                  bfin_read32(RTC_ALARM)
+#define bfin_write_RTC_ALARM(val)              bfin_write32(RTC_ALARM, val)
+#define bfin_read_RTC_FAST()                   bfin_read16(RTC_FAST)
+#define bfin_write_RTC_FAST(val)               bfin_write16(RTC_FAST, val)
+#define bfin_read_RTC_PREN()                   bfin_read16(RTC_PREN)
+#define bfin_write_RTC_PREN(val)               bfin_write16(RTC_PREN, val)
+
+
+/* UART0 Controller            (0xFFC00400 - 0xFFC004FF)                                                                       */
+#define bfin_read_UART0_THR()                  bfin_read16(UART0_THR)
+#define bfin_write_UART0_THR(val)              bfin_write16(UART0_THR, val)
+#define bfin_read_UART0_RBR()                  bfin_read16(UART0_RBR)
+#define bfin_write_UART0_RBR(val)              bfin_write16(UART0_RBR, val)
+#define bfin_read_UART0_DLL()                  bfin_read16(UART0_DLL)
+#define bfin_write_UART0_DLL(val)              bfin_write16(UART0_DLL, val)
+#define bfin_read_UART0_IER()                  bfin_read16(UART0_IER)
+#define bfin_write_UART0_IER(val)              bfin_write16(UART0_IER, val)
+#define bfin_read_UART0_DLH()                  bfin_read16(UART0_DLH)
+#define bfin_write_UART0_DLH(val)              bfin_write16(UART0_DLH, val)
+#define bfin_read_UART0_IIR()                  bfin_read16(UART0_IIR)
+#define bfin_write_UART0_IIR(val)              bfin_write16(UART0_IIR, val)
+#define bfin_read_UART0_LCR()                  bfin_read16(UART0_LCR)
+#define bfin_write_UART0_LCR(val)              bfin_write16(UART0_LCR, val)
+#define bfin_read_UART0_MCR()                  bfin_read16(UART0_MCR)
+#define bfin_write_UART0_MCR(val)              bfin_write16(UART0_MCR, val)
+#define bfin_read_UART0_LSR()                  bfin_read16(UART0_LSR)
+#define bfin_write_UART0_LSR(val)              bfin_write16(UART0_LSR, val)
+#define bfin_read_UART0_MSR()                  bfin_read16(UART0_MSR)
+#define bfin_write_UART0_MSR(val)              bfin_write16(UART0_MSR, val)
+#define bfin_read_UART0_SCR()                  bfin_read16(UART0_SCR)
+#define bfin_write_UART0_SCR(val)              bfin_write16(UART0_SCR, val)
+#define bfin_read_UART0_GCTL()                 bfin_read16(UART0_GCTL)
+#define bfin_write_UART0_GCTL(val)             bfin_write16(UART0_GCTL, val)
+
+
+/* TIMER0-7 Registers          (0xFFC00600 - 0xFFC006FF)                                                               */
+#define bfin_read_TIMER0_CONFIG()              bfin_read16(TIMER0_CONFIG)
+#define bfin_write_TIMER0_CONFIG(val)          bfin_write16(TIMER0_CONFIG, val)
+#define bfin_read_TIMER0_COUNTER()             bfin_read32(TIMER0_COUNTER)
+#define bfin_write_TIMER0_COUNTER(val)         bfin_write32(TIMER0_COUNTER, val)
+#define bfin_read_TIMER0_PERIOD()              bfin_read32(TIMER0_PERIOD)
+#define bfin_write_TIMER0_PERIOD(val)          bfin_write32(TIMER0_PERIOD, val)
+#define bfin_read_TIMER0_WIDTH()               bfin_read32(TIMER0_WIDTH)
+#define bfin_write_TIMER0_WIDTH(val)           bfin_write32(TIMER0_WIDTH, val)
+
+#define bfin_read_TIMER1_CONFIG()              bfin_read16(TIMER1_CONFIG)
+#define bfin_write_TIMER1_CONFIG(val)          bfin_write16(TIMER1_CONFIG, val)
+#define bfin_read_TIMER1_COUNTER()             bfin_read32(TIMER1_COUNTER)
+#define bfin_write_TIMER1_COUNTER(val)         bfin_write32(TIMER1_COUNTER, val)
+#define bfin_read_TIMER1_PERIOD()              bfin_read32(TIMER1_PERIOD)
+#define bfin_write_TIMER1_PERIOD(val)          bfin_write32(TIMER1_PERIOD, val)
+#define bfin_read_TIMER1_WIDTH()               bfin_read32(TIMER1_WIDTH)
+#define bfin_write_TIMER1_WIDTH(val)           bfin_write32(TIMER1_WIDTH, val)
+
+#define bfin_read_TIMER2_CONFIG()              bfin_read16(TIMER2_CONFIG)
+#define bfin_write_TIMER2_CONFIG(val)          bfin_write16(TIMER2_CONFIG, val)
+#define bfin_read_TIMER2_COUNTER()             bfin_read32(TIMER2_COUNTER)
+#define bfin_write_TIMER2_COUNTER(val)         bfin_write32(TIMER2_COUNTER, val)
+#define bfin_read_TIMER2_PERIOD()              bfin_read32(TIMER2_PERIOD)
+#define bfin_write_TIMER2_PERIOD(val)          bfin_write32(TIMER2_PERIOD, val)
+#define bfin_read_TIMER2_WIDTH()               bfin_read32(TIMER2_WIDTH)
+#define bfin_write_TIMER2_WIDTH(val)           bfin_write32(TIMER2_WIDTH, val)
+
+#define bfin_read_TIMER3_CONFIG()              bfin_read16(TIMER3_CONFIG)
+#define bfin_write_TIMER3_CONFIG(val)          bfin_write16(TIMER3_CONFIG, val)
+#define bfin_read_TIMER3_COUNTER()             bfin_read32(TIMER3_COUNTER)
+#define bfin_write_TIMER3_COUNTER(val)         bfin_write32(TIMER3_COUNTER, val)
+#define bfin_read_TIMER3_PERIOD()              bfin_read32(TIMER3_PERIOD)
+#define bfin_write_TIMER3_PERIOD(val)          bfin_write32(TIMER3_PERIOD, val)
+#define bfin_read_TIMER3_WIDTH()               bfin_read32(TIMER3_WIDTH)
+#define bfin_write_TIMER3_WIDTH(val)           bfin_write32(TIMER3_WIDTH, val)
+
+#define bfin_read_TIMER4_CONFIG()              bfin_read16(TIMER4_CONFIG)
+#define bfin_write_TIMER4_CONFIG(val)          bfin_write16(TIMER4_CONFIG, val)
+#define bfin_read_TIMER4_COUNTER()             bfin_read32(TIMER4_COUNTER)
+#define bfin_write_TIMER4_COUNTER(val)         bfin_write32(TIMER4_COUNTER, val)
+#define bfin_read_TIMER4_PERIOD()              bfin_read32(TIMER4_PERIOD)
+#define bfin_write_TIMER4_PERIOD(val)          bfin_write32(TIMER4_PERIOD, val)
+#define bfin_read_TIMER4_WIDTH()               bfin_read32(TIMER4_WIDTH)
+#define bfin_write_TIMER4_WIDTH(val)           bfin_write32(TIMER4_WIDTH, val)
+
+#define bfin_read_TIMER5_CONFIG()              bfin_read16(TIMER5_CONFIG)
+#define bfin_write_TIMER5_CONFIG(val)          bfin_write16(TIMER5_CONFIG, val)
+#define bfin_read_TIMER5_COUNTER()             bfin_read32(TIMER5_COUNTER)
+#define bfin_write_TIMER5_COUNTER(val)         bfin_write32(TIMER5_COUNTER, val)
+#define bfin_read_TIMER5_PERIOD()              bfin_read32(TIMER5_PERIOD)
+#define bfin_write_TIMER5_PERIOD(val)          bfin_write32(TIMER5_PERIOD, val)
+#define bfin_read_TIMER5_WIDTH()               bfin_read32(TIMER5_WIDTH)
+#define bfin_write_TIMER5_WIDTH(val)           bfin_write32(TIMER5_WIDTH, val)
+
+#define bfin_read_TIMER6_CONFIG()              bfin_read16(TIMER6_CONFIG)
+#define bfin_write_TIMER6_CONFIG(val)          bfin_write16(TIMER6_CONFIG, val)
+#define bfin_read_TIMER6_COUNTER()             bfin_read32(TIMER6_COUNTER)
+#define bfin_write_TIMER6_COUNTER(val)         bfin_write32(TIMER6_COUNTER, val)
+#define bfin_read_TIMER6_PERIOD()              bfin_read32(TIMER6_PERIOD)
+#define bfin_write_TIMER6_PERIOD(val)          bfin_write32(TIMER6_PERIOD, val)
+#define bfin_read_TIMER6_WIDTH()               bfin_read32(TIMER6_WIDTH)
+#define bfin_write_TIMER6_WIDTH(val)           bfin_write32(TIMER6_WIDTH, val)
+
+#define bfin_read_TIMER7_CONFIG()              bfin_read16(TIMER7_CONFIG)
+#define bfin_write_TIMER7_CONFIG(val)          bfin_write16(TIMER7_CONFIG, val)
+#define bfin_read_TIMER7_COUNTER()             bfin_read32(TIMER7_COUNTER)
+#define bfin_write_TIMER7_COUNTER(val)         bfin_write32(TIMER7_COUNTER, val)
+#define bfin_read_TIMER7_PERIOD()              bfin_read32(TIMER7_PERIOD)
+#define bfin_write_TIMER7_PERIOD(val)          bfin_write32(TIMER7_PERIOD, val)
+#define bfin_read_TIMER7_WIDTH()               bfin_read32(TIMER7_WIDTH)
+#define bfin_write_TIMER7_WIDTH(val)           bfin_write32(TIMER7_WIDTH, val)
+
+#define bfin_read_TIMER_ENABLE()               bfin_read16(TIMER_ENABLE)
+#define bfin_write_TIMER_ENABLE(val)           bfin_write16(TIMER_ENABLE, val)
+#define bfin_read_TIMER_DISABLE()              bfin_read16(TIMER_DISABLE)
+#define bfin_write_TIMER_DISABLE(val)          bfin_write16(TIMER_DISABLE, val)
+#define bfin_read_TIMER_STATUS()               bfin_read32(TIMER_STATUS)
+#define bfin_write_TIMER_STATUS(val)           bfin_write32(TIMER_STATUS, val)
+
+
+/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)                                                                */
+#define bfin_read_PORTFIO()                    bfin_read16(PORTFIO)
+#define bfin_write_PORTFIO(val)                        bfin_write16(PORTFIO, val)
+#define bfin_read_PORTFIO_CLEAR()              bfin_read16(PORTFIO_CLEAR)
+#define bfin_write_PORTFIO_CLEAR(val)          bfin_write16(PORTFIO_CLEAR, val)
+#define bfin_read_PORTFIO_SET()                        bfin_read16(PORTFIO_SET)
+#define bfin_write_PORTFIO_SET(val)            bfin_write16(PORTFIO_SET, val)
+#define bfin_read_PORTFIO_TOGGLE()             bfin_read16(PORTFIO_TOGGLE)
+#define bfin_write_PORTFIO_TOGGLE(val)         bfin_write16(PORTFIO_TOGGLE, val)
+#define bfin_read_PORTFIO_MASKA()              bfin_read16(PORTFIO_MASKA)
+#define bfin_write_PORTFIO_MASKA(val)          bfin_write16(PORTFIO_MASKA, val)
+#define bfin_read_PORTFIO_MASKA_CLEAR()                bfin_read16(PORTFIO_MASKA_CLEAR)
+#define bfin_write_PORTFIO_MASKA_CLEAR(val)    bfin_write16(PORTFIO_MASKA_CLEAR, val)
+#define bfin_read_PORTFIO_MASKA_SET()          bfin_read16(PORTFIO_MASKA_SET)
+#define bfin_write_PORTFIO_MASKA_SET(val)      bfin_write16(PORTFIO_MASKA_SET, val)
+#define bfin_read_PORTFIO_MASKA_TOGGLE()       bfin_read16(PORTFIO_MASKA_TOGGLE)
+#define bfin_write_PORTFIO_MASKA_TOGGLE(val)   bfin_write16(PORTFIO_MASKA_TOGGLE, val)
+#define bfin_read_PORTFIO_MASKB()              bfin_read16(PORTFIO_MASKB)
+#define bfin_write_PORTFIO_MASKB(val)          bfin_write16(PORTFIO_MASKB, val)
+#define bfin_read_PORTFIO_MASKB_CLEAR()                bfin_read16(PORTFIO_MASKB_CLEAR)
+#define bfin_write_PORTFIO_MASKB_CLEAR(val)    bfin_write16(PORTFIO_MASKB_CLEAR, val)
+#define bfin_read_PORTFIO_MASKB_SET()          bfin_read16(PORTFIO_MASKB_SET)
+#define bfin_write_PORTFIO_MASKB_SET(val)      bfin_write16(PORTFIO_MASKB_SET, val)
+#define bfin_read_PORTFIO_MASKB_TOGGLE()       bfin_read16(PORTFIO_MASKB_TOGGLE)
+#define bfin_write_PORTFIO_MASKB_TOGGLE(val)   bfin_write16(PORTFIO_MASKB_TOGGLE, val)
+#define bfin_read_PORTFIO_DIR()                        bfin_read16(PORTFIO_DIR)
+#define bfin_write_PORTFIO_DIR(val)            bfin_write16(PORTFIO_DIR, val)
+#define bfin_read_PORTFIO_POLAR()              bfin_read16(PORTFIO_POLAR)
+#define bfin_write_PORTFIO_POLAR(val)          bfin_write16(PORTFIO_POLAR, val)
+#define bfin_read_PORTFIO_EDGE()               bfin_read16(PORTFIO_EDGE)
+#define bfin_write_PORTFIO_EDGE(val)           bfin_write16(PORTFIO_EDGE, val)
+#define bfin_read_PORTFIO_BOTH()               bfin_read16(PORTFIO_BOTH)
+#define bfin_write_PORTFIO_BOTH(val)           bfin_write16(PORTFIO_BOTH, val)
+#define bfin_read_PORTFIO_INEN()               bfin_read16(PORTFIO_INEN)
+#define bfin_write_PORTFIO_INEN(val)           bfin_write16(PORTFIO_INEN, val)
+
+
+/* SPORT0 Controller           (0xFFC00800 - 0xFFC008FF)                                                               */
+#define bfin_read_SPORT0_TCR1()                        bfin_read16(SPORT0_TCR1)
+#define bfin_write_SPORT0_TCR1(val)            bfin_write16(SPORT0_TCR1, val)
+#define bfin_read_SPORT0_TCR2()                        bfin_read16(SPORT0_TCR2)
+#define bfin_write_SPORT0_TCR2(val)            bfin_write16(SPORT0_TCR2, val)
+#define bfin_read_SPORT0_TCLKDIV()             bfin_read16(SPORT0_TCLKDIV)
+#define bfin_write_SPORT0_TCLKDIV(val)         bfin_write16(SPORT0_TCLKDIV, val)
+#define bfin_read_SPORT0_TFSDIV()              bfin_read16(SPORT0_TFSDIV)
+#define bfin_write_SPORT0_TFSDIV(val)          bfin_write16(SPORT0_TFSDIV, val)
+#define bfin_read_SPORT0_TX()                  bfin_read32(SPORT0_TX)
+#define bfin_write_SPORT0_TX(val)              bfin_write32(SPORT0_TX, val)
+#define bfin_read_SPORT0_RX()                  bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX(val)              bfin_write32(SPORT0_RX, val)
+#define bfin_read_SPORT0_TX32()                        bfin_read32(SPORT0_TX)
+#define bfin_write_SPORT0_TX32(val)            bfin_write32(SPORT0_TX, val)
+#define bfin_read_SPORT0_RX32()                        bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX32(val)            bfin_write32(SPORT0_RX, val)
+#define bfin_read_SPORT0_TX16()                        bfin_read16(SPORT0_TX)
+#define bfin_write_SPORT0_TX16(val)            bfin_write16(SPORT0_TX, val)
+#define bfin_read_SPORT0_RX16()                        bfin_read16(SPORT0_RX)
+#define bfin_write_SPORT0_RX16(val)            bfin_write16(SPORT0_RX, val)
+#define bfin_read_SPORT0_RCR1()                        bfin_read16(SPORT0_RCR1)
+#define bfin_write_SPORT0_RCR1(val)            bfin_write16(SPORT0_RCR1, val)
+#define bfin_read_SPORT0_RCR2()                        bfin_read16(SPORT0_RCR2)
+#define bfin_write_SPORT0_RCR2(val)            bfin_write16(SPORT0_RCR2, val)
+#define bfin_read_SPORT0_RCLKDIV()             bfin_read16(SPORT0_RCLKDIV)
+#define bfin_write_SPORT0_RCLKDIV(val)         bfin_write16(SPORT0_RCLKDIV, val)
+#define bfin_read_SPORT0_RFSDIV()              bfin_read16(SPORT0_RFSDIV)
+#define bfin_write_SPORT0_RFSDIV(val)          bfin_write16(SPORT0_RFSDIV, val)
+#define bfin_read_SPORT0_STAT()                        bfin_read16(SPORT0_STAT)
+#define bfin_write_SPORT0_STAT(val)            bfin_write16(SPORT0_STAT, val)
+#define bfin_read_SPORT0_CHNL()                        bfin_read16(SPORT0_CHNL)
+#define bfin_write_SPORT0_CHNL(val)            bfin_write16(SPORT0_CHNL, val)
+#define bfin_read_SPORT0_MCMC1()               bfin_read16(SPORT0_MCMC1)
+#define bfin_write_SPORT0_MCMC1(val)           bfin_write16(SPORT0_MCMC1, val)
+#define bfin_read_SPORT0_MCMC2()               bfin_read16(SPORT0_MCMC2)
+#define bfin_write_SPORT0_MCMC2(val)           bfin_write16(SPORT0_MCMC2, val)
+#define bfin_read_SPORT0_MTCS0()               bfin_read32(SPORT0_MTCS0)
+#define bfin_write_SPORT0_MTCS0(val)           bfin_write32(SPORT0_MTCS0, val)
+#define bfin_read_SPORT0_MTCS1()               bfin_read32(SPORT0_MTCS1)
+#define bfin_write_SPORT0_MTCS1(val)           bfin_write32(SPORT0_MTCS1, val)
+#define bfin_read_SPORT0_MTCS2()               bfin_read32(SPORT0_MTCS2)
+#define bfin_write_SPORT0_MTCS2(val)           bfin_write32(SPORT0_MTCS2, val)
+#define bfin_read_SPORT0_MTCS3()               bfin_read32(SPORT0_MTCS3)
+#define bfin_write_SPORT0_MTCS3(val)           bfin_write32(SPORT0_MTCS3, val)
+#define bfin_read_SPORT0_MRCS0()               bfin_read32(SPORT0_MRCS0)
+#define bfin_write_SPORT0_MRCS0(val)           bfin_write32(SPORT0_MRCS0, val)
+#define bfin_read_SPORT0_MRCS1()               bfin_read32(SPORT0_MRCS1)
+#define bfin_write_SPORT0_MRCS1(val)           bfin_write32(SPORT0_MRCS1, val)
+#define bfin_read_SPORT0_MRCS2()               bfin_read32(SPORT0_MRCS2)
+#define bfin_write_SPORT0_MRCS2(val)           bfin_write32(SPORT0_MRCS2, val)
+#define bfin_read_SPORT0_MRCS3()               bfin_read32(SPORT0_MRCS3)
+#define bfin_write_SPORT0_MRCS3(val)           bfin_write32(SPORT0_MRCS3, val)
+
+
+/* SPORT1 Controller           (0xFFC00900 - 0xFFC009FF)                                                               */
+#define bfin_read_SPORT1_TCR1()                        bfin_read16(SPORT1_TCR1)
+#define bfin_write_SPORT1_TCR1(val)            bfin_write16(SPORT1_TCR1, val)
+#define bfin_read_SPORT1_TCR2()                        bfin_read16(SPORT1_TCR2)
+#define bfin_write_SPORT1_TCR2(val)            bfin_write16(SPORT1_TCR2, val)
+#define bfin_read_SPORT1_TCLKDIV()             bfin_read16(SPORT1_TCLKDIV)
+#define bfin_write_SPORT1_TCLKDIV(val)         bfin_write16(SPORT1_TCLKDIV, val)
+#define bfin_read_SPORT1_TFSDIV()              bfin_read16(SPORT1_TFSDIV)
+#define bfin_write_SPORT1_TFSDIV(val)          bfin_write16(SPORT1_TFSDIV, val)
+#define bfin_read_SPORT1_TX()                  bfin_read32(SPORT1_TX)
+#define bfin_write_SPORT1_TX(val)              bfin_write32(SPORT1_TX, val)
+#define bfin_read_SPORT1_RX()                  bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX(val)              bfin_write32(SPORT1_RX, val)
+#define bfin_read_SPORT1_TX32()                        bfin_read32(SPORT1_TX)
+#define bfin_write_SPORT1_TX32(val)            bfin_write32(SPORT1_TX, val)
+#define bfin_read_SPORT1_RX32()                        bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX32(val)            bfin_write32(SPORT1_RX, val)
+#define bfin_read_SPORT1_TX16()                        bfin_read16(SPORT1_TX)
+#define bfin_write_SPORT1_TX16(val)            bfin_write16(SPORT1_TX, val)
+#define bfin_read_SPORT1_RX16()                        bfin_read16(SPORT1_RX)
+#define bfin_write_SPORT1_RX16(val)            bfin_write16(SPORT1_RX, val)
+#define bfin_read_SPORT1_RCR1()                        bfin_read16(SPORT1_RCR1)
+#define bfin_write_SPORT1_RCR1(val)            bfin_write16(SPORT1_RCR1, val)
+#define bfin_read_SPORT1_RCR2()                        bfin_read16(SPORT1_RCR2)
+#define bfin_write_SPORT1_RCR2(val)            bfin_write16(SPORT1_RCR2, val)
+#define bfin_read_SPORT1_RCLKDIV()             bfin_read16(SPORT1_RCLKDIV)
+#define bfin_write_SPORT1_RCLKDIV(val)         bfin_write16(SPORT1_RCLKDIV, val)
+#define bfin_read_SPORT1_RFSDIV()              bfin_read16(SPORT1_RFSDIV)
+#define bfin_write_SPORT1_RFSDIV(val)          bfin_write16(SPORT1_RFSDIV, val)
+#define bfin_read_SPORT1_STAT()                        bfin_read16(SPORT1_STAT)
+#define bfin_write_SPORT1_STAT(val)            bfin_write16(SPORT1_STAT, val)
+#define bfin_read_SPORT1_CHNL()                        bfin_read16(SPORT1_CHNL)
+#define bfin_write_SPORT1_CHNL(val)            bfin_write16(SPORT1_CHNL, val)
+#define bfin_read_SPORT1_MCMC1()               bfin_read16(SPORT1_MCMC1)
+#define bfin_write_SPORT1_MCMC1(val)           bfin_write16(SPORT1_MCMC1, val)
+#define bfin_read_SPORT1_MCMC2()               bfin_read16(SPORT1_MCMC2)
+#define bfin_write_SPORT1_MCMC2(val)           bfin_write16(SPORT1_MCMC2, val)
+#define bfin_read_SPORT1_MTCS0()               bfin_read32(SPORT1_MTCS0)
+#define bfin_write_SPORT1_MTCS0(val)           bfin_write32(SPORT1_MTCS0, val)
+#define bfin_read_SPORT1_MTCS1()               bfin_read32(SPORT1_MTCS1)
+#define bfin_write_SPORT1_MTCS1(val)           bfin_write32(SPORT1_MTCS1, val)
+#define bfin_read_SPORT1_MTCS2()               bfin_read32(SPORT1_MTCS2)
+#define bfin_write_SPORT1_MTCS2(val)           bfin_write32(SPORT1_MTCS2, val)
+#define bfin_read_SPORT1_MTCS3()               bfin_read32(SPORT1_MTCS3)
+#define bfin_write_SPORT1_MTCS3(val)           bfin_write32(SPORT1_MTCS3, val)
+#define bfin_read_SPORT1_MRCS0()               bfin_read32(SPORT1_MRCS0)
+#define bfin_write_SPORT1_MRCS0(val)           bfin_write32(SPORT1_MRCS0, val)
+#define bfin_read_SPORT1_MRCS1()               bfin_read32(SPORT1_MRCS1)
+#define bfin_write_SPORT1_MRCS1(val)           bfin_write32(SPORT1_MRCS1, val)
+#define bfin_read_SPORT1_MRCS2()               bfin_read32(SPORT1_MRCS2)
+#define bfin_write_SPORT1_MRCS2(val)           bfin_write32(SPORT1_MRCS2, val)
+#define bfin_read_SPORT1_MRCS3()               bfin_read32(SPORT1_MRCS3)
+#define bfin_write_SPORT1_MRCS3(val)           bfin_write32(SPORT1_MRCS3, val)
+
+
+/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)                                                       */
+#define bfin_read_EBIU_AMGCTL()                        bfin_read16(EBIU_AMGCTL)
+#define bfin_write_EBIU_AMGCTL(val)            bfin_write16(EBIU_AMGCTL, val)
+#define bfin_read_EBIU_AMBCTL0()               bfin_read32(EBIU_AMBCTL0)
+#define bfin_write_EBIU_AMBCTL0(val)           bfin_write32(EBIU_AMBCTL0, val)
+#define bfin_read_EBIU_AMBCTL1()               bfin_read32(EBIU_AMBCTL1)
+#define bfin_write_EBIU_AMBCTL1(val)           bfin_write32(EBIU_AMBCTL1, val)
+#define bfin_read_EBIU_SDGCTL()                        bfin_read32(EBIU_SDGCTL)
+#define bfin_write_EBIU_SDGCTL(val)            bfin_write32(EBIU_SDGCTL, val)
+#define bfin_read_EBIU_SDBCTL()                        bfin_read16(EBIU_SDBCTL)
+#define bfin_write_EBIU_SDBCTL(val)            bfin_write16(EBIU_SDBCTL, val)
+#define bfin_read_EBIU_SDRRC()                 bfin_read16(EBIU_SDRRC)
+#define bfin_write_EBIU_SDRRC(val)             bfin_write16(EBIU_SDRRC, val)
+#define bfin_read_EBIU_SDSTAT()                        bfin_read16(EBIU_SDSTAT)
+#define bfin_write_EBIU_SDSTAT(val)            bfin_write16(EBIU_SDSTAT, val)
+
+
+/* DMA Traffic Control Registers                                                                                                       */
+#define bfin_read_DMAC_TC_PER()                        bfin_read16(DMAC_TC_PER)
+#define bfin_write_DMAC_TC_PER(val)            bfin_write16(DMAC_TC_PER, val)
+#define bfin_read_DMAC_TC_CNT()                        bfin_read16(DMAC_TC_CNT)
+#define bfin_write_DMAC_TC_CNT(val)            bfin_write16(DMAC_TC_CNT, val)
+
+/* DMA Controller                                                                                                                                      */
+#define bfin_read_DMA0_CONFIG()                        bfin_read16(DMA0_CONFIG)
+#define bfin_write_DMA0_CONFIG(val)            bfin_write16(DMA0_CONFIG, val)
+#define bfin_read_DMA0_NEXT_DESC_PTR()         bfin_read32(DMA0_NEXT_DESC_PTR)
+#define bfin_write_DMA0_NEXT_DESC_PTR(val)     bfin_write32(DMA0_NEXT_DESC_PTR, val)
+#define bfin_read_DMA0_START_ADDR()            bfin_read32(DMA0_START_ADDR)
+#define bfin_write_DMA0_START_ADDR(val)                bfin_write32(DMA0_START_ADDR, val)
+#define bfin_read_DMA0_X_COUNT()               bfin_read16(DMA0_X_COUNT)
+#define bfin_write_DMA0_X_COUNT(val)           bfin_write16(DMA0_X_COUNT, val)
+#define bfin_read_DMA0_Y_COUNT()               bfin_read16(DMA0_Y_COUNT)
+#define bfin_write_DMA0_Y_COUNT(val)           bfin_write16(DMA0_Y_COUNT, val)
+#define bfin_read_DMA0_X_MODIFY()              bfin_read16(DMA0_X_MODIFY)
+#define bfin_write_DMA0_X_MODIFY(val)          bfin_write16(DMA0_X_MODIFY, val)
+#define bfin_read_DMA0_Y_MODIFY()              bfin_read16(DMA0_Y_MODIFY)
+#define bfin_write_DMA0_Y_MODIFY(val)          bfin_write16(DMA0_Y_MODIFY, val)
+#define bfin_read_DMA0_CURR_DESC_PTR()         bfin_read32(DMA0_CURR_DESC_PTR)
+#define bfin_write_DMA0_CURR_DESC_PTR(val)     bfin_write32(DMA0_CURR_DESC_PTR, val)
+#define bfin_read_DMA0_CURR_ADDR()             bfin_read32(DMA0_CURR_ADDR)
+#define bfin_write_DMA0_CURR_ADDR(val)         bfin_write32(DMA0_CURR_ADDR, val)
+#define bfin_read_DMA0_CURR_X_COUNT()          bfin_read16(DMA0_CURR_X_COUNT)
+#define bfin_write_DMA0_CURR_X_COUNT(val)      bfin_write16(DMA0_CURR_X_COUNT, val)
+#define bfin_read_DMA0_CURR_Y_COUNT()          bfin_read16(DMA0_CURR_Y_COUNT)
+#define bfin_write_DMA0_CURR_Y_COUNT(val)      bfin_write16(DMA0_CURR_Y_COUNT, val)
+#define bfin_read_DMA0_IRQ_STATUS()            bfin_read16(DMA0_IRQ_STATUS)
+#define bfin_write_DMA0_IRQ_STATUS(val)                bfin_write16(DMA0_IRQ_STATUS, val)
+#define bfin_read_DMA0_PERIPHERAL_MAP()                bfin_read16(DMA0_PERIPHERAL_MAP)
+#define bfin_write_DMA0_PERIPHERAL_MAP(val)    bfin_write16(DMA0_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA1_CONFIG()                        bfin_read16(DMA1_CONFIG)
+#define bfin_write_DMA1_CONFIG(val)            bfin_write16(DMA1_CONFIG, val)
+#define bfin_read_DMA1_NEXT_DESC_PTR()         bfin_read32(DMA1_NEXT_DESC_PTR)
+#define bfin_write_DMA1_NEXT_DESC_PTR(val)     bfin_write32(DMA1_NEXT_DESC_PTR, val)
+#define bfin_read_DMA1_START_ADDR()            bfin_read32(DMA1_START_ADDR)
+#define bfin_write_DMA1_START_ADDR(val)                bfin_write32(DMA1_START_ADDR, val)
+#define bfin_read_DMA1_X_COUNT()               bfin_read16(DMA1_X_COUNT)
+#define bfin_write_DMA1_X_COUNT(val)           bfin_write16(DMA1_X_COUNT, val)
+#define bfin_read_DMA1_Y_COUNT()               bfin_read16(DMA1_Y_COUNT)
+#define bfin_write_DMA1_Y_COUNT(val)           bfin_write16(DMA1_Y_COUNT, val)
+#define bfin_read_DMA1_X_MODIFY()              bfin_read16(DMA1_X_MODIFY)
+#define bfin_write_DMA1_X_MODIFY(val)          bfin_write16(DMA1_X_MODIFY, val)
+#define bfin_read_DMA1_Y_MODIFY()              bfin_read16(DMA1_Y_MODIFY)
+#define bfin_write_DMA1_Y_MODIFY(val)          bfin_write16(DMA1_Y_MODIFY, val)
+#define bfin_read_DMA1_CURR_DESC_PTR()         bfin_read32(DMA1_CURR_DESC_PTR)
+#define bfin_write_DMA1_CURR_DESC_PTR(val)     bfin_write32(DMA1_CURR_DESC_PTR, val)
+#define bfin_read_DMA1_CURR_ADDR()             bfin_read32(DMA1_CURR_ADDR)
+#define bfin_write_DMA1_CURR_ADDR(val)         bfin_write32(DMA1_CURR_ADDR, val)
+#define bfin_read_DMA1_CURR_X_COUNT()          bfin_read16(DMA1_CURR_X_COUNT)
+#define bfin_write_DMA1_CURR_X_COUNT(val)      bfin_write16(DMA1_CURR_X_COUNT, val)
+#define bfin_read_DMA1_CURR_Y_COUNT()          bfin_read16(DMA1_CURR_Y_COUNT)
+#define bfin_write_DMA1_CURR_Y_COUNT(val)      bfin_write16(DMA1_CURR_Y_COUNT, val)
+#define bfin_read_DMA1_IRQ_STATUS()            bfin_read16(DMA1_IRQ_STATUS)
+#define bfin_write_DMA1_IRQ_STATUS(val)                bfin_write16(DMA1_IRQ_STATUS, val)
+#define bfin_read_DMA1_PERIPHERAL_MAP()                bfin_read16(DMA1_PERIPHERAL_MAP)
+#define bfin_write_DMA1_PERIPHERAL_MAP(val)    bfin_write16(DMA1_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA2_CONFIG()                        bfin_read16(DMA2_CONFIG)
+#define bfin_write_DMA2_CONFIG(val)            bfin_write16(DMA2_CONFIG, val)
+#define bfin_read_DMA2_NEXT_DESC_PTR()         bfin_read32(DMA2_NEXT_DESC_PTR)
+#define bfin_write_DMA2_NEXT_DESC_PTR(val)     bfin_write32(DMA2_NEXT_DESC_PTR, val)
+#define bfin_read_DMA2_START_ADDR()            bfin_read32(DMA2_START_ADDR)
+#define bfin_write_DMA2_START_ADDR(val)                bfin_write32(DMA2_START_ADDR, val)
+#define bfin_read_DMA2_X_COUNT()               bfin_read16(DMA2_X_COUNT)
+#define bfin_write_DMA2_X_COUNT(val)           bfin_write16(DMA2_X_COUNT, val)
+#define bfin_read_DMA2_Y_COUNT()               bfin_read16(DMA2_Y_COUNT)
+#define bfin_write_DMA2_Y_COUNT(val)           bfin_write16(DMA2_Y_COUNT, val)
+#define bfin_read_DMA2_X_MODIFY()              bfin_read16(DMA2_X_MODIFY)
+#define bfin_write_DMA2_X_MODIFY(val)          bfin_write16(DMA2_X_MODIFY, val)
+#define bfin_read_DMA2_Y_MODIFY()              bfin_read16(DMA2_Y_MODIFY)
+#define bfin_write_DMA2_Y_MODIFY(val)          bfin_write16(DMA2_Y_MODIFY, val)
+#define bfin_read_DMA2_CURR_DESC_PTR()         bfin_read32(DMA2_CURR_DESC_PTR)
+#define bfin_write_DMA2_CURR_DESC_PTR(val)     bfin_write32(DMA2_CURR_DESC_PTR, val)
+#define bfin_read_DMA2_CURR_ADDR()             bfin_read32(DMA2_CURR_ADDR)
+#define bfin_write_DMA2_CURR_ADDR(val)         bfin_write32(DMA2_CURR_ADDR, val)
+#define bfin_read_DMA2_CURR_X_COUNT()          bfin_read16(DMA2_CURR_X_COUNT)
+#define bfin_write_DMA2_CURR_X_COUNT(val)      bfin_write16(DMA2_CURR_X_COUNT, val)
+#define bfin_read_DMA2_CURR_Y_COUNT()          bfin_read16(DMA2_CURR_Y_COUNT)
+#define bfin_write_DMA2_CURR_Y_COUNT(val)      bfin_write16(DMA2_CURR_Y_COUNT, val)
+#define bfin_read_DMA2_IRQ_STATUS()            bfin_read16(DMA2_IRQ_STATUS)
+#define bfin_write_DMA2_IRQ_STATUS(val)                bfin_write16(DMA2_IRQ_STATUS, val)
+#define bfin_read_DMA2_PERIPHERAL_MAP()                bfin_read16(DMA2_PERIPHERAL_MAP)
+#define bfin_write_DMA2_PERIPHERAL_MAP(val)    bfin_write16(DMA2_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA3_CONFIG()                        bfin_read16(DMA3_CONFIG)
+#define bfin_write_DMA3_CONFIG(val)            bfin_write16(DMA3_CONFIG, val)
+#define bfin_read_DMA3_NEXT_DESC_PTR()         bfin_read32(DMA3_NEXT_DESC_PTR)
+#define bfin_write_DMA3_NEXT_DESC_PTR(val)     bfin_write32(DMA3_NEXT_DESC_PTR, val)
+#define bfin_read_DMA3_START_ADDR()            bfin_read32(DMA3_START_ADDR)
+#define bfin_write_DMA3_START_ADDR(val)                bfin_write32(DMA3_START_ADDR, val)
+#define bfin_read_DMA3_X_COUNT()               bfin_read16(DMA3_X_COUNT)
+#define bfin_write_DMA3_X_COUNT(val)           bfin_write16(DMA3_X_COUNT, val)
+#define bfin_read_DMA3_Y_COUNT()               bfin_read16(DMA3_Y_COUNT)
+#define bfin_write_DMA3_Y_COUNT(val)           bfin_write16(DMA3_Y_COUNT, val)
+#define bfin_read_DMA3_X_MODIFY()              bfin_read16(DMA3_X_MODIFY)
+#define bfin_write_DMA3_X_MODIFY(val)          bfin_write16(DMA3_X_MODIFY, val)
+#define bfin_read_DMA3_Y_MODIFY()              bfin_read16(DMA3_Y_MODIFY)
+#define bfin_write_DMA3_Y_MODIFY(val)          bfin_write16(DMA3_Y_MODIFY, val)
+#define bfin_read_DMA3_CURR_DESC_PTR()         bfin_read32(DMA3_CURR_DESC_PTR)
+#define bfin_write_DMA3_CURR_DESC_PTR(val)     bfin_write32(DMA3_CURR_DESC_PTR, val)
+#define bfin_read_DMA3_CURR_ADDR()             bfin_read32(DMA3_CURR_ADDR)
+#define bfin_write_DMA3_CURR_ADDR(val)         bfin_write32(DMA3_CURR_ADDR, val)
+#define bfin_read_DMA3_CURR_X_COUNT()          bfin_read16(DMA3_CURR_X_COUNT)
+#define bfin_write_DMA3_CURR_X_COUNT(val)      bfin_write16(DMA3_CURR_X_COUNT, val)
+#define bfin_read_DMA3_CURR_Y_COUNT()          bfin_read16(DMA3_CURR_Y_COUNT)
+#define bfin_write_DMA3_CURR_Y_COUNT(val)      bfin_write16(DMA3_CURR_Y_COUNT, val)
+#define bfin_read_DMA3_IRQ_STATUS()            bfin_read16(DMA3_IRQ_STATUS)
+#define bfin_write_DMA3_IRQ_STATUS(val)                bfin_write16(DMA3_IRQ_STATUS, val)
+#define bfin_read_DMA3_PERIPHERAL_MAP()                bfin_read16(DMA3_PERIPHERAL_MAP)
+#define bfin_write_DMA3_PERIPHERAL_MAP(val)    bfin_write16(DMA3_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA4_CONFIG()                        bfin_read16(DMA4_CONFIG)
+#define bfin_write_DMA4_CONFIG(val)            bfin_write16(DMA4_CONFIG, val)
+#define bfin_read_DMA4_NEXT_DESC_PTR()         bfin_read32(DMA4_NEXT_DESC_PTR)
+#define bfin_write_DMA4_NEXT_DESC_PTR(val)     bfin_write32(DMA4_NEXT_DESC_PTR, val)
+#define bfin_read_DMA4_START_ADDR()            bfin_read32(DMA4_START_ADDR)
+#define bfin_write_DMA4_START_ADDR(val)                bfin_write32(DMA4_START_ADDR, val)
+#define bfin_read_DMA4_X_COUNT()               bfin_read16(DMA4_X_COUNT)
+#define bfin_write_DMA4_X_COUNT(val)           bfin_write16(DMA4_X_COUNT, val)
+#define bfin_read_DMA4_Y_COUNT()               bfin_read16(DMA4_Y_COUNT)
+#define bfin_write_DMA4_Y_COUNT(val)           bfin_write16(DMA4_Y_COUNT, val)
+#define bfin_read_DMA4_X_MODIFY()              bfin_read16(DMA4_X_MODIFY)
+#define bfin_write_DMA4_X_MODIFY(val)          bfin_write16(DMA4_X_MODIFY, val)
+#define bfin_read_DMA4_Y_MODIFY()              bfin_read16(DMA4_Y_MODIFY)
+#define bfin_write_DMA4_Y_MODIFY(val)          bfin_write16(DMA4_Y_MODIFY, val)
+#define bfin_read_DMA4_CURR_DESC_PTR()         bfin_read32(DMA4_CURR_DESC_PTR)
+#define bfin_write_DMA4_CURR_DESC_PTR(val)     bfin_write32(DMA4_CURR_DESC_PTR, val)
+#define bfin_read_DMA4_CURR_ADDR()             bfin_read32(DMA4_CURR_ADDR)
+#define bfin_write_DMA4_CURR_ADDR(val)         bfin_write32(DMA4_CURR_ADDR, val)
+#define bfin_read_DMA4_CURR_X_COUNT()          bfin_read16(DMA4_CURR_X_COUNT)
+#define bfin_write_DMA4_CURR_X_COUNT(val)      bfin_write16(DMA4_CURR_X_COUNT, val)
+#define bfin_read_DMA4_CURR_Y_COUNT()          bfin_read16(DMA4_CURR_Y_COUNT)
+#define bfin_write_DMA4_CURR_Y_COUNT(val)      bfin_write16(DMA4_CURR_Y_COUNT, val)
+#define bfin_read_DMA4_IRQ_STATUS()            bfin_read16(DMA4_IRQ_STATUS)
+#define bfin_write_DMA4_IRQ_STATUS(val)                bfin_write16(DMA4_IRQ_STATUS, val)
+#define bfin_read_DMA4_PERIPHERAL_MAP()                bfin_read16(DMA4_PERIPHERAL_MAP)
+#define bfin_write_DMA4_PERIPHERAL_MAP(val)    bfin_write16(DMA4_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA5_CONFIG()                        bfin_read16(DMA5_CONFIG)
+#define bfin_write_DMA5_CONFIG(val)            bfin_write16(DMA5_CONFIG, val)
+#define bfin_read_DMA5_NEXT_DESC_PTR()         bfin_read32(DMA5_NEXT_DESC_PTR)
+#define bfin_write_DMA5_NEXT_DESC_PTR(val)     bfin_write32(DMA5_NEXT_DESC_PTR, val)
+#define bfin_read_DMA5_START_ADDR()            bfin_read32(DMA5_START_ADDR)
+#define bfin_write_DMA5_START_ADDR(val)                bfin_write32(DMA5_START_ADDR, val)
+#define bfin_read_DMA5_X_COUNT()               bfin_read16(DMA5_X_COUNT)
+#define bfin_write_DMA5_X_COUNT(val)           bfin_write16(DMA5_X_COUNT, val)
+#define bfin_read_DMA5_Y_COUNT()               bfin_read16(DMA5_Y_COUNT)
+#define bfin_write_DMA5_Y_COUNT(val)           bfin_write16(DMA5_Y_COUNT, val)
+#define bfin_read_DMA5_X_MODIFY()              bfin_read16(DMA5_X_MODIFY)
+#define bfin_write_DMA5_X_MODIFY(val)          bfin_write16(DMA5_X_MODIFY, val)
+#define bfin_read_DMA5_Y_MODIFY()              bfin_read16(DMA5_Y_MODIFY)
+#define bfin_write_DMA5_Y_MODIFY(val)          bfin_write16(DMA5_Y_MODIFY, val)
+#define bfin_read_DMA5_CURR_DESC_PTR()         bfin_read32(DMA5_CURR_DESC_PTR)
+#define bfin_write_DMA5_CURR_DESC_PTR(val)     bfin_write32(DMA5_CURR_DESC_PTR, val)
+#define bfin_read_DMA5_CURR_ADDR()             bfin_read32(DMA5_CURR_ADDR)
+#define bfin_write_DMA5_CURR_ADDR(val)         bfin_write32(DMA5_CURR_ADDR, val)