]> git.openfabrics.org - ~shefty/rdma-dev.git/commitdiff
ARM: bcmring: use proper MMIO accessors
authorArnd Bergmann <arnd@arndb.de>
Wed, 25 Apr 2012 16:44:23 +0000 (16:44 +0000)
committerArnd Bergmann <arnd@arndb.de>
Wed, 2 May 2012 16:21:47 +0000 (16:21 +0000)
A lot of code in bcmring just dereferences pointers to MMIO
locations, which is not safe. This annotates the pointers
correctly using __iomem and uses readl/write to access them.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
18 files changed:
arch/arm/mach-bcmring/csp/chipc/chipcHw.c
arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
arch/arm/mach-bcmring/csp/dmac/dmacHw.c
arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
arch/arm/mach-bcmring/include/mach/csp/dmacHw.h
arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
arch/arm/mach-bcmring/include/mach/csp/mm_io.h
arch/arm/mach-bcmring/include/mach/csp/reg.h
arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
arch/arm/mach-bcmring/include/mach/reg_umi.h
arch/arm/mach-bcmring/mm.c
drivers/mtd/nand/bcm_umi_nand.c
drivers/mtd/nand/nand_bcm_umi.h

index 5ac7e2509724f81f37d1270cdfa35ecc55d8f4bc..5050833817b7b6db05ee6c1635e3e3ba720a8b0d 100644 (file)
@@ -61,21 +61,21 @@ static int chipcHw_divide(int num, int denom)
 /****************************************************************************/
 chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock   /*  [ IN ] Configurable clock */
     ) {
-       volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
-       volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
-       volatile uint32_t *pDependentClock = (uint32_t *) 0x0;
+       uint32_t __iomem *pPLLReg = NULL;
+       uint32_t __iomem *pClockCtrl = NULL;
+       uint32_t __iomem *pDependentClock = NULL;
        uint32_t vcoFreqPll1Hz = 0;     /* Effective VCO frequency for PLL1 in Hz */
        uint32_t vcoFreqPll2Hz = 0;     /* Effective VCO frequency for PLL2 in Hz */
        uint32_t dependentClockType = 0;
        uint32_t vcoHz = 0;
 
        /* Get VCO frequencies */
-       if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
+       if ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
                uint64_t adjustFreq = 0;
 
                vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-                   ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+                   ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
                     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
 
                /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
@@ -86,13 +86,13 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock        /*  [ IN ] Configur
        } else {
                vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-                   ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+                   ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
                     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
        }
        vcoFreqPll2Hz =
            chipcHw_XTAL_FREQ_Hz *
                 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-           ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+           ((readl(&pChipcHw->PLLPreDivider2) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
             chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
 
        switch (clock) {
@@ -187,51 +187,51 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock      /*  [ IN ] Configur
 
        if (pPLLReg) {
                /* Obtain PLL clock frequency */
-               if (*pPLLReg & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
+               if (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
                        /* Return crystal clock frequency when bypassed */
                        return chipcHw_XTAL_FREQ_Hz;
                } else if (clock == chipcHw_CLOCK_DDR) {
                        /* DDR frequency is configured in PLLDivider register */
-                       return chipcHw_divide (vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256));
+                       return chipcHw_divide (vcoHz, (((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) ? ((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) : 256));
                } else {
                        /* From chip revision number B0, LCD clock is internally divided by 2 */
                        if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
                                vcoHz >>= 1;
                        }
                        /* Obtain PLL clock frequency using VCO dividers */
-                       return chipcHw_divide(vcoHz, ((*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
+                       return chipcHw_divide(vcoHz, ((readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ?  (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
                }
        } else if (pClockCtrl) {
                /* Obtain divider clock frequency */
                uint32_t div;
                uint32_t freq = 0;
 
-               if (*pClockCtrl & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
+               if (readl(pClockCtrl) & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
                        /* Return crystal clock frequency when bypassed */
                        return chipcHw_XTAL_FREQ_Hz;
                } else if (pDependentClock) {
                        /* Identify the dependent clock frequency */
                        switch (dependentClockType) {
                        case PLL_CLOCK:
-                               if (*pDependentClock & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
+                               if (readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
                                        /* Use crystal clock frequency when dependent PLL clock is bypassed */
                                        freq = chipcHw_XTAL_FREQ_Hz;
                                } else {
                                        /* Obtain PLL clock frequency using VCO dividers */
-                                       div = *pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK;
+                                       div = readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_MDIV_MASK;
                                        freq = div ? chipcHw_divide(vcoHz, div) : 0;
                                }
                                break;
                        case NON_PLL_CLOCK:
-                               if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) {
+                               if (pDependentClock == &pChipcHw->ACLKClock) {
                                        freq = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
                                } else {
-                                       if (*pDependentClock & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
+                                       if (readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
                                                /* Use crystal clock frequency when dependent divider clock is bypassed */
                                                freq = chipcHw_XTAL_FREQ_Hz;
                                        } else {
                                                /* Obtain divider clock frequency using XTAL dividers */
-                                               div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK;
+                                               div = readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_DIV_MASK;
                                                freq = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, (div ? div : 256));
                                        }
                                }
@@ -242,7 +242,7 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock        /*  [ IN ] Configur
                        freq = chipcHw_XTAL_FREQ_Hz;
                }
 
-               div = *pClockCtrl & chipcHw_REG_DIV_CLOCK_DIV_MASK;
+               div = readl(pClockCtrl) & chipcHw_REG_DIV_CLOCK_DIV_MASK;
                return chipcHw_divide(freq, (div ? div : 256));
        }
        return 0;
@@ -261,9 +261,9 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock        /*  [ IN ] Configur
 chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,  /*  [ IN ] Configurable clock */
                                       uint32_t freq    /*  [ IN ] Clock frequency in Hz */
     ) {
-       volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
-       volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
-       volatile uint32_t *pDependentClock = (uint32_t *) 0x0;
+       uint32_t __iomem *pPLLReg = NULL;
+       uint32_t __iomem *pClockCtrl = NULL;
+       uint32_t __iomem *pDependentClock = NULL;
        uint32_t vcoFreqPll1Hz = 0;     /* Effective VCO frequency for PLL1 in Hz */
        uint32_t desVcoFreqPll1Hz = 0;  /* Desired VCO frequency for PLL1 in Hz */
        uint32_t vcoFreqPll2Hz = 0;     /* Effective VCO frequency for PLL2 in Hz */
@@ -272,12 +272,12 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,     /*  [ IN ] Configu
        uint32_t desVcoHz = 0;
 
        /* Get VCO frequencies */
-       if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
+       if ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
                uint64_t adjustFreq = 0;
 
                vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-                   ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+                   ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
                     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
 
                /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
@@ -289,16 +289,16 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,     /*  [ IN ] Configu
                /* Desired VCO frequency */
                desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-                   (((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+                   (((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
                      chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) + 1);
        } else {
                vcoFreqPll1Hz = desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-                   ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+                   ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
                     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
        }
        vcoFreqPll2Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-           ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+           ((readl(&pChipcHw->PLLPreDivider2) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
             chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
 
        switch (clock) {
@@ -307,8 +307,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,       /*  [ IN ] Configu
                {
                        REG_LOCAL_IRQ_SAVE;
                        /* Dvide DDR_phy by two to obtain DDR_ctrl clock */
-                       pChipcHw->DDRClock = (pChipcHw->DDRClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1)
-                               << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT);
+                       writel((readl(&pChipcHw->DDRClock) & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT), &pChipcHw->DDRClock);
                        REG_LOCAL_IRQ_RESTORE;
                }
                pPLLReg = &pChipcHw->DDRClock;
@@ -329,8 +328,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,       /*  [ IN ] Configu
                /* Configure the VPM:BUS ratio settings */
                {
                        REG_LOCAL_IRQ_SAVE;
-                       pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1)
-                               << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT);
+                       writel((readl(&pChipcHw->VPMClock) & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT), &pChipcHw->VPMClock);
                        REG_LOCAL_IRQ_RESTORE;
                }
                pPLLReg = &pChipcHw->VPMClock;
@@ -428,9 +426,9 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,       /*  [ IN ] Configu
                /* For DDR settings use only the PLL divider clock */
                if (pPLLReg == &pChipcHw->DDRClock) {
                        /* Set M1DIV for PLL1, which controls the DDR clock */
-                       reg32_write(&pChipcHw->PLLDivider, (pChipcHw->PLLDivider & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24));
+                       reg32_write(&pChipcHw->PLLDivider, (readl(&pChipcHw->PLLDivider) & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24));
                        /* Calculate expected frequency */
-                       freq = chipcHw_divide(vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256));
+                       freq = chipcHw_divide(vcoHz, (((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) ? ((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) : 256));
                } else {
                        /* From chip revision number B0, LCD clock is internally divided by 2 */
                        if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
@@ -441,7 +439,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,       /*  [ IN ] Configu
                        reg32_modify_and(pPLLReg, ~(chipcHw_REG_PLL_CLOCK_MDIV_MASK));
                        reg32_modify_or(pPLLReg, chipcHw_REG_PLL_DIVIDER_MDIV(desVcoHz, freq));
                        /* Calculate expected frequency */
-                       freq = chipcHw_divide(vcoHz, ((*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
+                       freq = chipcHw_divide(vcoHz, ((readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
                }
                /* Wait for for atleast 200ns as per the protocol to change frequency */
                udelay(1);
@@ -460,16 +458,16 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,     /*  [ IN ] Configu
                if (pDependentClock) {
                        switch (dependentClockType) {
                        case PLL_CLOCK:
-                               divider = chipcHw_divide(chipcHw_divide (desVcoHz, (*pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq);
+                               divider = chipcHw_divide(chipcHw_divide (desVcoHz, (readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq);
                                break;
                        case NON_PLL_CLOCK:
                                {
                                        uint32_t sourceClock = 0;
 
-                                       if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) {
+                                       if (pDependentClock == &pChipcHw->ACLKClock) {
                                                sourceClock = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
                                        } else {
-                                               uint32_t div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK;
+                                               uint32_t div = readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_DIV_MASK;
                                                sourceClock = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, ((div) ? div : 256));
                                        }
                                        divider = chipcHw_divide(sourceClock, freq);
@@ -483,7 +481,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,       /*  [ IN ] Configu
                if (divider) {
                        REG_LOCAL_IRQ_SAVE;
                        /* Set the divider to obtain the required frequency */
-                       *pClockCtrl = (*pClockCtrl & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & chipcHw_REG_DIV_CLOCK_DIV_MASK);
+                       writel((readl(pClockCtrl) & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & chipcHw_REG_DIV_CLOCK_DIV_MASK), pClockCtrl);
                        REG_LOCAL_IRQ_RESTORE;
                        return freq;
                }
@@ -515,25 +513,26 @@ static int vpmPhaseAlignA0(void)
        int count = 0;
 
        for (iter = 0; (iter < MAX_PHASE_ALIGN_ATTEMPTS) && (adjustCount < MAX_PHASE_ADJUST_COUNT); iter++) {
-               phaseControl = (pChipcHw->VPMClock & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT;
+               phaseControl = (readl(&pChipcHw->VPMClock) & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT;
                phaseValue = 0;
                prevPhaseComp = 0;
 
                /* Step 1: Look for falling PH_COMP transition */
 
                /* Read the contents of VPM Clock resgister */
-               phaseValue = pChipcHw->VPMClock;
+               phaseValue = readl(&pChipcHw->VPMClock);
                do {
                        /* Store previous value of phase comparator */
                        prevPhaseComp = phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP;
                        /* Change the value of PH_CTRL. */
-                       reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                       reg32_write(&pChipcHw->VPMClock,
+                       (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
                        /* Wait atleast 20 ns */
                        udelay(1);
                        /* Toggle the LOAD_CH after phase control is written. */
-                       pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+                       writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
                        /* Read the contents of  VPM Clock resgister. */
-                       phaseValue = pChipcHw->VPMClock;
+                       phaseValue = readl(&pChipcHw->VPMClock);
 
                        if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
                                phaseControl = (0x3F & (phaseControl - 1));
@@ -557,12 +556,13 @@ static int vpmPhaseAlignA0(void)
 
                for (count = 0; (count < 5) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
                        phaseControl = (0x3F & (phaseControl + 1));
-                       reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                       reg32_write(&pChipcHw->VPMClock,
+                       (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
                        /* Wait atleast 20 ns */
                        udelay(1);
                        /* Toggle the LOAD_CH after phase control is written. */
-                       pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-                       phaseValue = pChipcHw->VPMClock;
+                       writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
+                       phaseValue = readl(&pChipcHw->VPMClock);
                        /* Count number of adjustment made */
                        adjustCount++;
                }
@@ -581,12 +581,13 @@ static int vpmPhaseAlignA0(void)
 
                for (count = 0; (count < 3) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
                        phaseControl = (0x3F & (phaseControl - 1));
-                       reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                       reg32_write(&pChipcHw->VPMClock,
+                       (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
                        /* Wait atleast 20 ns */
                        udelay(1);
                        /* Toggle the LOAD_CH after phase control is written. */
-                       pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-                       phaseValue = pChipcHw->VPMClock;
+                       writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
+                       phaseValue = readl(&pChipcHw->VPMClock);
                        /* Count number of adjustment made */
                        adjustCount++;
                }
@@ -605,12 +606,13 @@ static int vpmPhaseAlignA0(void)
 
                for (count = 0; (count < 5); count++) {
                        phaseControl = (0x3F & (phaseControl - 1));
-                       reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                       reg32_write(&pChipcHw->VPMClock,
+                       (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
                        /* Wait atleast 20 ns */
                        udelay(1);
                        /* Toggle the LOAD_CH after phase control is written. */
-                       pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-                       phaseValue = pChipcHw->VPMClock;
+                       writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
+                       phaseValue = readl(&pChipcHw->VPMClock);
                        /* Count number of adjustment made */
                        adjustCount++;
                }
@@ -631,14 +633,14 @@ static int vpmPhaseAlignA0(void)
                        /* Store previous value of phase comparator */
                        prevPhaseComp = phaseValue;
                        /* Change the value of PH_CTRL. */
-                       reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                       reg32_write(&pChipcHw->VPMClock,
+                       (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
                        /* Wait atleast 20 ns */
                        udelay(1);
                        /* Toggle the LOAD_CH after phase control is written. */
-                       pChipcHw->VPMClock ^=
-                           chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+                       writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
                        /* Read the contents of  VPM Clock resgister. */
-                       phaseValue = pChipcHw->VPMClock;
+                       phaseValue = readl(&pChipcHw->VPMClock);
 
                        if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
                                phaseControl = (0x3F & (phaseControl - 1));
@@ -661,13 +663,13 @@ static int vpmPhaseAlignA0(void)
        }
 
        /* For VPM Phase should be perfectly aligned. */
-       phaseControl = (((pChipcHw->VPMClock >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F);
+       phaseControl = (((readl(&pChipcHw->VPMClock) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F);
        {
                REG_LOCAL_IRQ_SAVE;
 
-               pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT);
+               writel((readl(&pChipcHw->VPMClock) & ~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT), &pChipcHw->VPMClock);
                /* Load new phase value */
-               pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+               writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
 
                REG_LOCAL_IRQ_RESTORE;
        }
@@ -697,7 +699,7 @@ int chipcHw_vpmPhaseAlign(void)
                int adjustCount = 0;
 
                /* Disable VPM access */
-               pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
+               writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1);
                /* Disable HW VPM phase alignment  */
                chipcHw_vpmHwPhaseAlignDisable();
                /* Enable SW VPM phase alignment  */
@@ -715,23 +717,24 @@ int chipcHw_vpmPhaseAlign(void)
                                phaseControl--;
                        } else {
                                /* Enable VPM access */
-                               pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
+                               writel(readl(&pChipcHw->Spare1) | chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1);
                                /* Return adjust count */
                                return adjustCount;
                        }
                        /* Change the value of PH_CTRL. */
-                       reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                       reg32_write(&pChipcHw->VPMClock,
+                       (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
                        /* Wait atleast 20 ns */
                        udelay(1);
                        /* Toggle the LOAD_CH after phase control is written. */
-                       pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+                       writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
                        /* Count adjustment */
                        adjustCount++;
                }
        }
 
        /* Disable VPM access */
-       pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
+       writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1);
        return -1;
 }
 
index a711d9bdf318084c4deb95f1963b250c3cf3276e..8377d8054168012b26dcdaacdc42f7b13c465972 100644 (file)
@@ -73,9 +73,9 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz)
 
        {
                REG_LOCAL_IRQ_SAVE;
-               pChipcHw->PLLConfig2 =
-                   chipcHw_REG_PLL_CONFIG_D_RESET |
-                   chipcHw_REG_PLL_CONFIG_A_RESET;
+               writel(chipcHw_REG_PLL_CONFIG_D_RESET |
+                      chipcHw_REG_PLL_CONFIG_A_RESET,
+                       &pChipcHw->PLLConfig2);
 
                pllPreDivider2 = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
                    chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
@@ -87,28 +87,30 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz)
                     chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
 
                /* Enable CHIPC registers to control the PLL */
-               pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
+               writel(readl(&pChipcHw->PLLStatus) | chipcHw_REG_PLL_STATUS_CONTROL_ENABLE, &pChipcHw->PLLStatus);
 
                /* Set pre divider to get desired VCO frequency */
-               pChipcHw->PLLPreDivider2 = pllPreDivider2;
+               writel(pllPreDivider2, &pChipcHw->PLLPreDivider2);
                /* Set NDIV Frac */
-               pChipcHw->PLLDivider2 = chipcHw_REG_PLL_DIVIDER_NDIV_f;
+               writel(chipcHw_REG_PLL_DIVIDER_NDIV_f, &pChipcHw->PLLDivider2);
 
                /* This has to be removed once the default values are fixed for PLL2. */
-               pChipcHw->PLLControl12 = 0x38000700;
-               pChipcHw->PLLControl22 = 0x00000015;
+               writel(0x38000700, &pChipcHw->PLLControl12);
+               writel(0x00000015, &pChipcHw->PLLControl22);
 
                /* Reset PLL2 */
                if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
-                       pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
+                       writel(chipcHw_REG_PLL_CONFIG_D_RESET |
                            chipcHw_REG_PLL_CONFIG_A_RESET |
                            chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
-                           chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+                           chipcHw_REG_PLL_CONFIG_POWER_DOWN,
+                           &pChipcHw->PLLConfig2);
                } else {
-                       pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
+                       writel(chipcHw_REG_PLL_CONFIG_D_RESET |
                            chipcHw_REG_PLL_CONFIG_A_RESET |
                            chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
-                           chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+                           chipcHw_REG_PLL_CONFIG_POWER_DOWN,
+                           &pChipcHw->PLLConfig2);
                }
                REG_LOCAL_IRQ_RESTORE;
        }
@@ -119,22 +121,25 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz)
        {
                REG_LOCAL_IRQ_SAVE;
                /* Remove analog reset and Power on the PLL */
-               pChipcHw->PLLConfig2 &=
+               writel(readl(&pChipcHw->PLLConfig2) &
                    ~(chipcHw_REG_PLL_CONFIG_A_RESET |
-                     chipcHw_REG_PLL_CONFIG_POWER_DOWN);
+                     chipcHw_REG_PLL_CONFIG_POWER_DOWN),
+                     &pChipcHw->PLLConfig2);
 
                REG_LOCAL_IRQ_RESTORE;
 
        }
 
        /* Wait until PLL is locked */
-       while (!(pChipcHw->PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
+       while (!(readl(&pChipcHw->PLLStatus2) & chipcHw_REG_PLL_STATUS_LOCKED))
                ;
 
        {
                REG_LOCAL_IRQ_SAVE;
                /* Remove digital reset */
-               pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
+               writel(readl(&pChipcHw->PLLConfig2) &
+                       ~chipcHw_REG_PLL_CONFIG_D_RESET,
+                       &pChipcHw->PLLConfig2);
 
                REG_LOCAL_IRQ_RESTORE;
        }
@@ -157,9 +162,9 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport)
        {
                REG_LOCAL_IRQ_SAVE;
 
-               pChipcHw->PLLConfig =
-                   chipcHw_REG_PLL_CONFIG_D_RESET |
-                   chipcHw_REG_PLL_CONFIG_A_RESET;
+               writel(chipcHw_REG_PLL_CONFIG_D_RESET |
+                   chipcHw_REG_PLL_CONFIG_A_RESET,
+                   &pChipcHw->PLLConfig);
                /* Setting VCO frequency */
                if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
                        pllPreDivider =
@@ -182,30 +187,22 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport)
                }
 
                /* Enable CHIPC registers to control the PLL */
-               pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
+               writel(readl(&pChipcHw->PLLStatus) | chipcHw_REG_PLL_STATUS_CONTROL_ENABLE, &pChipcHw->PLLStatus);
 
                /* Set pre divider to get desired VCO frequency */
-               pChipcHw->PLLPreDivider = pllPreDivider;
+               writel(pllPreDivider, &pChipcHw->PLLPreDivider);
                /* Set NDIV Frac */
                if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
-                       pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
-                           chipcHw_REG_PLL_DIVIDER_NDIV_f_SS;
+                       writel(chipcHw_REG_PLL_DIVIDER_M1DIV | chipcHw_REG_PLL_DIVIDER_NDIV_f_SS, &pChipcHw->PLLDivider);
                } else {
-                       pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
-                           chipcHw_REG_PLL_DIVIDER_NDIV_f;
+                       writel(chipcHw_REG_PLL_DIVIDER_M1DIV | chipcHw_REG_PLL_DIVIDER_NDIV_f, &pChipcHw->PLLDivider);
                }
 
                /* Reset PLL1 */
                if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
-                       pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
-                           chipcHw_REG_PLL_CONFIG_A_RESET |
-                           chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
-                           chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+                       writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_1601_3200 | chipcHw_REG_PLL_CONFIG_POWER_DOWN, &pChipcHw->PLLConfig);
                } else {
-                       pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
-                           chipcHw_REG_PLL_CONFIG_A_RESET |
-                           chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
-                           chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+                       writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_800_1600 | chipcHw_REG_PLL_CONFIG_POWER_DOWN, &pChipcHw->PLLConfig);
                }
 
                REG_LOCAL_IRQ_RESTORE;
@@ -216,22 +213,19 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport)
                {
                        REG_LOCAL_IRQ_SAVE;
                        /* Remove analog reset and Power on the PLL */
-                       pChipcHw->PLLConfig &=
-                           ~(chipcHw_REG_PLL_CONFIG_A_RESET |
-                             chipcHw_REG_PLL_CONFIG_POWER_DOWN);
+                       writel(readl(&pChipcHw->PLLConfig) & ~(chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_POWER_DOWN), &pChipcHw->PLLConfig);
                        REG_LOCAL_IRQ_RESTORE;
                }
 
                /* Wait until PLL is locked */
-               while (!(pChipcHw->PLLStatus & chipcHw_REG_PLL_STATUS_LOCKED)
-                      || !(pChipcHw->
-                           PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
+               while (!(readl(&pChipcHw->PLLStatus) & chipcHw_REG_PLL_STATUS_LOCKED)
+                      || !(readl(&pChipcHw->PLLStatus2) & chipcHw_REG_PLL_STATUS_LOCKED))
                        ;
 
                /* Remove digital reset */
                {
                        REG_LOCAL_IRQ_SAVE;
-                       pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
+                       writel(readl(&pChipcHw->PLLConfig) & ~chipcHw_REG_PLL_CONFIG_D_RESET, &pChipcHw->PLLConfig);
                        REG_LOCAL_IRQ_RESTORE;
                }
        }
@@ -267,11 +261,7 @@ void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam  /*  [ IN ] Misc chip initializ
        chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_SOFT_RESET);
 
        /* Before configuring the ARM clock, atleast we need to make sure BUS clock maintains the proper ratio with ARM clock */
-       pChipcHw->ACLKClock =
-           (pChipcHw->
-            ACLKClock & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam->
-                                                                armBusRatio &
-                                                                chipcHw_REG_ACLKClock_CLK_DIV_MASK);
+       writel((readl(&pChipcHw->ACLKClock) & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam-> armBusRatio & chipcHw_REG_ACLKClock_CLK_DIV_MASK), &pChipcHw->ACLKClock);
 
        /* Set various core component frequencies. The order in which this is done is important for some. */
        /* The RTBUS (DDR PHY) is derived from the BUS, and the BUS from the ARM, and VPM needs to know BUS */
index 74d2b023dcec3289a404002503912faa89f9faea..f95ce913fa1e4aec3f1f77467e1d3bad2da7ab6b 100644 (file)
@@ -50,15 +50,16 @@ void chipcHw_reset(uint32_t mask)
                        chipcHw_softReset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
                }
                /* Bypass the PLL clocks before reboot */
-               pChipcHw->UARTClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
-               pChipcHw->SPIClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
+               writel(readl(&pChipcHw->UARTClock) | chipcHw_REG_PLL_CLOCK_BYPASS_SELECT,
+                       &pChipcHw->UARTClock);
+               writel(readl(&pChipcHw->SPIClock) | chipcHw_REG_PLL_CLOCK_BYPASS_SELECT,
+                       &pChipcHw->SPIClock);
 
                /* Copy the chipcHw_warmReset_run_from_aram function into ARAM */
                do {
-                       ((uint32_t *) MM_IO_BASE_ARAM)[i] =
-                           ((uint32_t *) &chipcHw_reset_run_from_aram)[i];
+                       writel(((uint32_t *) &chipcHw_reset_run_from_aram)[i], ((uint32_t __iomem *) MM_IO_BASE_ARAM) + i);
                        i++;
-               } while (((uint32_t *) MM_IO_BASE_ARAM)[i - 1] != 0xe1a0f00f);  /* 0xe1a0f00f == asm ("mov r15, r15"); */
+               } while (readl(((uint32_t __iomem*) MM_IO_BASE_ARAM) + i - 1) != 0xe1a0f00f);   /* 0xe1a0f00f == asm ("mov r15, r15"); */
 
                flush_cache_all();
 
index 570ab0ab923213fc64e48daace574426fbbb5a49..547f746c7ff4711331774d81dd238d454498fd7f 100644 (file)
@@ -27,7 +27,7 @@
 /* ---- Include Files ---------------------------------------------------- */
 #include <linux/types.h>
 #include <linux/string.h>
-#include <stddef.h>
+#include <linux/stddef.h>
 
 #include <mach/csp/dmacHw.h>
 #include <mach/csp/dmacHw_reg.h>
@@ -55,33 +55,32 @@ static uint32_t GetFifoSize(dmacHw_HANDLE_t handle  /*   [ IN ] DMA Channel handl
     ) {
        uint32_t val = 0;
        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-       dmacHw_MISC_t *pMiscReg =
-           (dmacHw_MISC_t *) dmacHw_REG_MISC_BASE(pCblk->module);
+       dmacHw_MISC_t __iomem *pMiscReg = (void __iomem *)dmacHw_REG_MISC_BASE(pCblk->module);
 
        switch (pCblk->channel) {
        case 0:
-               val = (pMiscReg->CompParm2.lo & 0x70000000) >> 28;
+               val = (readl(&pMiscReg->CompParm2.lo) & 0x70000000) >> 28;
                break;
        case 1:
-               val = (pMiscReg->CompParm3.hi & 0x70000000) >> 28;
+               val = (readl(&pMiscReg->CompParm3.hi) & 0x70000000) >> 28;
                break;
        case 2:
-               val = (pMiscReg->CompParm3.lo & 0x70000000) >> 28;
+               val = (readl(&pMiscReg->CompParm3.lo) & 0x70000000) >> 28;
                break;
        case 3:
-               val = (pMiscReg->CompParm4.hi & 0x70000000) >> 28;
+               val = (readl(&pMiscReg->CompParm4.hi) & 0x70000000) >> 28;
                break;
        case 4:
-               val = (pMiscReg->CompParm4.lo & 0x70000000) >> 28;
+               val = (readl(&pMiscReg->CompParm4.lo) & 0x70000000) >> 28;
                break;
        case 5:
-               val = (pMiscReg->CompParm5.hi & 0x70000000) >> 28;
+               val = (readl(&pMiscReg->CompParm5.hi) & 0x70000000) >> 28;
                break;
        case 6:
-               val = (pMiscReg->CompParm5.lo & 0x70000000) >> 28;
+               val = (readl(&pMiscReg->CompParm5.lo) & 0x70000000) >> 28;
                break;
        case 7:
-               val = (pMiscReg->CompParm6.hi & 0x70000000) >> 28;
+               val = (readl(&pMiscReg->CompParm6.hi) & 0x70000000) >> 28;
                break;
        }
 
index ea0bd642b3641e22f7c3bcd2eb938bb065d8f7fc..fe438699d11ed6dffad1e8f1ea29b2d215e922d5 100644 (file)
@@ -27,7 +27,7 @@
 /* ---- Include Files ---------------------------------------------------- */
 
 #include <linux/types.h>
-#include <stddef.h>
+#include <linux/stddef.h>
 
 #include <mach/csp/dmacHw.h>
 #include <mach/csp/dmacHw_reg.h>
index 830f323c00cd25e699aaa4e1040e8892b3fdcba6..a66f3f7abb8646ef7797ec50ae2f81f22acccb82 100644 (file)
@@ -47,7 +47,7 @@ static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
 /****************************************************************************/
 static inline uint32_t chipcHw_getChipId(void)
 {
-       return pChipcHw->ChipId;
+       return readl(&pChipcHw->ChipId);
 }
 
 /****************************************************************************/
@@ -59,15 +59,16 @@ static inline uint32_t chipcHw_getChipId(void)
 /****************************************************************************/
 static inline void chipcHw_enableSpreadSpectrum(void)
 {
-       if ((pChipcHw->
-            PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) !=
+       if ((readl(&pChipcHw->
+            PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) !=
            chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
-               ddrcReg_PHY_ADDR_CTL_REGP->ssCfg =
-                   (0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) |
+               writel((0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) |
                    (ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK <<
-                    ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT);
-               ddrcReg_PHY_ADDR_CTL_REGP->ssCtl |=
-                   ddrcReg_PHY_ADDR_SS_CTRL_ENABLE;
+                    ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT),
+                    &ddrcReg_PHY_ADDR_CTL_REGP->ssCfg);
+               writel(readl(&ddrcReg_PHY_ADDR_CTL_REGP->ssCtl) |
+                   ddrcReg_PHY_ADDR_SS_CTRL_ENABLE,
+                   &ddrcReg_PHY_ADDR_CTL_REGP->ssCtl);
        }
 }
 
@@ -93,8 +94,8 @@ static inline void chipcHw_disableSpreadSpectrum(void)
 /****************************************************************************/
 static inline uint32_t chipcHw_getChipProductId(void)
 {
-       return (pChipcHw->
-                ChipId & chipcHw_REG_CHIPID_BASE_MASK) >>
+       return (readl(&pChipcHw->
+                ChipId) & chipcHw_REG_CHIPID_BASE_MASK) >>
                chipcHw_REG_CHIPID_BASE_SHIFT;
 }
 
@@ -109,7 +110,7 @@ static inline uint32_t chipcHw_getChipProductId(void)
 /****************************************************************************/
 static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void)
 {
-       return pChipcHw->ChipId & chipcHw_REG_CHIPID_REV_MASK;
+       return readl(&pChipcHw->ChipId) & chipcHw_REG_CHIPID_REV_MASK;
 }
 
 /****************************************************************************/
@@ -156,7 +157,7 @@ static inline void chipcHw_busInterfaceClockDisable(uint32_t mask)
 /****************************************************************************/
 static inline uint32_t chipcHw_getBusInterfaceClockStatus(void)
 {
-       return pChipcHw->BusIntfClock;
+       return readl(&pChipcHw->BusIntfClock);
 }
 
 /****************************************************************************/
@@ -215,8 +216,9 @@ static inline void chipcHw_softResetDisable(uint64_t mask)
 
        /* Deassert module soft reset */
        REG_LOCAL_IRQ_SAVE;
-       pChipcHw->SoftReset1 ^= ctrl1;
-       pChipcHw->SoftReset2 ^= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK));
+       writel(readl(&pChipcHw->SoftReset1) ^ ctrl1, &pChipcHw->SoftReset1);
+       writel(readl(&pChipcHw->SoftReset2) ^ (ctrl2 &
+               (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)), &pChipcHw->SoftReset2);
        REG_LOCAL_IRQ_RESTORE;
 }
 
@@ -227,9 +229,10 @@ static inline void chipcHw_softResetEnable(uint64_t mask)
        uint32_t unhold = 0;
 
        REG_LOCAL_IRQ_SAVE;
-       pChipcHw->SoftReset1 |= ctrl1;
+       writel(readl(&pChipcHw->SoftReset1) | ctrl1, &pChipcHw->SoftReset1);
        /* Mask out unhold request bits */
-       pChipcHw->SoftReset2 |= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK));
+       writel(readl(&pChipcHw->SoftReset2) | (ctrl2 &
+               (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)), &pChipcHw->SoftReset2);
 
        /* Process unhold requests */
        if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD) {
@@ -246,7 +249,7 @@ static inline void chipcHw_softResetEnable(uint64_t mask)
 
        if (unhold) {
                /* Make sure unhold request is effective */
-               pChipcHw->SoftReset1 &= ~unhold;
+               writel(readl(&pChipcHw->SoftReset1) & ~unhold, &pChipcHw->SoftReset1);
        }
        REG_LOCAL_IRQ_RESTORE;
 }
@@ -307,7 +310,7 @@ static inline void chipcHw_setOTPOption(uint64_t mask)
 /****************************************************************************/
 static inline uint32_t chipcHw_getStickyBits(void)
 {
-       return pChipcHw->Sticky;
+       return readl(&pChipcHw->Sticky);
 }
 
 /****************************************************************************/
@@ -328,7 +331,7 @@ static inline void chipcHw_setStickyBits(uint32_t mask)
                bits |= chipcHw_REG_STICKY_POR_BROM;
        } else {
                uint32_t sticky;
-               sticky = pChipcHw->Sticky;
+               sticky = readl(pChipcHw->Sticky);
 
                if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
                    && (sticky & chipcHw_REG_STICKY_BOOT_DONE) == 0) {
@@ -355,7 +358,7 @@ static inline void chipcHw_setStickyBits(uint32_t mask)
                        bits |= chipcHw_REG_STICKY_GENERAL_5;
                }
        }
-       pChipcHw->Sticky = bits;
+       writel(bits, pChipcHw->Sticky);
        REG_LOCAL_IRQ_RESTORE;
 }
 
@@ -377,7 +380,7 @@ static inline void chipcHw_clearStickyBits(uint32_t mask)
            (chipcHw_REG_STICKY_BOOT_DONE | chipcHw_REG_STICKY_GENERAL_1 |
             chipcHw_REG_STICKY_GENERAL_2 | chipcHw_REG_STICKY_GENERAL_3 |
             chipcHw_REG_STICKY_GENERAL_4 | chipcHw_REG_STICKY_GENERAL_5)) {
-               uint32_t sticky = pChipcHw->Sticky;
+               uint32_t sticky = readl(&pChipcHw->Sticky);
 
                if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
                    && (sticky & chipcHw_REG_STICKY_BOOT_DONE)) {
@@ -410,7 +413,7 @@ static inline void chipcHw_clearStickyBits(uint32_t mask)
                        mask &= ~chipcHw_REG_STICKY_GENERAL_5;
                }
        }
-       pChipcHw->Sticky = bits | mask;
+       writel(bits | mask, &pChipcHw->Sticky);
        REG_LOCAL_IRQ_RESTORE;
 }
 
@@ -426,7 +429,7 @@ static inline void chipcHw_clearStickyBits(uint32_t mask)
 /****************************************************************************/
 static inline uint32_t chipcHw_getSoftStraps(void)
 {
-       return pChipcHw->SoftStraps;
+       return readl(&pChipcHw->SoftStraps);
 }
 
 /****************************************************************************/
@@ -456,7 +459,7 @@ static inline void chipcHw_setSoftStraps(uint32_t strapOptions)
 /****************************************************************************/
 static inline uint32_t chipcHw_getPinStraps(void)
 {
-       return pChipcHw->PinStraps;
+       return readl(&pChipcHw->PinStraps);
 }
 
 /****************************************************************************/
@@ -671,9 +674,9 @@ static inline void chipcHw_selectGE3(void)
 /****************************************************************************/
 static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin)
 {
-       return (*((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) &
+       return (readl(chipcHw_REG_GPIO_MUX(pin))) &
                (chipcHw_REG_GPIO_MUX_MASK <<
-                chipcHw_REG_GPIO_MUX_POSITION(pin))) >>
+                chipcHw_REG_GPIO_MUX_POSITION(pin)) >>
            chipcHw_REG_GPIO_MUX_POSITION(pin);
 }
 
@@ -841,8 +844,8 @@ static inline void chipcHw_setUsbDevice(void)
 static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
                                    chipcHw_OPTYPE_e type, int mode)
 {
-       volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
-       volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
+       uint32_t __iomem *pPLLReg = NULL;
+       uint32_t __iomem *pClockCtrl = NULL;
 
        switch (clock) {
        case chipcHw_CLOCK_DDR:
@@ -1071,7 +1074,7 @@ static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock)
 /****************************************************************************/
 static inline int chipcHw_isSoftwareStrapsEnable(void)
 {
-       return pChipcHw->SoftStraps & 0x00000001;
+       return readl(&pChipcHw->SoftStraps) & 0x00000001;
 }
 
 /****************************************************************************/
@@ -1138,7 +1141,7 @@ static inline void chipcHw_pll2TestDisable(void)
 /****************************************************************************/
 static inline int chipcHw_isPllTestEnable(void)
 {
-       return pChipcHw->PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
+       return readl(&pChipcHw->PLLConfig) & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
 }
 
 /****************************************************************************/
@@ -1147,7 +1150,7 @@ static inline int chipcHw_isPllTestEnable(void)
 /****************************************************************************/
 static inline int chipcHw_isPll2TestEnable(void)
 {
-       return pChipcHw->PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
+       return readl(&pChipcHw->PLLConfig2) & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
 }
 
 /****************************************************************************/
@@ -1183,8 +1186,8 @@ static inline void chipcHw_pll2TestSelect(uint32_t val)
 /****************************************************************************/
 static inline uint8_t chipcHw_getPllTestSelected(void)
 {
-       return (uint8_t) ((pChipcHw->
-                          PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
+       return (uint8_t) ((readl(&pChipcHw->
+                          PLLConfig) & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
                          >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
 }
 
@@ -1194,8 +1197,8 @@ static inline uint8_t chipcHw_getPllTestSelected(void)
 /****************************************************************************/
 static inline uint8_t chipcHw_getPll2TestSelected(void)
 {
-       return (uint8_t) ((pChipcHw->
-                          PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
+       return (uint8_t) ((readl(&pChipcHw->
+                          PLLConfig2) & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
                          >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
 }
 
@@ -1208,7 +1211,8 @@ static inline uint8_t chipcHw_getPll2TestSelected(void)
 static inline void chipcHw_pll1Disable(void)
 {
        REG_LOCAL_IRQ_SAVE;
-       pChipcHw->PLLConfig |= chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+       writel(readl(&pChipcHw->PLLConfig) | chipcHw_REG_PLL_CONFIG_POWER_DOWN,
+               &pChipcHw->PLLConfig);
        REG_LOCAL_IRQ_RESTORE;
 }
 
@@ -1221,7 +1225,8 @@ static inline void chipcHw_pll1Disable(void)
 static inline void chipcHw_pll2Disable(void)
 {
        REG_LOCAL_IRQ_SAVE;
-       pChipcHw->PLLConfig2 |= chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+       writel(readl(&pChipcHw->PLLConfig2) | chipcHw_REG_PLL_CONFIG_POWER_DOWN,
+               &pChipcHw->PLLConfig2);
        REG_LOCAL_IRQ_RESTORE;
 }
 
@@ -1233,7 +1238,8 @@ static inline void chipcHw_pll2Disable(void)
 static inline void chipcHw_ddrPhaseAlignInterruptEnable(void)
 {
        REG_LOCAL_IRQ_SAVE;
-       pChipcHw->Spare1 |= chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE;
+       writel(readl(&pChipcHw->Spare1) | chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE,
+               &pChipcHw->Spare1);
        REG_LOCAL_IRQ_RESTORE;
 }
 
@@ -1245,7 +1251,8 @@ static inline void chipcHw_ddrPhaseAlignInterruptEnable(void)
 static inline void chipcHw_ddrPhaseAlignInterruptDisable(void)
 {
        REG_LOCAL_IRQ_SAVE;
-       pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE;
+       writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE,
+               &pChipcHw->Spare1);
        REG_LOCAL_IRQ_RESTORE;
 }
 
@@ -1333,7 +1340,8 @@ static inline void chipcHw_ddrHwPhaseAlignDisable(void)
 static inline void chipcHw_vpmSwPhaseAlignEnable(void)
 {
        REG_LOCAL_IRQ_SAVE;
-       pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE;
+       writel(readl(&pChipcHw->VPMPhaseCtrl1) | chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE,
+                       &pChipcHw->VPMPhaseCtrl1);
        REG_LOCAL_IRQ_RESTORE;
 }
 
@@ -1372,7 +1380,8 @@ static inline void chipcHw_vpmHwPhaseAlignEnable(void)
 static inline void chipcHw_vpmHwPhaseAlignDisable(void)
 {
        REG_LOCAL_IRQ_SAVE;
-       pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE;
+       writel(readl(&pChipcHw->VPMPhaseCtrl1) & ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE,
+               &pChipcHw->VPMPhaseCtrl1);
        REG_LOCAL_IRQ_RESTORE;
 }
 
@@ -1474,8 +1483,8 @@ chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin)
 /****************************************************************************/
 static inline uint32_t chipcHw_isDdrHwPhaseAligned(void)
 {
-       return (pChipcHw->
-               PhaseAlignStatus & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0;
+       return (readl(&pChipcHw->
+               PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0;
 }
 
 /****************************************************************************/
@@ -1488,8 +1497,8 @@ static inline uint32_t chipcHw_isDdrHwPhaseAligned(void)
 /****************************************************************************/
 static inline uint32_t chipcHw_isVpmHwPhaseAligned(void)
 {
-       return (pChipcHw->
-               PhaseAlignStatus & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0;
+       return (readl(&pChipcHw->
+               PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0;
 }
 
 /****************************************************************************/
@@ -1500,8 +1509,8 @@ static inline uint32_t chipcHw_isVpmHwPhaseAligned(void)
 /****************************************************************************/
 static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void)
 {
-       return (pChipcHw->
-               PhaseAlignStatus & chipcHw_REG_DDR_PHASE_STATUS_MASK) >>
+       return (readl(&pChipcHw->
+               PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_STATUS_MASK) >>
            chipcHw_REG_DDR_PHASE_STATUS_SHIFT;
 }
 
@@ -1513,8 +1522,8 @@ static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void)
 /****************************************************************************/
 static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void)
 {
-       return (pChipcHw->
-               PhaseAlignStatus & chipcHw_REG_VPM_PHASE_STATUS_MASK) >>
+       return (readl(&pChipcHw->
+               PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_STATUS_MASK) >>
            chipcHw_REG_VPM_PHASE_STATUS_SHIFT;
 }
 
@@ -1526,8 +1535,8 @@ static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void)
 /****************************************************************************/
 static inline uint32_t chipcHw_getDdrPhaseControl(void)
 {
-       return (pChipcHw->
-               PhaseAlignStatus & chipcHw_REG_DDR_PHASE_CTRL_MASK) >>
+       return (readl(&pChipcHw->
+               PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_CTRL_MASK) >>
            chipcHw_REG_DDR_PHASE_CTRL_SHIFT;
 }
 
@@ -1539,8 +1548,8 @@ static inline uint32_t chipcHw_getDdrPhaseControl(void)
 /****************************************************************************/
 static inline uint32_t chipcHw_getVpmPhaseControl(void)
 {
-       return (pChipcHw->
-               PhaseAlignStatus & chipcHw_REG_VPM_PHASE_CTRL_MASK) >>
+       return (readl(&pChipcHw->
+               PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_CTRL_MASK) >>
            chipcHw_REG_VPM_PHASE_CTRL_SHIFT;
 }
 
index 76d7531d1e1b2d9e851d1ba59b8ab06dece21268..26f5d0e4e1dd7f84214f1a0273c57d7168ab5b8b 100644 (file)
@@ -131,8 +131,8 @@ typedef struct {
        uint32_t MiscInput_0_15;        /* Input type for MISC 0 - 16 */
 } chipcHw_REG_t;
 
-#define pChipcHw  ((volatile chipcHw_REG_t *) chipcHw_BASE_ADDRESS)
-#define pChipcPhysical  ((volatile chipcHw_REG_t *) MM_ADDR_IO_CHIPC)
+#define pChipcHw  ((chipcHw_REG_t __iomem *) chipcHw_BASE_ADDRESS)
+#define pChipcPhysical  (MM_ADDR_IO_CHIPC)
 
 #define chipcHw_REG_CHIPID_BASE_MASK                    0xFFFFF000
 #define chipcHw_REG_CHIPID_BASE_SHIFT                   12
index cabb7dab42ba7e9dc0fc2ffefef7b830c682583e..39da2c1fdafb813cab8bf213dfedca717de683fa 100644 (file)
@@ -416,7 +416,7 @@ extern "C" {
        } ddrcReg_PHY_ADDR_CTL_REG_t;
 
 #define ddrcReg_PHY_ADDR_CTL_REG_OFFSET                 0x0400
-#define ddrcReg_PHY_ADDR_CTL_REGP                       ((volatile ddrcReg_PHY_ADDR_CTL_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET))
+#define ddrcReg_PHY_ADDR_CTL_REGP                       ((volatile ddrcReg_PHY_ADDR_CTL_REG_t __iomem*) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET))
 
 /* @todo These SS definitions are duplicates of ones below */
 
index bde7faa49e7780afa3acfa90b908a8c62b393857..9dc90f46a84d919ec122af0bb8021d6d3066c73b 100644 (file)
@@ -23,7 +23,7 @@
 #ifndef _DMACHW_H
 #define _DMACHW_H
 
-#include <stddef.h>
+#include <linux/stddef.h>
 
 #include <linux/types.h>
 #include <mach/csp/dmacHw_reg.h>
index 1be9556ba14eeb597cdb1bfa67338c54d5bf5e19..7cd0aafa6f6e65697507862a359d9ca8022973ad 100644 (file)
@@ -121,75 +121,75 @@ typedef struct {
 } dmacHw_MISC_t;
 
 /* Base registers */
-#define dmacHw_0_MODULE_BASE_ADDR        (char *) MM_IO_BASE_DMA0      /* DMAC 0 module's base address */
-#define dmacHw_1_MODULE_BASE_ADDR        (char *) MM_IO_BASE_DMA1      /* DMAC 1 module's base address */
+#define dmacHw_0_MODULE_BASE_ADDR        (char __iomem*) MM_IO_BASE_DMA0       /* DMAC 0 module's base address */
+#define dmacHw_1_MODULE_BASE_ADDR        (char __iomem*) MM_IO_BASE_DMA1       /* DMAC 1 module's base address */
 
 extern uint32_t dmaChannelCount_0;
 extern uint32_t dmaChannelCount_1;
 
 /* Define channel specific registers */
-#define dmacHw_CHAN_BASE(module, chan)          ((dmacHw_CH_REG_t *) ((char *)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t))))
+#define dmacHw_CHAN_BASE(module, chan)          ((dmacHw_CH_REG_t __iomem*) ((char __iomem*)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t))))
 
 /* Raw interrupt status registers */
-#define dmacHw_REG_INT_RAW_BASE(module)         ((char *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0)))
-#define dmacHw_REG_INT_RAW_TRAN(module)         (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo)
-#define dmacHw_REG_INT_RAW_BLOCK(module)        (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo)
-#define dmacHw_REG_INT_RAW_STRAN(module)        (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo)
-#define dmacHw_REG_INT_RAW_DTRAN(module)        (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo)
-#define dmacHw_REG_INT_RAW_ERROR(module)        (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo)
+#define dmacHw_REG_INT_RAW_BASE(module)         ((char __iomem *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0)))
+#define dmacHw_REG_INT_RAW_TRAN(module)         (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo)
+#define dmacHw_REG_INT_RAW_BLOCK(module)        (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo)
+#define dmacHw_REG_INT_RAW_STRAN(module)        (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo)
+#define dmacHw_REG_INT_RAW_DTRAN(module)        (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo)
+#define dmacHw_REG_INT_RAW_ERROR(module)        (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo)
 
 /* Interrupt status registers */
-#define dmacHw_REG_INT_STAT_BASE(module)        ((char *)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t)))
-#define dmacHw_REG_INT_STAT_TRAN(module)        (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo)
-#define dmacHw_REG_INT_STAT_BLOCK(module)       (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo)
-#define dmacHw_REG_INT_STAT_STRAN(module)       (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo)
-#define dmacHw_REG_INT_STAT_DTRAN(module)       (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo)
-#define dmacHw_REG_INT_STAT_ERROR(module)       (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo)
+#define dmacHw_REG_INT_STAT_BASE(module)        ((char __iomem*)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t)))
+#define dmacHw_REG_INT_STAT_TRAN(module)        (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo)
+#define dmacHw_REG_INT_STAT_BLOCK(module)       (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo)
+#define dmacHw_REG_INT_STAT_STRAN(module)       (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo)
+#define dmacHw_REG_INT_STAT_DTRAN(module)       (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo)
+#define dmacHw_REG_INT_STAT_ERROR(module)       (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo)
 
 /* Interrupt status registers */
-#define dmacHw_REG_INT_MASK_BASE(module)        ((char *)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t)))
-#define dmacHw_REG_INT_MASK_TRAN(module)        (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo)
-#define dmacHw_REG_INT_MASK_BLOCK(module)       (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo)
-#define dmacHw_REG_INT_MASK_STRAN(module)       (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo)
-#define dmacHw_REG_INT_MASK_DTRAN(module)       (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo)
-#define dmacHw_REG_INT_MASK_ERROR(module)       (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo)
+#define dmacHw_REG_INT_MASK_BASE(module)        ((char __iomem*)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t)))
+#define dmacHw_REG_INT_MASK_TRAN(module)        (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo)
+#define dmacHw_REG_INT_MASK_BLOCK(module)       (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo)
+#define dmacHw_REG_INT_MASK_STRAN(module)       (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo)
+#define dmacHw_REG_INT_MASK_DTRAN(module)       (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo)
+#define dmacHw_REG_INT_MASK_ERROR(module)       (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo)
 
 /* Interrupt clear registers */
-#define dmacHw_REG_INT_CLEAR_BASE(module)       ((char *)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t)))
-#define dmacHw_REG_INT_CLEAR_TRAN(module)       (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo)
-#define dmacHw_REG_INT_CLEAR_BLOCK(module)      (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo)
-#define dmacHw_REG_INT_CLEAR_STRAN(module)      (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo)
-#define dmacHw_REG_INT_CLEAR_DTRAN(module)      (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo)
-#define dmacHw_REG_INT_CLEAR_ERROR(module)      (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo)
-#define dmacHw_REG_INT_STATUS(module)           (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo)
+#define dmacHw_REG_INT_CLEAR_BASE(module)       ((char __iomem*)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t)))
+#define dmacHw_REG_INT_CLEAR_TRAN(module)       (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo)
+#define dmacHw_REG_INT_CLEAR_BLOCK(module)      (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo)
+#define dmacHw_REG_INT_CLEAR_STRAN(module)      (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo)
+#define dmacHw_REG_INT_CLEAR_DTRAN(module)      (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo)
+#define dmacHw_REG_INT_CLEAR_ERROR(module)      (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo)
+#define dmacHw_REG_INT_STATUS(module)           (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo)
 
 /* Software handshaking registers */
-#define dmacHw_REG_SW_HS_BASE(module)           ((char *)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t)))
-#define dmacHw_REG_SW_HS_SRC_REQ(module)        (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo)
-#define dmacHw_REG_SW_HS_DST_REQ(module)        (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo)
-#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module)    (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo)
-#define dmacHw_REG_SW_HS_DST_SGL_REQ(module)    (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo)
-#define dmacHw_REG_SW_HS_SRC_LST_REQ(module)    (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo)
-#define dmacHw_REG_SW_HS_DST_LST_REQ(module)    (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo)
+#define dmacHw_REG_SW_HS_BASE(module)           ((char __iomem*)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t)))
+#define dmacHw_REG_SW_HS_SRC_REQ(module)        (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo)
+#define dmacHw_REG_SW_HS_DST_REQ(module)        (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo)
+#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module)    (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo)
+#define dmacHw_REG_SW_HS_DST_SGL_REQ(module)    (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo)
+#define dmacHw_REG_SW_HS_SRC_LST_REQ(module)    (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo)
+#define dmacHw_REG_SW_HS_DST_LST_REQ(module)    (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo)
 
 /* Miscellaneous registers */
-#define dmacHw_REG_MISC_BASE(module)            ((char *)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t)))
-#define dmacHw_REG_MISC_CFG(module)             (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo)
-#define dmacHw_REG_MISC_CH_ENABLE(module)       (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo)
-#define dmacHw_REG_MISC_ID(module)              (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo)
-#define dmacHw_REG_MISC_TEST(module)            (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo)
-#define dmacHw_REG_MISC_COMP_PARAM1_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo)
-#define dmacHw_REG_MISC_COMP_PARAM1_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi)
-#define dmacHw_REG_MISC_COMP_PARAM2_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo)
-#define dmacHw_REG_MISC_COMP_PARAM2_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi)
-#define dmacHw_REG_MISC_COMP_PARAM3_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo)
-#define dmacHw_REG_MISC_COMP_PARAM3_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi)
-#define dmacHw_REG_MISC_COMP_PARAM4_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo)
-#define dmacHw_REG_MISC_COMP_PARAM4_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi)
-#define dmacHw_REG_MISC_COMP_PARAM5_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo)
-#define dmacHw_REG_MISC_COMP_PARAM5_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi)
-#define dmacHw_REG_MISC_COMP_PARAM6_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo)
-#define dmacHw_REG_MISC_COMP_PARAM6_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi)
+#define dmacHw_REG_MISC_BASE(module)            ((char __iomem*)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t)))
+#define dmacHw_REG_MISC_CFG(module)             (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo)
+#define dmacHw_REG_MISC_CH_ENABLE(module)       (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo)
+#define dmacHw_REG_MISC_ID(module)              (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo)
+#define dmacHw_REG_MISC_TEST(module)            (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo)
+#define dmacHw_REG_MISC_COMP_PARAM1_LO(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo)
+#define dmacHw_REG_MISC_COMP_PARAM1_HI(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi)
+#define dmacHw_REG_MISC_COMP_PARAM2_LO(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo)
+#define dmacHw_REG_MISC_COMP_PARAM2_HI(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi)
+#define dmacHw_REG_MISC_COMP_PARAM3_LO(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo)
+#define dmacHw_REG_MISC_COMP_PARAM3_HI(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi)
+#define dmacHw_REG_MISC_COMP_PARAM4_LO(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo)
+#define dmacHw_REG_MISC_COMP_PARAM4_HI(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi)
+#define dmacHw_REG_MISC_COMP_PARAM5_LO(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo)
+#define dmacHw_REG_MISC_COMP_PARAM5_HI(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi)
+#define dmacHw_REG_MISC_COMP_PARAM6_LO(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo)
+#define dmacHw_REG_MISC_COMP_PARAM6_HI(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi)
 
 /* Channel control registers */
 #define dmacHw_REG_SAR(module, chan)            (dmacHw_CHAN_BASE((module), (chan))->ChannelSar.lo)
index 49403d5725e8f8eec0eaf07816a171bb539d2426..f59db25b5632a601c563d63ee11bb536e83604ef 100644 (file)
@@ -37,9 +37,9 @@
 #define INTCHW_NUM_INTC           3
 
 /* Defines for interrupt controllers. This simplifies and cleans up the function calls. */
-#define INTCHW_INTC0    ((void *)MM_IO_BASE_INTC0)
-#define INTCHW_INTC1    ((void *)MM_IO_BASE_INTC1)
-#define INTCHW_SINTC    ((void *)MM_IO_BASE_SINTC)
+#define INTCHW_INTC0    (MM_IO_BASE_INTC0)
+#define INTCHW_INTC1    (MM_IO_BASE_INTC1)
+#define INTCHW_SINTC    (MM_IO_BASE_SINTC)
 
 /* INTC0 - interrupt controller 0 */
 #define INTCHW_INTC0_PIF_BITNUM           31   /* Peripheral interface interrupt */
 /* ---- Public Variable Externs ------------------------------------------ */
 /* ---- Public Function Prototypes --------------------------------------- */
 /* Clear one or more IRQ interrupts. */
-static inline void intcHw_irq_disable(void *basep, uint32_t mask)
+static inline void intcHw_irq_disable(void __iomem *basep, uint32_t mask)
 {
-       __REG32(basep + INTCHW_INTENCLEAR) = mask;
+       writel(mask, basep + INTCHW_INTENCLEAR);
 }
 
 /* Enables one or more IRQ interrupts. */
-static inline void intcHw_irq_enable(void *basep, uint32_t mask)
+static inline void intcHw_irq_enable(void __iomem *basep, uint32_t mask)
 {
-       __REG32(basep + INTCHW_INTENABLE) = mask;
+       writel(mask, basep + INTCHW_INTENABLE);
 }
 
 #endif /* _INTCHW_REG_H */
index dbc98ddaeb676c19c046e8194e5c91917bb2026a..47450c23685a9b64826b167ce41210d3e3595d55 100644 (file)
@@ -49,7 +49,7 @@
 #ifdef __ASSEMBLY__
 #define MM_IO_PHYS_TO_VIRT(phys)       (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF))
 #else
-#define MM_IO_PHYS_TO_VIRT(phys)       (((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \
+#define MM_IO_PHYS_TO_VIRT(phys)       (void __iomem *)(((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \
                        (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF)))
 #endif
 #endif
@@ -60,8 +60,8 @@
 #ifdef __ASSEMBLY__
 #define MM_IO_VIRT_TO_PHYS(virt)       ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF))
 #else
-#define MM_IO_VIRT_TO_PHYS(virt)       (((virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \
-                       ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF)))
+#define MM_IO_VIRT_TO_PHYS(virt)       (((unsigned long)(virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \
+                       ((((unsigned long)(virt) & 0x0F000000) << 4) | ((unsigned long)(virt) & 0xFFFFFF)))
 #endif
 #endif
 
index 026eb0b3ba2ddfbd8d278b20e01f45376aabe433..d9cbdca8cd252689c1f7cfeb290374eff5559364 100644 (file)
 /* ---- Include Files ---------------------------------------------------- */
 
 #include <linux/types.h>
+#include <linux/io.h>
 
 /* ---- Public Constants and Types --------------------------------------- */
 
-#define __REG32(x)      (*((volatile uint32_t *)(x)))
-#define __REG16(x)      (*((volatile uint16_t *)(x)))
-#define __REG8(x)       (*((volatile uint8_t *) (x)))
+#define __REG32(x)      (*((volatile uint32_t __iomem *)(x)))
+#define __REG16(x)      (*((volatile uint16_t __iomem *)(x)))
+#define __REG8(x)       (*((volatile uint8_t __iomem *) (x)))
 
 /* Macros used to define a sequence of reserved registers. The start / end */
 /* are byte offsets in the particular register definition, with the "end" */
 
 #endif
 
-static inline void reg32_modify_and(volatile uint32_t *reg, uint32_t value)
+static inline void reg32_modify_and(volatile uint32_t __iomem *reg, uint32_t value)
 {
        REG_LOCAL_IRQ_SAVE;
-       *reg &= value;
+       __raw_writel(__raw_readl(reg) & value, reg);
        REG_LOCAL_IRQ_RESTORE;
 }
 
-static inline void reg32_modify_or(volatile uint32_t *reg, uint32_t value)
+static inline void reg32_modify_or(volatile uint32_t __iomem *reg, uint32_t value)
 {
        REG_LOCAL_IRQ_SAVE;
-       *reg |= value;
+       __raw_writel(__raw_readl(reg) | value, reg);
        REG_LOCAL_IRQ_RESTORE;
 }
 
-static inline void reg32_modify_mask(volatile uint32_t *reg, uint32_t mask,
+static inline void reg32_modify_mask(volatile uint32_t __iomem *reg, uint32_t mask,
                                     uint32_t value)
 {
        REG_LOCAL_IRQ_SAVE;
-       *reg = (*reg & mask) | value;
+       __raw_writel((__raw_readl(reg) & mask) | value, reg);
        REG_LOCAL_IRQ_RESTORE;
 }
 
-static inline void reg32_write(volatile uint32_t *reg, uint32_t value)
+static inline void reg32_write(volatile uint32_t __iomem *reg, uint32_t value)
 {
-       *reg = value;
+       __raw_writel(value, reg);
 }
 
 #endif /* CSP_REG_H */
index 9cd6a032ab716394dba50986a3a72b2da55f7bd4..55d3cd4fd1e736d3c649d4434be566ac082db17b 100644 (file)
@@ -34,7 +34,7 @@
 /****************************************************************************/
 static inline void secHw_setSecure(uint32_t mask       /*  mask of type secHw_BLK_MASK_XXXXXX */
     ) {
-       secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
+       secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC;
 
        if (mask & 0x0000FFFF) {
                regp->reg[secHw_IDX_LS].setSecure = mask & 0x0000FFFF;
@@ -53,13 +53,13 @@ static inline void secHw_setSecure(uint32_t mask    /*  mask of type secHw_BLK_MASK
 /****************************************************************************/
 static inline void secHw_setUnsecure(uint32_t mask     /*  mask of type secHw_BLK_MASK_XXXXXX */
     ) {
-       secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
+       secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC;
 
        if (mask & 0x0000FFFF) {
-               regp->reg[secHw_IDX_LS].setUnsecure = mask & 0x0000FFFF;
+               writel(mask & 0x0000FFFF, &regp->reg[secHw_IDX_LS].setUnsecure);
        }
        if (mask & 0xFFFF0000) {
-               regp->reg[secHw_IDX_MS].setUnsecure = mask >> 16;
+               writel(mask >> 16, &regp->reg[secHw_IDX_MS].setUnsecure);
        }
 }
 
@@ -71,7 +71,7 @@ static inline void secHw_setUnsecure(uint32_t mask    /*  mask of type secHw_BLK_MA
 /****************************************************************************/
 static inline uint32_t secHw_getStatus(void)
 {
-       secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
+       secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC;
 
        return (regp->reg[1].status << 16) + regp->reg[0].status;
 }
index 041a68eb66610b81b10ab2073540a02d4f6f2398..56dd9de7d83f4118ffe4dcb9da87e137a8481172 100644 (file)
 #define REG_UMI_BCH_ERR_LOC_WORD              0x00000018
 /* location within a page (512 byte) */
 #define REG_UMI_BCH_ERR_LOC_PAGE              0x00001FE0
-#define REG_UMI_BCH_ERR_LOC_ADDR(index)     (__REG32(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16))
+#define REG_UMI_BCH_ERR_LOC_ADDR(index)     (readl(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16))
 #endif
index 1adec78ec940ef7a620a23e88752a1f6c0c2d642..33824a81cac4ce28cd68890ec34e638bc35b4e6e 100644 (file)
 #include <mach/hardware.h>
 #include <mach/csp/mm_io.h>
 
-#define IO_DESC(va, sz) { .virtual = va, \
+#define IO_DESC(va, sz) { .virtual = (unsigned long)va, \
        .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
        .length = sz, \
        .type = MT_DEVICE }
 
-#define MEM_DESC(va, sz) { .virtual = va, \
+#define MEM_DESC(va, sz) { .virtual = (unsigned long)va, \
        .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
        .length = sz, \
        .type = MT_MEMORY }
index 6908cdde3065e73b24509e8c9d32865f5befb1d9..55e7799f4bf37176ca4ad045066088c870b10b24 100644 (file)
@@ -249,20 +249,20 @@ static int nand_dev_ready(struct mtd_info *mtd)
 int bcm_umi_nand_inithw(void)
 {
        /* Configure nand timing parameters */
-       REG_UMI_NAND_TCR &= ~0x7ffff;
-       REG_UMI_NAND_TCR |= HW_CFG_NAND_TCR;
+       writel(readl(&REG_UMI_NAND_TCR) & ~0x7ffff, &REG_UMI_NAND_TCR);
+       writel(readl(&REG_UMI_NAND_TCR) | HW_CFG_NAND_TCR, &REG_UMI_NAND_TCR);
 
 #if !defined(CONFIG_MTD_NAND_BCM_UMI_HWCS)
        /* enable software control of CS */
-       REG_UMI_NAND_TCR |= REG_UMI_NAND_TCR_CS_SWCTRL;
+       writel(readl(&REG_UMI_NAND_TCR) | REG_UMI_NAND_TCR_CS_SWCTRL, &REG_UMI_NAND_TCR);
 #endif
 
        /* keep NAND chip select asserted */
-       REG_UMI_NAND_RCSR |= REG_UMI_NAND_RCSR_CS_ASSERTED;
+       writel(readl(&REG_UMI_NAND_RCSR) | REG_UMI_NAND_RCSR_CS_ASSERTED, &REG_UMI_NAND_RCSR);
 
-       REG_UMI_NAND_TCR &= ~REG_UMI_NAND_TCR_WORD16;
+       writel(readl(&REG_UMI_NAND_TCR) & ~REG_UMI_NAND_TCR_WORD16, &REG_UMI_NAND_TCR);
        /* enable writes to flash */
-       REG_UMI_MMD_ICR |= REG_UMI_MMD_ICR_FLASH_WP;
+       writel(readl(&REG_UMI_MMD_ICR) | REG_UMI_MMD_ICR_FLASH_WP, &REG_UMI_MMD_ICR);
 
        writel(NAND_CMD_RESET, bcm_umi_io_base + REG_NAND_CMD_OFFSET);
        nand_bcm_umi_wait_till_ready();
index a158d5dd9a02ffbff7d04af4c008268d95bf6e3d..d90186684db85ff18a99fbbb95f93a466824e37b 100644 (file)
@@ -48,7 +48,7 @@ int nand_bcm_umi_bch_correct_page(uint8_t *datap, uint8_t *readEccData,
 /* Check in device is ready */
 static inline int nand_bcm_umi_dev_ready(void)
 {
-       return REG_UMI_NAND_RCSR & REG_UMI_NAND_RCSR_RDY;
+       return readl(&REG_UMI_NAND_RCSR) & REG_UMI_NAND_RCSR_RDY;
 }
 
 /* Wait until device is ready */
@@ -62,10 +62,11 @@ static inline void nand_bcm_umi_wait_till_ready(void)
 static inline void nand_bcm_umi_hamming_enable_hwecc(void)
 {
        /* disable and reset ECC, 512 byte page */
-       REG_UMI_NAND_ECC_CSR &= ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE |
-               REG_UMI_NAND_ECC_CSR_256BYTE);
+       writel(readl(&REG_UMI_NAND_ECC_CSR) & ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE |
+               REG_UMI_NAND_ECC_CSR_256BYTE), &REG_UMI_NAND_ECC_CSR);
        /* enable ECC */
-       REG_UMI_NAND_ECC_CSR |= REG_UMI_NAND_ECC_CSR_ECC_ENABLE;
+       writel(readl(&REG_UMI_NAND_ECC_CSR) | REG_UMI_NAND_ECC_CSR_ECC_ENABLE,
+               &REG_UMI_NAND_ECC_CSR);
 }
 
 #if NAND_ECC_BCH
@@ -76,18 +77,18 @@ static inline void nand_bcm_umi_hamming_enable_hwecc(void)
 static inline void nand_bcm_umi_bch_enable_read_hwecc(void)
 {
        /* disable and reset ECC */
-       REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID;
+       writel(REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID, &REG_UMI_BCH_CTRL_STATUS);
        /* Turn on ECC */
-       REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN;
+       writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN, &REG_UMI_BCH_CTRL_STATUS);
 }
 
 /* Enable BCH Write ECC */
 static inline void nand_bcm_umi_bch_enable_write_hwecc(void)
 {
        /* disable and reset ECC */
-       REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID;
+       writel(REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID, &REG_UMI_BCH_CTRL_STATUS);
        /* Turn on ECC */
-       REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN;
+       writel(REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN, &REG_UMI_BCH_CTRL_STATUS);
 }
 
 /* Config number of BCH ECC bytes */
@@ -99,9 +100,9 @@ static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes)
        uint32_t numBits = numEccBytes * 8;
 
        /* disable and reset ECC */
-       REG_UMI_BCH_CTRL_STATUS =
-           REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID |
-           REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID;
+       writel(REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID |
+              REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID,
+              &REG_UMI_BCH_CTRL_STATUS);
 
        /* Every correctible bit requires 13 ECC bits */
        tValue = (uint32_t) (numBits / ECC_BITS_PER_CORRECTABLE_BIT);
@@ -113,23 +114,21 @@ static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes)
        kValue = nValue - (tValue * ECC_BITS_PER_CORRECTABLE_BIT);
 
        /* Write the settings */
-       REG_UMI_BCH_N = nValue;
-       REG_UMI_BCH_T = tValue;
-       REG_UMI_BCH_K = kValue;
+       writel(nValue, &REG_UMI_BCH_N);
+       writel(tValue, &REG_UMI_BCH_T);
+       writel(kValue, &REG_UMI_BCH_K);
 }
 
 /* Pause during ECC read calculation to skip bytes in OOB */
 static inline void nand_bcm_umi_bch_pause_read_ecc_calc(void)
 {
-       REG_UMI_BCH_CTRL_STATUS =
-           REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN |
-           REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC;
+       writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN | REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC, &REG_UMI_BCH_CTRL_STATUS);
 }
 
 /* Resume during ECC read calculation after skipping bytes in OOB */
 static inline void nand_bcm_umi_bch_resume_read_ecc_calc(void)
 {
-       REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN;
+       writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN, &REG_UMI_BCH_CTRL_STATUS);
 }
 
 /* Poll read ECC calc to check when hardware completes */
@@ -139,7 +138,7 @@ static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void)
 
        do {
                /* wait for ECC to be valid */
-               regVal = REG_UMI_BCH_CTRL_STATUS;
+               regVal = readl(&REG_UMI_BCH_CTRL_STATUS);
        } while ((regVal & REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID) == 0);
 
        return regVal;
@@ -149,7 +148,7 @@ static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void)
 static inline void nand_bcm_umi_bch_poll_write_ecc_calc(void)
 {
        /* wait for ECC to be valid */
-       while ((REG_UMI_BCH_CTRL_STATUS & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID)
+       while ((readl(&REG_UMI_BCH_CTRL_STATUS) & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID)
               == 0)
                ;
 }
@@ -170,9 +169,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
        if (pageSize != NAND_DATA_ACCESS_SIZE) {
                /* skip BI */
 #if defined(__KERNEL__) && !defined(STANDALONE)
-               *oobp++ = REG_NAND_DATA8;
+               *oobp++ = readb(&REG_NAND_DATA8);
 #else
-               REG_NAND_DATA8;
+               readb(&REG_NAND_DATA8);
 #endif
                numToRead--;
        }
@@ -180,9 +179,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
        while (numToRead > numEccBytes) {
                /* skip free oob region */
 #if defined(__KERNEL__) && !defined(STANDALONE)
-               *oobp++ = REG_NAND_DATA8;
+               *oobp++ = readb(&REG_NAND_DATA8);
 #else
-               REG_NAND_DATA8;
+               readb(&REG_NAND_DATA8);
 #endif
                numToRead--;
        }
@@ -193,11 +192,11 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
 
                while (numToRead > 11) {
 #if defined(__KERNEL__) && !defined(STANDALONE)
-                       *oobp = REG_NAND_DATA8;
+                       *oobp = readb(&REG_NAND_DATA8);
                        eccCalc[eccPos++] = *oobp;
                        oobp++;
 #else
-                       eccCalc[eccPos++] = REG_NAND_DATA8;
+                       eccCalc[eccPos++] = readb(&REG_NAND_DATA8);
 #endif
                        numToRead--;
                }
@@ -207,9 +206,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
                if (numToRead == 11) {
                        /* read BI */
 #if defined(__KERNEL__) && !defined(STANDALONE)
-                       *oobp++ = REG_NAND_DATA8;
+                       *oobp++ = readb(&REG_NAND_DATA8);
 #else
-                       REG_NAND_DATA8;
+                       readb(&REG_NAND_DATA8);
 #endif
                        numToRead--;
                }
@@ -219,11 +218,11 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
        nand_bcm_umi_bch_resume_read_ecc_calc();
        while (numToRead) {
 #if defined(__KERNEL__) && !defined(STANDALONE)
-               *oobp = REG_NAND_DATA8;
+               *oobp = readb(&REG_NAND_DATA8);
                eccCalc[eccPos++] = *oobp;
                oobp++;
 #else
-               eccCalc[eccPos++] = REG_NAND_DATA8;
+               eccCalc[eccPos++] = readb(&REG_NAND_DATA8);
 #endif
                numToRead--;
        }
@@ -255,7 +254,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
        if (pageSize == NAND_DATA_ACCESS_SIZE) {
                /* Now fill in the ECC bytes */
                if (numEccBytes >= 13)
-                       eccVal = REG_UMI_BCH_WR_ECC_3;
+                       eccVal = readl(&REG_UMI_BCH_WR_ECC_3);
 
                /* Usually we skip CM in oob[0,1] */
                NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[0],
@@ -268,7 +267,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
                        eccVal & 0xff); /* ECC 12 */
 
                if (numEccBytes >= 9)
-                       eccVal = REG_UMI_BCH_WR_ECC_2;
+                       eccVal = readl(&REG_UMI_BCH_WR_ECC_2);
 
                NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[3],
                        (eccVal >> 24) & 0xff); /* ECC11 */
@@ -281,7 +280,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
 
                /* Now fill in the ECC bytes */
                if (numEccBytes >= 13)
-                       eccVal = REG_UMI_BCH_WR_ECC_3;
+                       eccVal = readl(&REG_UMI_BCH_WR_ECC_3);
 
                /* Usually skip CM in oob[1,2] */
                NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[1],
@@ -294,7 +293,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
                        eccVal & 0xff); /* ECC12 */
 
                if (numEccBytes >= 9)
-                       eccVal = REG_UMI_BCH_WR_ECC_2;
+                       eccVal = readl(&REG_UMI_BCH_WR_ECC_2);
 
                NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[4],
                        (eccVal >> 24) & 0xff); /* ECC11 */
@@ -309,7 +308,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
                eccVal & 0xff); /* ECC8 */
 
        if (numEccBytes >= 5)
-               eccVal = REG_UMI_BCH_WR_ECC_1;
+               eccVal = readl(&REG_UMI_BCH_WR_ECC_1);
 
        NAND_BCM_UMI_ECC_WRITE(numEccBytes, 8, &oobp[8],
                (eccVal >> 24) & 0xff); /* ECC7 */
@@ -321,7 +320,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
                eccVal & 0xff); /* ECC4 */
 
        if (numEccBytes >= 1)
-               eccVal = REG_UMI_BCH_WR_ECC_0;
+               eccVal = readl(&REG_UMI_BCH_WR_ECC_0);
 
        NAND_BCM_UMI_ECC_WRITE(numEccBytes, 4, &oobp[12],
                (eccVal >> 24) & 0xff); /* ECC3 */