Merge tag 'tegra-for-3.9-soc-ccf-fixes' of git://git.kernel.org/pub/scm/linux/kernel...
authorArnd Bergmann <arnd@arndb.de>
Tue, 19 Feb 2013 21:38:51 +0000 (22:38 +0100)
committerArnd Bergmann <arnd@arndb.de>
Tue, 19 Feb 2013 21:38:51 +0000 (22:38 +0100)
ARM: tegra: common clock framework fixes

A number of small fixes are included to the new Tegra common clock
driver. These are: Missing locking, definition of device tree clock IDs
not matching the binding, a static cleanup, missing initialization of
some UART clocks.

This branch is based on Tegra's previous pull request tegra-for-3.9-dt.
This dependency is caused by the one patch that edits the device tree.
If this causes a problem, I can drop the final two patches in this pull
request for now, and rebase it onto previous tegra-for-3.9-soc-ccf
instead.

* tag 'tegra-for-3.9-soc-ccf-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
  clk: tegra: initialise parent of uart clocks
  ARM: tegra: remove clock-frequency properties from serial nodes
  clk: tegra: fix driver to match DT binding
  clk: tegra: local arrays should be static
  clk: tegra: Add missing spinlock for hclk and pclk
  clk: tegra: Implement locking for super clock
  clk: tegra: fix wrong clock index between se to sata_cold

(applied to next/dt branch rather than next/soc because of the
dependency)

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
arch/arm/boot/dts/tegra20.dtsi
arch/arm/boot/dts/tegra30.dtsi
drivers/clk/tegra/clk-super.c
drivers/clk/tegra/clk-tegra20.c
drivers/clk/tegra/clk-tegra30.c

index cdb8da0b69833f6f3084b5c7a48f7db7a5b80311..9a428931d0429d2befef3d6d3084b7499eeb3a02 100644 (file)
                reg = <0x70006000 0x40>;
                reg-shift = <2>;
                interrupts = <0 36 0x04>;
-               clock-frequency = <216000000>;
                nvidia,dma-request-selector = <&apbdma 8>;
                clocks = <&tegra_car 6>;
                status = "disabled";
                reg = <0x70006040 0x40>;
                reg-shift = <2>;
                interrupts = <0 37 0x04>;
-               clock-frequency = <216000000>;
                nvidia,dma-request-selector = <&apbdma 9>;
                clocks = <&tegra_car 96>;
                status = "disabled";
                reg = <0x70006200 0x100>;
                reg-shift = <2>;
                interrupts = <0 46 0x04>;
-               clock-frequency = <216000000>;
                nvidia,dma-request-selector = <&apbdma 10>;
                clocks = <&tegra_car 55>;
                status = "disabled";
                reg = <0x70006300 0x100>;
                reg-shift = <2>;
                interrupts = <0 90 0x04>;
-               clock-frequency = <216000000>;
                nvidia,dma-request-selector = <&apbdma 19>;
                clocks = <&tegra_car 65>;
                status = "disabled";
                reg = <0x70006400 0x100>;
                reg-shift = <2>;
                interrupts = <0 91 0x04>;
-               clock-frequency = <216000000>;
                nvidia,dma-request-selector = <&apbdma 20>;
                clocks = <&tegra_car 66>;
                status = "disabled";
index 572a45bab93be3c2e150a315cd57f9813bd367e0..767803e1fd55f2d6e75053527e47a26d536e4f77 100644 (file)
                reg = <0x70006000 0x40>;
                reg-shift = <2>;
                interrupts = <0 36 0x04>;
-               clock-frequency = <408000000>;
                nvidia,dma-request-selector = <&apbdma 8>;
                clocks = <&tegra_car 6>;
                status = "disabled";
                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                reg = <0x70006040 0x40>;
                reg-shift = <2>;
-               clock-frequency = <408000000>;
                interrupts = <0 37 0x04>;
                nvidia,dma-request-selector = <&apbdma 9>;
                clocks = <&tegra_car 160>;
                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                reg = <0x70006200 0x100>;
                reg-shift = <2>;
-               clock-frequency = <408000000>;
                interrupts = <0 46 0x04>;
                nvidia,dma-request-selector = <&apbdma 10>;
                clocks = <&tegra_car 55>;
                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                reg = <0x70006300 0x100>;
                reg-shift = <2>;
-               clock-frequency = <408000000>;
                interrupts = <0 90 0x04>;
                nvidia,dma-request-selector = <&apbdma 19>;
                clocks = <&tegra_car 65>;
                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                reg = <0x70006400 0x100>;
                reg-shift = <2>;
-               clock-frequency = <408000000>;
                interrupts = <0 91 0x04>;
                nvidia,dma-request-selector = <&apbdma 20>;
                clocks = <&tegra_car 66>;
index 7ad48a832334c88dff1d7d7059e4763d03525edd..2fd924d38606920ce011cb51edf4adb0ab544720 100644 (file)
@@ -73,7 +73,12 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index)
 {
        struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
        u32 val, state;
+       int err = 0;
        u8 parent_index, shift;
+       unsigned long flags = 0;
+
+       if (mux->lock)
+               spin_lock_irqsave(mux->lock, flags);
 
        val = readl_relaxed(mux->reg);
        state = val & SUPER_STATE_MASK;
@@ -92,8 +97,10 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index)
                                               (index == mux->pllx_index))) {
                parent_index = clk_super_get_parent(hw);
                if ((parent_index == mux->div2_index) ||
-                   (parent_index == mux->pllx_index))
-                       return -EINVAL;
+                   (parent_index == mux->pllx_index)) {
+                       err = -EINVAL;
+                       goto out;
+               }
 
                val ^= SUPER_LP_DIV2_BYPASS;
                writel_relaxed(val, mux->reg);
@@ -107,7 +114,12 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index)
 
        writel_relaxed(val, mux->reg);
        udelay(2);
-       return 0;
+
+out:
+       if (mux->lock)
+               spin_unlock_irqrestore(mux->lock, flags);
+
+       return err;
 }
 
 const struct clk_ops tegra_clk_super_ops = {
index 5d41569883a79534e6c49a40dfd5724635266403..143ce1f899ad74a5ce447652f64bb48c34b39652 100644 (file)
@@ -194,6 +194,7 @@ static void __iomem *clk_base;
 static void __iomem *pmc_base;
 
 static DEFINE_SPINLOCK(pll_div_lock);
+static DEFINE_SPINLOCK(sysrate_lock);
 
 #define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset,        \
                            _clk_num, _regs, _gate_flags, _clk_id)      \
@@ -239,8 +240,8 @@ enum tegra20_clk {
        uartb = 96, vfir, spdif_in, spdif_out, vi, vi_sensor, tvo, cve,
        osc, clk_32k, clk_m, sclk, cclk, hclk, pclk, blink, pll_a, pll_a_out0,
        pll_c, pll_c_out1, pll_d, pll_d_out0, pll_e, pll_m, pll_m_out1,
-       pll_p, pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_u,
-       pll_x, audio, pll_ref, twd, clk_max,
+       pll_p, pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_s, pll_u,
+       pll_x, cop, audio, pll_ref, twd, clk_max,
 };
 
 static struct clk *clks[clk_max];
@@ -768,19 +769,21 @@ static void tegra20_super_clk_init(void)
 
        /* HCLK */
        clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
-                                  clk_base + CLK_SYSTEM_RATE, 4, 2, 0, NULL);
+                                  clk_base + CLK_SYSTEM_RATE, 4, 2, 0,
+                                  &sysrate_lock);
        clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT,
                                clk_base + CLK_SYSTEM_RATE, 7,
-                               CLK_GATE_SET_TO_DISABLE, NULL);
+                               CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
        clk_register_clkdev(clk, "hclk", NULL);
        clks[hclk] = clk;
 
        /* PCLK */
        clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
-                                  clk_base + CLK_SYSTEM_RATE, 0, 2, 0, NULL);
+                                  clk_base + CLK_SYSTEM_RATE, 0, 2, 0,
+                                  &sysrate_lock);
        clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT,
                                clk_base + CLK_SYSTEM_RATE, 3,
-                               CLK_GATE_SET_TO_DISABLE, NULL);
+                               CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
        clk_register_clkdev(clk, "pclk", NULL);
        clks[pclk] = clk;
 
@@ -1251,8 +1254,11 @@ static __initdata struct tegra_clk_init_table init_table[] = {
        {csite, clk_max, 0, 1},
        {emc, clk_max, 0, 1},
        {cclk, clk_max, 0, 1},
-       {uarta, pll_p, 0, 1},
-       {uartd, pll_p, 0, 1},
+       {uarta, pll_p, 0, 0},
+       {uartb, pll_p, 0, 0},
+       {uartc, pll_p, 0, 0},
+       {uartd, pll_p, 0, 0},
+       {uarte, pll_p, 0, 0},
        {usbd, clk_max, 12000000, 0},
        {usb2, clk_max, 12000000, 0},
        {usb3, clk_max, 12000000, 0},
index a1638129eba40d7bdb0e651d961396aaed75e51d..32c61cb6d0bb186d01a37fbea5dc3b15ef126e86 100644 (file)
@@ -275,6 +275,7 @@ static DEFINE_SPINLOCK(clk_out_lock);
 static DEFINE_SPINLOCK(pll_div_lock);
 static DEFINE_SPINLOCK(cml_lock);
 static DEFINE_SPINLOCK(pll_d_lock);
+static DEFINE_SPINLOCK(sysrate_lock);
 
 #define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset,        \
                            _clk_num, _regs, _gate_flags, _clk_id)      \
@@ -327,21 +328,21 @@ enum tegra30_clk {
        kbc = 36, statmon, pmc, kfuse = 40, sbc1, nor, sbc2 = 44, sbc3 = 46,
        i2c5, dsia, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
        usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
-       pcie, owr, afi, csite, pciex, avpucq, la, dtv = 79, ndspeed, i2c_slow,
+       pcie, owr, afi, csite, pciex, avpucq, la, dtv = 79, ndspeed, i2cslow,
        dsib, irama = 84, iramb, iramc, iramd, cram2, audio_2x = 90, csus = 92,
        cdev1, cdev2, cpu_g = 96, cpu_lp, gr3d2, mselect, tsensor, i2s3, i2s4,
        i2c4, sbc5, sbc6, d_audio, apbif, dam0, dam1, dam2, hda2codec_2x,
        atomics, audio0_2x, audio1_2x, audio2_2x, audio3_2x, audio4_2x,
-       spdif_2x, actmon, extern1, extern2, extern3, sata_oob, sata, hda, se,
-       hda2hdmi, sata_cold, uartb = 160, vfir, spdif_out, spdif_in, vi,
-       vi_sensor, fuse, fuse_burn, cve, tvo, clk_32k, clk_m, clk_m_div2,
+       spdif_2x, actmon, extern1, extern2, extern3, sata_oob, sata, hda,
+       se = 127, hda2hdmi, sata_cold, uartb = 160, vfir, spdif_in, spdif_out,
+       vi, vi_sensor, fuse, fuse_burn, cve, tvo, clk_32k, clk_m, clk_m_div2,
        clk_m_div4, pll_ref, pll_c, pll_c_out1, pll_m, pll_m_out1, pll_p,
        pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_a, pll_a_out0,
        pll_d, pll_d_out0, pll_d2, pll_d2_out0, pll_u, pll_x, pll_x_out0, pll_e,
        spdif_in_sync, i2s0_sync, i2s1_sync, i2s2_sync, i2s3_sync, i2s4_sync,
        vimclk_sync, audio0, audio1, audio2, audio3, audio4, spdif, clk_out_1,
        clk_out_2, clk_out_3, sclk, blink, cclk_g, cclk_lp, twd, cml0, cml1,
-       i2cslow, hclk, pclk, clk_out_1_mux = 300, clk_max
+       hclk, pclk, clk_out_1_mux = 300, clk_max
 };
 
 static struct clk *clks[clk_max];
@@ -1249,16 +1250,16 @@ static void __init tegra30_pmc_clk_init(void)
 
 }
 
-const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
-                                "pll_p_cclkg", "pll_p_out4_cclkg",
-                                "pll_p_out3_cclkg", "unused", "pll_x" };
-const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
-                                 "pll_p_cclklp", "pll_p_out4_cclklp",
-                                 "pll_p_out3_cclklp", "unused", "pll_x",
-                                 "pll_x_out0" };
-const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
-                              "pll_p_out3", "pll_p_out2", "unused",
-                              "clk_32k", "pll_m_out1" };
+static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
+                                       "pll_p_cclkg", "pll_p_out4_cclkg",
+                                       "pll_p_out3_cclkg", "unused", "pll_x" };
+static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
+                                        "pll_p_cclklp", "pll_p_out4_cclklp",
+                                        "pll_p_out3_cclklp", "unused", "pll_x",
+                                        "pll_x_out0" };
+static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
+                                     "pll_p_out3", "pll_p_out2", "unused",
+                                     "clk_32k", "pll_m_out1" };
 
 static void __init tegra30_super_clk_init(void)
 {
@@ -1348,19 +1349,21 @@ static void __init tegra30_super_clk_init(void)
 
        /* HCLK */
        clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
-                                  clk_base + SYSTEM_CLK_RATE, 4, 2, 0, NULL);
+                                  clk_base + SYSTEM_CLK_RATE, 4, 2, 0,
+                                  &sysrate_lock);
        clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT,
                                clk_base + SYSTEM_CLK_RATE, 7,
-                               CLK_GATE_SET_TO_DISABLE, NULL);
+                               CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
        clk_register_clkdev(clk, "hclk", NULL);
        clks[hclk] = clk;
 
        /* PCLK */
        clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
-                                  clk_base + SYSTEM_CLK_RATE, 0, 2, 0, NULL);
+                                  clk_base + SYSTEM_CLK_RATE, 0, 2, 0,
+                                  &sysrate_lock);
        clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT,
                                clk_base + SYSTEM_CLK_RATE, 3,
-                               CLK_GATE_SET_TO_DISABLE, NULL);
+                               CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
        clk_register_clkdev(clk, "pclk", NULL);
        clks[pclk] = clk;
 
@@ -1874,7 +1877,11 @@ static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
 };
 
 static __initdata struct tegra_clk_init_table init_table[] = {
-       {uarta, pll_p, 408000000, 1},
+       {uarta, pll_p, 408000000, 0},
+       {uartb, pll_p, 408000000, 0},
+       {uartc, pll_p, 408000000, 0},
+       {uartd, pll_p, 408000000, 0},
+       {uarte, pll_p, 408000000, 0},
        {pll_a, clk_max, 564480000, 1},
        {pll_a_out0, clk_max, 11289600, 1},
        {extern1, pll_a_out0, 0, 1},