Merge tag 'pinctrl-for-v3.9' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw...
authorLinus Torvalds <torvalds@linux-foundation.org>
Wed, 20 Feb 2013 17:23:30 +0000 (09:23 -0800)
committerLinus Torvalds <torvalds@linux-foundation.org>
Wed, 20 Feb 2013 17:23:30 +0000 (09:23 -0800)
Pull pinctrl changes from Linus Walleij:
 "These are the main pinctrl changes for the v3.9 merge window.  The
  most interesting change by far is how the device core grabs pinctrl
  default handles avoiding the need to stick boilerplate into driver
  consumers.

   - Grabbing of default pinctrl handles from the device core.  These
     are the hunks hitting drivers/base.  All is ACKed by Greg, after a
     long discussion about different alternatives.

   - Some stuff also touches the MFD and ARM SoC trees, this has been
     coordinated and ACKed.

   - New drivers for:
     - The Tegra 114 sub-SoC
     - Allwinner sunxi
     - New ABx500 driver and sub-SoC drivers for AB8500, AB8505, AB9540
       and AB8540.

   - Make it possible for hogged pins to enter a sleep mode, and make it
     possible for drivers to control that mode.

   - Various clean-up, extensions and device tree support to various pin
     controllers."

* tag 'pinctrl-for-v3.9' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (68 commits)
  pinctrl: tegra: add clfvs function to Tegra114 support
  pinctrl: generic: rename input schmitt disable
  pinctrl/pinconfig: add debug interface
  pinctrl: samsung: remove duplicated line
  ARM: ux500: use real AB8500 IRQ numbers instead of virtual ones
  ARM: ux500: remove irq_base property from platform_data
  pinctrl/abx500: use direct IRQ defines
  pinctrl/abx500: replace IRQ offsets with table read-in values
  pinctrl/abx500: move IRQ handling to ab8500-core
  pinctrl: exynos5440: remove erroneous __init
  pinctrl/abx500: adjust offset for get_mode()
  pinctrl/abx500: add Device Tree support
  pinctrl/abx500: align GPIO cluster boundaries
  pinctrl/abx500: prevent error path from corrupting returning error
  pinctrl: sunxi: add of_xlate function
  pinctrl/lantiq: fix pin number in ltq_pmx_gpio_request_enable
  pinctrl/lantiq: add functionality to falcon_pinconf_dbg_show
  pinctrl/lantiq: fix pinconfig parameters
  pinctrl/lantiq: one of the boot leds was defined incorrectly
  pinctrl/lantiq: only probe available pad controllers
  ...

54 files changed:
Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt [new file with mode: 0644]
Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.txt [new file with mode: 0644]
Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt [new file with mode: 0644]
Documentation/devicetree/bindings/vendor-prefixes.txt
Documentation/pinctrl.txt
arch/arm/Kconfig
arch/arm/boot/dts/dbx5x0.dtsi
arch/arm/boot/dts/sun4i-a10.dtsi
arch/arm/boot/dts/sun5i-a13-olinuxino.dts
arch/arm/boot/dts/sun5i-a13.dtsi
arch/arm/mach-sunxi/Kconfig
arch/arm/mach-ux500/Kconfig
arch/arm/mach-ux500/board-mop500.c
arch/arm/mach-ux500/cpu-db8500.c
arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
drivers/base/Makefile
drivers/base/dd.c
drivers/base/pinctrl.c [new file with mode: 0644]
drivers/gpio/Kconfig
drivers/gpio/Makefile
drivers/gpio/gpio-ab8500.c [deleted file]
drivers/gpio/gpiolib-of.c
drivers/pinctrl/Kconfig
drivers/pinctrl/Makefile
drivers/pinctrl/core.c
drivers/pinctrl/core.h
drivers/pinctrl/devicetree.c
drivers/pinctrl/pinconf-generic.c
drivers/pinctrl/pinconf.c
drivers/pinctrl/pinctrl-ab8500.c [new file with mode: 0644]
drivers/pinctrl/pinctrl-ab8505.c [new file with mode: 0644]
drivers/pinctrl/pinctrl-ab8540.c [new file with mode: 0644]
drivers/pinctrl/pinctrl-ab9540.c [new file with mode: 0644]
drivers/pinctrl/pinctrl-abx500.c [new file with mode: 0644]
drivers/pinctrl/pinctrl-abx500.h [new file with mode: 0644]
drivers/pinctrl/pinctrl-falcon.c
drivers/pinctrl/pinctrl-lantiq.c
drivers/pinctrl/pinctrl-lantiq.h
drivers/pinctrl/pinctrl-nomadik.c
drivers/pinctrl/pinctrl-samsung.c
drivers/pinctrl/pinctrl-sunxi.c [new file with mode: 0644]
drivers/pinctrl/pinctrl-sunxi.h [new file with mode: 0644]
drivers/pinctrl/pinctrl-tegra.c
drivers/pinctrl/pinctrl-tegra.h
drivers/pinctrl/pinctrl-tegra114.c [new file with mode: 0644]
drivers/pinctrl/pinctrl-tegra20.c
drivers/pinctrl/pinctrl-tegra30.c
drivers/pinctrl/pinctrl-xway.c
include/linux/device.h
include/linux/mfd/abx500/ab8500-gpio.h
include/linux/mfd/abx500/ab8500.h
include/linux/pinctrl/devinfo.h [new file with mode: 0644]
include/linux/pinctrl/pinconf-generic.h
include/linux/pinctrl/pinctrl.h

diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
new file mode 100644 (file)
index 0000000..dff0e5f
--- /dev/null
@@ -0,0 +1,60 @@
+* Allwinner A1X Pin Controller
+
+The pins controlled by sunXi pin controller are organized in banks,
+each bank has 32 pins.  Each pin has 7 multiplexing functions, with
+the first two functions being GPIO in and out. The configuration on
+the pins includes drive strength and pull-up.
+
+Required properties:
+- compatible: "allwinner,<soc>-pinctrl". Supported SoCs for now are:
+  sun5i-a13.
+- reg: Should contain the register physical address and length for the
+  pin controller.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices.
+
+A pinctrl node should contain at least one subnodes representing the
+pinctrl groups available on the machine. Each subnode will list the
+pins it needs, and how they should be configured, with regard to muxer
+configuration, drive strength and pullups. If one of these options is
+not set, its actual value will be unspecified.
+
+Required subnode-properties:
+
+- allwinner,pins: List of strings containing the pin name.
+- allwinner,function: Function to mux the pins listed above to.
+
+Optional subnode-properties:
+- allwinner,drive: Integer. Represents the current sent to the pin
+    0: 10 mA
+    1: 20 mA
+    2: 30 mA
+    3: 40 mA
+- allwinner,pull: Integer.
+    0: No resistor
+    1: Pull-up resistor
+    2: Pull-down resistor
+
+Examples:
+
+pinctrl@01c20800 {
+       compatible = "allwinner,sun5i-a13-pinctrl";
+       reg = <0x01c20800 0x400>;
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       uart1_pins_a: uart1@0 {
+               allwinner,pins = "PE10", "PE11";
+               allwinner,function = "uart1";
+               allwinner,drive = <0>;
+               allwinner,pull = <0>;
+       };
+
+       uart1_pins_b: uart1@1 {
+               allwinner,pins = "PG3", "PG4";
+               allwinner,function = "uart1";
+               allwinner,drive = <0>;
+               allwinner,pull = <0>;
+       };
+};
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.txt
new file mode 100644 (file)
index 0000000..e204d00
--- /dev/null
@@ -0,0 +1,120 @@
+NVIDIA Tegra114 pinmux controller
+
+The Tegra114 pinctrl binding is very similar to the Tegra20 and Tegra30
+pinctrl binding, as described in nvidia,tegra20-pinmux.txt and
+nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as
+a baseline, and only documents the differences between the two bindings.
+
+Required properties:
+- compatible: "nvidia,tegra114-pinmux"
+- reg: Should contain the register physical address and length for each of
+  the pad control and mux registers. The first bank of address must be the
+  driver strength pad control register address and second bank address must
+  be pinmux register address.
+
+Tegra114 adds the following optional properties for pin configuration subnodes:
+- nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
+- nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
+- nvidia,lock: Integer. Lock the pin configuration against further changes
+    until reset. 0: no, 1: yes.
+- nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
+- nvidia,rcv-sel: Integer. Select VIL/VIH receivers. 0: normal, 1: high.
+- nvidia,drive-type: Integer. Valid range 0...3.
+
+As with Tegra20 and Terga30, see the Tegra TRM for complete details regarding
+which groups support which functionality.
+
+Valid values for pin and group names are:
+
+  per-pin mux groups:
+
+    These all support nvidia,function, nvidia,tristate, nvidia,pull,
+    nvidia,enable-input, nvidia,lock. Some support nvidia,open-drain,
+    nvidia,io-reset and nvidia,rcv-sel.
+
+    ulpi_data0_po1, ulpi_data1_po2, ulpi_data2_po3, ulpi_data3_po4,
+    ulpi_data4_po5, ulpi_data5_po6, ulpi_data6_po7, ulpi_data7_po0,
+    ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3, dap3_fs_pp0,
+    dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3, pv0, pv1, sdmmc1_clk_pz0,
+    sdmmc1_cmd_pz1, sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6,
+    sdmmc1_dat0_py7, clk2_out_pw5, clk2_req_pcc5, hdmi_int_pn7, ddc_scl_pv4,
+    ddc_sda_pv5, uart2_rxd_pc3, uart2_txd_pc2, uart2_rts_n_pj6,
+    uart2_cts_n_pj5, uart3_txd_pw6, uart3_rxd_pw7, uart3_cts_n_pa1,
+    uart3_rts_n_pc0, pu0, pu1, pu2, pu3, pu4, pu5, pu6, gen1_i2c_sda_pc5,
+    gen1_i2c_scl_pc4, dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7,
+    clk3_out_pee0, clk3_req_pee1, gmi_wp_n_pc7, gmi_iordy_pi5, gmi_wait_pi7,
+    gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs0_n_pj0, gmi_cs1_n_pj2, gmi_cs2_n_pk3,
+    gmi_cs3_n_pk4, gmi_cs4_n_pk2, gmi_cs6_n_pi3, gmi_cs7_n_pi6, gmi_ad0_pg0,
+    gmi_ad1_pg1, gmi_ad2_pg2, gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5,
+    gmi_ad6_pg6, gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2,
+    gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6, gmi_ad15_ph7,
+    gmi_a16_pj7, gmi_a17_pb0, gmi_a18_pb1, gmi_a19_pk7, gmi_wr_n_pi0,
+    gmi_oe_n_pi1, gmi_dqs_p_pj3, gmi_rst_n_pi4, gen2_i2c_scl_pt5,
+    gen2_i2c_sda_pt6, sdmmc4_clk_pcc4, sdmmc4_cmd_pt7, sdmmc4_dat0_paa0,
+    sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, sdmmc4_dat4_paa4,
+    sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, sdmmc4_dat7_paa7, cam_mclk_pcc0,
+    pcc1, pbb0, cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6,
+    pbb7, pcc2, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, kb_row0_pr0, kb_row1_pr1,
+    kb_row2_pr2, kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6,
+    kb_row7_pr7, kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_col0_pq0,
+    kb_col1_pq1, kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5,
+    kb_col6_pq6, kb_col7_pq7, clk_32k_out_pa0, sys_clk_req_pz5, core_pwr_req,
+    cpu_pwr_req, pwr_int_n, owr, dap1_fs_pn0, dap1_din_pn1, dap1_dout_pn2,
+    dap1_sclk_pn3, clk1_req_pee2, clk1_out_pw4, spdif_in_pk6, spdif_out_pk5,
+    dap2_fs_pa2, dap2_din_pa4, dap2_dout_pa5, dap2_sclk_pa3, dvfs_pwm_px0,
+    gpio_x1_aud_px1, gpio_x3_aud_px3, dvfs_clk_px2, gpio_x4_aud_px4,
+    gpio_x5_aud_px5, gpio_x6_aud_px6, gpio_x7_aud_px7, sdmmc3_clk_pa6,
+    sdmmc3_cmd_pa7, sdmmc3_dat0_pb7, sdmmc3_dat1_pb6, sdmmc3_dat2_pb5,
+    sdmmc3_dat3_pb4, hdmi_cec_pee3, sdmmc1_wp_n_pv3, sdmmc3_cd_n_pv2,
+    gpio_w2_aud_pw2, gpio_w3_aud_pw3, usb_vbus_en0_pn4, usb_vbus_en1_pn5,
+    sdmmc3_clk_lb_in_pee5, sdmmc3_clk_lb_out_pee4, reset_out_n.
+
+  drive groups:
+
+    These all support nvidia,pull-down-strength, nvidia,pull-up-strength,
+    nvidia,slew-rate-rising, nvidia,slew-rate-falling. Most but not all
+    support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode
+    and nvidia,drive-type.
+
+    ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, dap1, dap2, dap3, dap4,
+    dbg, sdio3, spi, uaa, uab, uart2, uart3, sdio1, ddc, gma, gme, gmf, gmg,
+    gmh, owr, uda.
+
+Example:
+
+       pinmux: pinmux {
+               compatible = "nvidia,tegra114-pinmux";
+               reg = <0x70000868 0x148         /* Pad control registers */
+                      0x70003000 0x40c>;       /* PinMux registers */
+       };
+
+Example board file extract:
+
+       pinctrl {
+               sdmmc4_default: pinmux {
+                       sdmmc4_clk_pcc4 {
+                               nvidia,pins = "sdmmc4_clk_pcc4",
+                               nvidia,function = "sdmmc4";
+                               nvidia,pull = <0>;
+                               nvidia,tristate = <0>;
+                       };
+                       sdmmc4_dat0_paa0 {
+                               nvidia,pins = "sdmmc4_dat0_paa0",
+                                               "sdmmc4_dat1_paa1",
+                                               "sdmmc4_dat2_paa2",
+                                               "sdmmc4_dat3_paa3",
+                                               "sdmmc4_dat4_paa4",
+                                               "sdmmc4_dat5_paa5",
+                                               "sdmmc4_dat6_paa6",
+                                               "sdmmc4_dat7_paa7";
+                               nvidia,function = "sdmmc4";
+                               nvidia,pull = <2>;
+                               nvidia,tristate = <0>;
+                       };
+               };
+       };
+
+       sdhci@78000400 {
+               pinctrl-names = "default";
+               pinctrl-0 = <&sdmmc4_default>;
+       };
diff --git a/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt b/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt
new file mode 100644 (file)
index 0000000..9a2f3f4
--- /dev/null
@@ -0,0 +1,140 @@
+ST Ericsson Nomadik pinmux controller
+
+Required properties:
+- compatible: "stericsson,nmk-pinctrl", "stericsson,nmk-pinctrl-db8540",
+              "stericsson,nmk-pinctrl-stn8815"
+- reg: Should contain the register physical address and length of the PRCMU.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+ST Ericsson's pin configuration nodes act as a container for an arbitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as input, output, pull up, pull down...
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Required subnode-properties:
+- ste,pins : An array of strings. Each string contains the name of a pin or
+    group.
+
+Optional subnode-properties:
+- ste,function: A string containing the name of the function to mux to the
+  pin or group.
+
+- ste,config: Handle of pin configuration node (e.g. ste,config = <&slpm_in_wkup_pdis>)
+
+- ste,input : <0/1/2>
+       0: input with no pull
+       1: input with pull up,
+       2: input with pull down,
+
+- ste,output: <0/1/2>
+       0: output low,
+       1: output high,
+       2: output (value is not specified).
+
+- ste,sleep: <0/1>
+       0: sleep mode disable,
+       1: sleep mode enable.
+
+- ste,sleep-input: <0/1/2/3>
+       0: sleep input with no pull,
+       1: sleep input with pull up,
+       2: sleep input with pull down.
+       3: sleep input and keep last input configuration (no pull, pull up or pull down).
+
+- ste,sleep-output: <0/1/2>
+       0: sleep output low,
+       1: sleep output high,
+       2: sleep output (value is not specified).
+
+- ste,sleep-gpio: <0/1>
+       0: disable sleep gpio mode,
+       1: enable sleep gpio mode.
+
+- ste,sleep-wakeup: <0/1>
+       0: wake-up detection enabled,
+       1: wake-up detection disabled.
+
+- ste,sleep-pull-disable: <0/1>
+       0: GPIO pull-up or pull-down resistor is enabled, when pin is an input,
+       1: GPIO pull-up and pull-down resistor are disabled.
+
+Example board file extract:
+
+       pinctrl@80157000 {
+               compatible = "stericsson,nmk-pinctrl";
+               reg = <0x80157000 0x2000>;
+
+               pinctrl-names = "default";
+
+               slpm_in_wkup_pdis: slpm_in_wkup_pdis {
+                       ste,sleep = <1>;
+                       ste,sleep-input = <3>;
+                       ste,sleep-wakeup = <1>;
+                       ste,sleep-pull-disable = <0>;
+               };
+
+               slpm_out_hi_wkup_pdis: slpm_out_hi_wkup_pdis {
+                       ste,sleep = <1>;
+                       ste,sleep-output = <1>;
+                       ste,sleep-wakeup = <1>;
+                       ste,sleep-pull-disable = <0>;
+               };
+
+               slpm_out_wkup_pdis: slpm_out_wkup_pdis {
+                       ste,sleep = <1>;
+                       ste,sleep-output = <2>;
+                       ste,sleep-wakeup = <1>;
+                       ste,sleep-pull-disable = <0>;
+               };
+
+               uart0 {
+                       uart0_default_mux: uart0_mux {
+                               u0_default_mux {
+                                       ste,function = "u0";
+                                       ste,pins = "u0_a_1";
+                               };
+                       };
+                       uart0_default_mode: uart0_default {
+                               uart0_default_cfg1 {
+                                       ste,pins = "GPIO0", "GPIO2";
+                                       ste,input = <1>;
+                               };
+
+                               uart0_default_cfg2 {
+                                       ste,pins = "GPIO1", "GPIO3";
+                                       ste,output = <1>;
+                               };
+                       };
+                       uart0_sleep_mode: uart0_sleep {
+                               uart0_sleep_cfg1 {
+                                       ste,pins = "GPIO0", "GPIO2";
+                                       ste,config = <&slpm_in_wkup_pdis>;
+                               };
+                               uart0_sleep_cfg2 {
+                                       ste,pins = "GPIO1";
+                                       ste,config = <&slpm_out_hi_wkup_pdis>;
+                               };
+                               uart0_sleep_cfg3 {
+                                       ste,pins = "GPIO3";
+                                       ste,config = <&slpm_out_wkup_pdis>;
+                               };
+                       };
+               };
+       };
+
+       uart@80120000 {
+               compatible = "arm,pl011", "arm,primecell";
+               reg = <0x80120000 0x1000>;
+               interrupts = <0 11 0x4>;
+
+               pinctrl-names = "default","sleep";
+               pinctrl-0 = <&uart0_default_mux>, <&uart0_default_mode>;
+               pinctrl-1 = <&uart0_sleep_mode>;
+       };
index 902b1b1f568e39b16a26e0ca6278f9225ea1fd9e..15321373ec8d4113acfba3f4917aa30fe96bb53b 100644 (file)
@@ -50,6 +50,7 @@ simtek
 sirf   SiRF Technology, Inc.
 snps   Synopsys, Inc.
 st     STMicroelectronics
+ste    ST-Ericsson
 stericsson     ST-Ericsson
 ti     Texas Instruments
 via    VIA Technologies, Inc.
index da40efbef6ec5599406a1e086f7b11aaaa06e018..a2b57e0a1db04d6454253d8f8fa7b383fcb974ed 100644 (file)
@@ -972,6 +972,18 @@ pinmux core.
 Pin control requests from drivers
 =================================
 
+When a device driver is about to probe the device core will automatically
+attempt to issue pinctrl_get_select_default() on these devices.
+This way driver writers do not need to add any of the boilerplate code
+of the type found below. However when doing fine-grained state selection
+and not using the "default" state, you may have to do some device driver
+handling of the pinctrl handles and states.
+
+So if you just want to put the pins for a certain device into the default
+state and be done with it, there is nothing you need to do besides
+providing the proper mapping table. The device core will take care of
+the rest.
+
 Generally it is discouraged to let individual drivers get and enable pin
 control. So if possible, handle the pin control in platform code or some other
 place where you have access to all the affected struct device * pointers. In
@@ -1097,9 +1109,9 @@ situations that can be electrically unpleasant, you will certainly want to
 mux in and bias pins in a certain way before the GPIO subsystems starts to
 deal with them.
 
-The above can be hidden: using pinctrl hogs, the pin control driver may be
-setting up the config and muxing for the pins when it is probing,
-nevertheless orthogonal to the GPIO subsystem.
+The above can be hidden: using the device core, the pinctrl core may be
+setting up the config and muxing for the pins right before the device is
+probing, nevertheless orthogonal to the GPIO subsystem.
 
 But there are also situations where it makes sense for the GPIO subsystem
 to communicate directly with with the pinctrl subsystem, using the latter
index 9bbe760f2352dc86266ace6a8d4d4d5f08a26eda..6c0900a9bf5c30039bf852ea42bd3612b522244e 100644 (file)
@@ -1636,7 +1636,7 @@ config ARCH_NR_GPIO
        default 355 if ARCH_U8500
        default 264 if MACH_H4700
        default 512 if SOC_OMAP5
-       default 288 if ARCH_VT8500
+       default 288 if ARCH_VT8500 || ARCH_SUNXI
        default 0
        help
          Maximum number of GPIOs in the system.
index 63f2fbcfe8196823a93ac5f74f2eadebd3ae52f7..69140ba99f465ea357980c84cc232924a69071c0 100644 (file)
                        gpio-bank = <8>;
                };
 
-               pinctrl@80157000 {
-                       // This is actually the PRCMU base address
-                       reg = <0x80157000 0x2000>;
-                       compatible = "stericsson,nmk_pinctrl";
+               pinctrl {
+                       compatible = "stericsson,nmk-pinctrl";
+                       prcm = <&prcmu>;
                };
 
                usb@a03e0000 {
                        interrupts = <0 25 0x4>;
                };
 
-               prcmu@80157000 {
+               prcmu: prcmu@80157000 {
                        compatible = "stericsson,db8500-prcmu";
                        reg = <0x80157000 0x1000>;
+                       reg-names = "prcmu";
                        interrupts = <0 47 0x4>;
                        #address-cells = <1>;
                        #size-cells = <1>;
index e61fdd47bd01d31492412be871da11db61502b41..f99f60dadf5dcde62d2e3a6bcccfdc2c3b4fed8c 100644 (file)
        memory {
                reg = <0x40000000 0x80000000>;
        };
+
+       soc {
+               pinctrl@01c20800 {
+                       compatible = "allwinner,sun4i-a10-pinctrl";
+                       reg = <0x01c20800 0x400>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       uart0_pins_a: uart0@0 {
+                               allwinner,pins = "PB22", "PB23";
+                               allwinner,function = "uart0";
+                               allwinner,drive = <0>;
+                               allwinner,pull = <0>;
+                       };
+
+                       uart0_pins_b: uart0@1 {
+                               allwinner,pins = "PF2", "PF4";
+                               allwinner,function = "uart0";
+                               allwinner,drive = <0>;
+                               allwinner,pull = <0>;
+                       };
+
+                       uart1_pins_a: uart1@0 {
+                               allwinner,pins = "PA10", "PA11";
+                               allwinner,function = "uart1";
+                               allwinner,drive = <0>;
+                               allwinner,pull = <0>;
+                       };
+               };
+       };
 };
index 498a091a4ea20c9eba86cf61287d7be24f68612b..4a1e45d4aacef5da48e4d8c6a0da0d3f135f4e3f 100644 (file)
@@ -24,6 +24,8 @@
 
        soc {
                uart1: uart@01c28400 {
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&uart1_pins_b>;
                        status = "okay";
                };
        };
index 59a2d265a98eee4960a74c4a29a49bfe8a7aa31d..e1121890fb29db8d76538a3b482f155d70fdfb61 100644 (file)
        memory {
                reg = <0x40000000 0x20000000>;
        };
+
+       soc {
+               pinctrl@01c20800 {
+                       compatible = "allwinner,sun5i-a13-pinctrl";
+                       reg = <0x01c20800 0x400>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       uart1_pins_a: uart1@0 {
+                               allwinner,pins = "PE10", "PE11";
+                               allwinner,function = "uart1";
+                               allwinner,drive = <0>;
+                               allwinner,pull = <0>;
+                       };
+
+                       uart1_pins_b: uart1@1 {
+                               allwinner,pins = "PG3", "PG4";
+                               allwinner,function = "uart1";
+                               allwinner,drive = <0>;
+                               allwinner,pull = <0>;
+                       };
+               };
+       };
 };
index 3fdd0085e3067bbb1f03dbde1624bf76b595beec..8709a39bd34c461468404a4822f0a13ca0398205 100644 (file)
@@ -7,3 +7,4 @@ config ARCH_SUNXI
        select PINCTRL
        select SPARSE_IRQ
        select SUNXI_TIMER
+       select PINCTRL_SUNXI
\ No newline at end of file
index 5dea90636d94f91e10820a41a502f23b796fc522..3e5bbd0e5b23db9840cda61cb6c5174e5ebe3a12 100644 (file)
@@ -11,6 +11,7 @@ config UX500_SOC_COMMON
        select COMMON_CLK
        select PINCTRL
        select PINCTRL_NOMADIK
+       select PINCTRL_ABX500
        select PL310_ERRATA_753970 if CACHE_PL310
 
 config UX500_SOC_DB8500
@@ -18,6 +19,11 @@ config UX500_SOC_DB8500
        select CPU_FREQ_TABLE if CPU_FREQ
        select MFD_DB8500_PRCMU
        select PINCTRL_DB8500
+       select PINCTRL_DB8540
+       select PINCTRL_AB8500
+       select PINCTRL_AB8505
+       select PINCTRL_AB9540
+       select PINCTRL_AB8540
        select REGULATOR
        select REGULATOR_DB8500_PRCMU
 
index d453522edb0d66b0488e46247fa4446876e69f6f..b8781caa54b8b28d43c7504e61d85711729259e4 100644 (file)
@@ -90,26 +90,8 @@ static struct platform_device snowball_gpio_en_3v3_regulator_dev = {
        },
 };
 
-static struct ab8500_gpio_platform_data ab8500_gpio_pdata = {
+static struct abx500_gpio_platform_data ab8500_gpio_pdata = {
        .gpio_base              = MOP500_AB8500_PIN_GPIO(1),
-       .irq_base               = MOP500_AB8500_VIR_GPIO_IRQ_BASE,
-       /* config_reg is the initial configuration of ab8500 pins.
-        * The pins can be configured as GPIO or alt functions based
-        * on value present in GpioSel1 to GpioSel6 and AlternatFunction
-        * register. This is the array of 7 configuration settings.
-        * One has to compile time decide these settings. Below is the
-        * explanation of these setting
-        * GpioSel1 = 0x00 => Pins GPIO1 to GPIO8 are not used as GPIO
-        * GpioSel2 = 0x1E => Pins GPIO10 to GPIO13 are configured as GPIO
-        * GpioSel3 = 0x80 => Pin GPIO24 is configured as GPIO
-        * GpioSel4 = 0x01 => Pin GPIo25 is configured as GPIO
-        * GpioSel5 = 0x7A => Pins GPIO34, GPIO36 to GPIO39 are conf as GPIO
-        * GpioSel6 = 0x00 => Pins GPIO41 & GPIo42 are not configured as GPIO
-        * AlternaFunction = 0x00 => If Pins GPIO10 to 13 are not configured
-        * as GPIO then this register selectes the alternate fucntions
-        */
-       .config_reg             = {0x00, 0x1E, 0x80, 0x01,
-                                       0x7A, 0x00, 0x00},
 };
 
 /* ab8500-codec */
index 5b286e06474ce481ff019f302bf1a66aec635687..b80ad9610e9752e3c1d9740f03ddaf5f7e0ec5d1 100644 (file)
@@ -285,7 +285,7 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
        OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL),
        OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
        /* Requires device name bindings. */
-       OF_DEV_AUXDATA("stericsson,nmk_pinctrl", U8500_PRCMU_BASE,
+       OF_DEV_AUXDATA("stericsson,nmk-pinctrl", U8500_PRCMU_BASE,
                "pinctrl-db8500", NULL),
        /* Requires clock name and DMA bindings. */
        OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
index 7d34c52798b5dd1e7162d13eb63866cff62e2079..d526dd8e87d3b9927bd579339c59dab50070f397 100644 (file)
 #define MOP500_STMPE1601_IRQ_END       \
        MOP500_STMPE1601_IRQ(STMPE_NR_INTERNAL_IRQS)
 
-/* AB8500 virtual gpio IRQ */
-#define AB8500_VIR_GPIO_NR_IRQS                        16
-
-#define MOP500_AB8500_VIR_GPIO_IRQ_BASE                \
-       MOP500_STMPE1601_IRQ_END
-#define MOP500_AB8500_VIR_GPIO_IRQ_END         \
-       (MOP500_AB8500_VIR_GPIO_IRQ_BASE + AB8500_VIR_GPIO_NR_IRQS)
-
-#define MOP500_NR_IRQS         MOP500_AB8500_VIR_GPIO_IRQ_END
+#define MOP500_NR_IRQS         MOP500_STMPE1601_IRQ_END
 
 #define MOP500_IRQ_END         MOP500_NR_IRQS
 
index 5aa2d703d19fac08073c54e27530ef8d5bc5b45d..4e22ce3ed73d408b97d316c61fefc089e824c3c3 100644 (file)
@@ -21,6 +21,7 @@ endif
 obj-$(CONFIG_SYS_HYPERVISOR) += hypervisor.o
 obj-$(CONFIG_REGMAP)   += regmap/
 obj-$(CONFIG_SOC_BUS) += soc.o
+obj-$(CONFIG_PINCTRL) += pinctrl.o
 
 ccflags-$(CONFIG_DEBUG_DRIVER) := -DDEBUG
 
index e3bbed8a617c257373a1fa2d75318d9ff930601a..656310156ddeeeabc0d709f3393b9af27e949214 100644 (file)
@@ -24,6 +24,7 @@
 #include <linux/wait.h>
 #include <linux/async.h>
 #include <linux/pm_runtime.h>
+#include <linux/pinctrl/devinfo.h>
 
 #include "base.h"
 #include "power/power.h"
@@ -269,6 +270,12 @@ static int really_probe(struct device *dev, struct device_driver *drv)
        WARN_ON(!list_empty(&dev->devres_head));
 
        dev->driver = drv;
+
+       /* If using pinctrl, bind pins now before probing */
+       ret = pinctrl_bind_pins(dev);
+       if (ret)
+               goto probe_failed;
+
        if (driver_sysfs_add(dev)) {
                printk(KERN_ERR "%s: driver_sysfs_add(%s) failed\n",
                        __func__, dev_name(dev));
diff --git a/drivers/base/pinctrl.c b/drivers/base/pinctrl.c
new file mode 100644 (file)
index 0000000..67a274e
--- /dev/null
@@ -0,0 +1,69 @@
+/*
+ * Driver core interface to the pinctrl subsystem.
+ *
+ * Copyright (C) 2012 ST-Ericsson SA
+ * Written on behalf of Linaro for ST-Ericsson
+ * Based on bits of regulator core, gpio core and clk core
+ *
+ * Author: Linus Walleij <linus.walleij@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include <linux/device.h>
+#include <linux/pinctrl/devinfo.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/slab.h>
+
+/**
+ * pinctrl_bind_pins() - called by the device core before probe
+ * @dev: the device that is just about to probe
+ */
+int pinctrl_bind_pins(struct device *dev)
+{
+       int ret;
+
+       dev->pins = devm_kzalloc(dev, sizeof(*(dev->pins)), GFP_KERNEL);
+       if (!dev->pins)
+               return -ENOMEM;
+
+       dev->pins->p = devm_pinctrl_get(dev);
+       if (IS_ERR(dev->pins->p)) {
+               dev_dbg(dev, "no pinctrl handle\n");
+               ret = PTR_ERR(dev->pins->p);
+               goto cleanup_alloc;
+       }
+
+       dev->pins->default_state = pinctrl_lookup_state(dev->pins->p,
+                                       PINCTRL_STATE_DEFAULT);
+       if (IS_ERR(dev->pins->default_state)) {
+               dev_dbg(dev, "no default pinctrl state\n");
+               ret = 0;
+               goto cleanup_get;
+       }
+
+       ret = pinctrl_select_state(dev->pins->p, dev->pins->default_state);
+       if (ret) {
+               dev_dbg(dev, "failed to activate default pinctrl state\n");
+               goto cleanup_get;
+       }
+
+       return 0;
+
+       /*
+        * If no pinctrl handle or default state was found for this device,
+        * let's explicitly free the pin container in the device, there is
+        * no point in keeping it around.
+        */
+cleanup_get:
+       devm_pinctrl_put(dev->pins->p);
+cleanup_alloc:
+       devm_kfree(dev, dev->pins);
+       dev->pins = NULL;
+
+       /* Only return deferrals */
+       if (ret != -EPROBE_DEFER)
+               ret = 0;
+
+       return ret;
+}
index 682de754d63f166a92de96338c7f4d01bf87cdb2..e5116fa851406ffc57b900ba3374f2f09091216a 100644 (file)
@@ -657,12 +657,6 @@ config GPIO_JANZ_TTL
          This driver provides support for driving the pins in output
          mode only. Input mode is not supported.
 
-config GPIO_AB8500
-       bool "ST-Ericsson AB8500 Mixed Signal Circuit gpio functions"
-       depends on AB8500_CORE && BROKEN
-       help
-         Select this to enable the AB8500 IC GPIO driver
-
 config GPIO_TPS6586X
        bool "TPS6586X GPIO"
        depends on MFD_TPS6586X
index c5aebd008dde4d3e5428fb90de3563f82ae159ac..45a388c21d0468f54782492dc014dcdbb0a5df14 100644 (file)
@@ -10,7 +10,6 @@ obj-$(CONFIG_GPIO_ACPI)               += gpiolib-acpi.o
 obj-$(CONFIG_GPIO_GENERIC)     += gpio-generic.o
 
 obj-$(CONFIG_GPIO_74X164)      += gpio-74x164.o
-obj-$(CONFIG_GPIO_AB8500)      += gpio-ab8500.o
 obj-$(CONFIG_GPIO_ADNP)                += gpio-adnp.o
 obj-$(CONFIG_GPIO_ADP5520)     += gpio-adp5520.o
 obj-$(CONFIG_GPIO_ADP5588)     += gpio-adp5588.o
diff --git a/drivers/gpio/gpio-ab8500.c b/drivers/gpio/gpio-ab8500.c
deleted file mode 100644 (file)
index 983ad42..0000000
+++ /dev/null
@@ -1,520 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2011
- *
- * Author: BIBEK BASU <bibek.basu@stericsson.com>
- * License terms: GNU General Public License (GPL) version 2
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/err.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/mfd/ab8500.h>
-#include <linux/mfd/abx500.h>
-#include <linux/mfd/ab8500/gpio.h>
-
-/*
- * GPIO registers offset
- * Bank: 0x10
- */
-#define AB8500_GPIO_SEL1_REG   0x00
-#define AB8500_GPIO_SEL2_REG   0x01
-#define AB8500_GPIO_SEL3_REG   0x02
-#define AB8500_GPIO_SEL4_REG   0x03
-#define AB8500_GPIO_SEL5_REG   0x04
-#define AB8500_GPIO_SEL6_REG   0x05
-
-#define AB8500_GPIO_DIR1_REG   0x10
-#define AB8500_GPIO_DIR2_REG   0x11
-#define AB8500_GPIO_DIR3_REG   0x12
-#define AB8500_GPIO_DIR4_REG   0x13
-#define AB8500_GPIO_DIR5_REG   0x14
-#define AB8500_GPIO_DIR6_REG   0x15
-
-#define AB8500_GPIO_OUT1_REG   0x20
-#define AB8500_GPIO_OUT2_REG   0x21
-#define AB8500_GPIO_OUT3_REG   0x22
-#define AB8500_GPIO_OUT4_REG   0x23
-#define AB8500_GPIO_OUT5_REG   0x24
-#define AB8500_GPIO_OUT6_REG   0x25
-
-#define AB8500_GPIO_PUD1_REG   0x30
-#define AB8500_GPIO_PUD2_REG   0x31
-#define AB8500_GPIO_PUD3_REG   0x32
-#define AB8500_GPIO_PUD4_REG   0x33
-#define AB8500_GPIO_PUD5_REG   0x34
-#define AB8500_GPIO_PUD6_REG   0x35
-
-#define AB8500_GPIO_IN1_REG    0x40
-#define AB8500_GPIO_IN2_REG    0x41
-#define AB8500_GPIO_IN3_REG    0x42
-#define AB8500_GPIO_IN4_REG    0x43
-#define AB8500_GPIO_IN5_REG    0x44
-#define AB8500_GPIO_IN6_REG    0x45
-#define AB8500_GPIO_ALTFUN_REG 0x45
-#define ALTFUN_REG_INDEX       6
-#define AB8500_NUM_GPIO                42
-#define AB8500_NUM_VIR_GPIO_IRQ        16
-
-enum ab8500_gpio_action {
-       NONE,
-       STARTUP,
-       SHUTDOWN,
-       MASK,
-       UNMASK
-};
-
-struct ab8500_gpio {
-       struct gpio_chip chip;
-       struct ab8500 *parent;
-       struct device *dev;
-       struct mutex lock;
-       u32 irq_base;
-       enum ab8500_gpio_action irq_action;
-       u16 rising;
-       u16 falling;
-};
-/**
- * to_ab8500_gpio() - get the pointer to ab8500_gpio
- * @chip:      Member of the structure ab8500_gpio
- */
-static inline struct ab8500_gpio *to_ab8500_gpio(struct gpio_chip *chip)
-{
-       return container_of(chip, struct ab8500_gpio, chip);
-}
-
-static int ab8500_gpio_set_bits(struct gpio_chip *chip, u8 reg,
-                                       unsigned offset, int val)
-{
-       struct ab8500_gpio *ab8500_gpio = to_ab8500_gpio(chip);
-       u8 pos = offset % 8;
-       int ret;
-
-       reg = reg + (offset / 8);
-       ret = abx500_mask_and_set_register_interruptible(ab8500_gpio->dev,
-                               AB8500_MISC, reg, 1 << pos, val << pos);
-       if (ret < 0)
-               dev_err(ab8500_gpio->dev, "%s write failed\n", __func__);
-       return ret;
-}
-/**
- * ab8500_gpio_get() - Get the particular GPIO value
- * @chip: Gpio device
- * @offset: GPIO number to read
- */
-static int ab8500_gpio_get(struct gpio_chip *chip, unsigned offset)
-{
-       struct ab8500_gpio *ab8500_gpio = to_ab8500_gpio(chip);
-       u8 mask = 1 << (offset % 8);
-       u8 reg = AB8500_GPIO_OUT1_REG + (offset / 8);
-       int ret;
-       u8 data;
-       ret = abx500_get_register_interruptible(ab8500_gpio->dev, AB8500_MISC,
-                                               reg, &data);
-       if (ret < 0) {
-               dev_err(ab8500_gpio->dev, "%s read failed\n", __func__);
-               return ret;
-       }
-       return (data & mask) >> (offset % 8);
-}
-
-static void ab8500_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
-{
-       struct ab8500_gpio *ab8500_gpio = to_ab8500_gpio(chip);
-       int ret;
-       /* Write the data */
-       ret = ab8500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, 1);
-       if (ret < 0)
-               dev_err(ab8500_gpio->dev, "%s write failed\n", __func__);
-}
-
-static int ab8500_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
-                                       int val)
-{
-       int ret;
-       /* set direction as output */
-       ret = ab8500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 1);
-       if (ret < 0)
-               return ret;
-       /* disable pull down */
-       ret = ab8500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG, offset, 1);
-       if (ret < 0)
-               return ret;
-       /* set the output as 1 or 0 */
-       return ab8500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
-
-}
-
-static int ab8500_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
-{
-       /* set the register as input */
-       return ab8500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 0);
-}
-
-static int ab8500_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
-{
-       /*
-        * Only some GPIOs are interrupt capable, and they are
-        * organized in discontiguous clusters:
-        *
-        *      GPIO6 to GPIO13
-        *      GPIO24 and GPIO25
-        *      GPIO36 to GPIO41
-        */
-       static struct ab8500_gpio_irq_cluster {
-               int start;
-               int end;
-       } clusters[] = {
-               {.start = 6,  .end = 13},
-               {.start = 24, .end = 25},
-               {.start = 36, .end = 41},
-       };
-       struct ab8500_gpio *ab8500_gpio = to_ab8500_gpio(chip);
-       int base = ab8500_gpio->irq_base;
-       int i;
-
-       for (i = 0; i < ARRAY_SIZE(clusters); i++) {
-               struct ab8500_gpio_irq_cluster *cluster = &clusters[i];
-
-               if (offset >= cluster->start && offset <= cluster->end)
-                       return base + offset - cluster->start;
-
-               /* Advance by the number of gpios in this cluster */
-               base += cluster->end - cluster->start + 1;
-       }
-
-       return -EINVAL;
-}
-
-static struct gpio_chip ab8500gpio_chip = {
-       .label                  = "ab8500_gpio",
-       .owner                  = THIS_MODULE,
-       .direction_input        = ab8500_gpio_direction_input,
-       .get                    = ab8500_gpio_get,
-       .direction_output       = ab8500_gpio_direction_output,
-       .set                    = ab8500_gpio_set,
-       .to_irq                 = ab8500_gpio_to_irq,
-};
-
-static unsigned int irq_to_rising(unsigned int irq)
-{
-       struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
-       int offset = irq - ab8500_gpio->irq_base;
-       int new_irq = offset +  AB8500_INT_GPIO6R
-                       + ab8500_gpio->parent->irq_base;
-       return new_irq;
-}
-
-static unsigned int irq_to_falling(unsigned int irq)
-{
-       struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
-       int offset = irq - ab8500_gpio->irq_base;
-       int new_irq = offset +  AB8500_INT_GPIO6F
-                       +  ab8500_gpio->parent->irq_base;
-       return new_irq;
-
-}
-
-static unsigned int rising_to_irq(unsigned int irq, void *dev)
-{
-       struct ab8500_gpio *ab8500_gpio = dev;
-       int offset = irq - AB8500_INT_GPIO6R
-                       - ab8500_gpio->parent->irq_base ;
-       int new_irq = offset + ab8500_gpio->irq_base;
-       return new_irq;
-}
-
-static unsigned int falling_to_irq(unsigned int irq, void *dev)
-{
-       struct ab8500_gpio *ab8500_gpio = dev;
-       int offset = irq - AB8500_INT_GPIO6F
-                       - ab8500_gpio->parent->irq_base ;
-       int new_irq = offset + ab8500_gpio->irq_base;
-       return new_irq;
-
-}
-
-/*
- * IRQ handler
- */
-
-static irqreturn_t handle_rising(int irq, void *dev)
-{
-
-       handle_nested_irq(rising_to_irq(irq , dev));
-       return IRQ_HANDLED;
-}
-
-static irqreturn_t handle_falling(int irq, void *dev)
-{
-
-       handle_nested_irq(falling_to_irq(irq, dev));
-       return IRQ_HANDLED;
-}
-
-static void ab8500_gpio_irq_lock(unsigned int irq)
-{
-       struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
-       mutex_lock(&ab8500_gpio->lock);
-}
-
-static void ab8500_gpio_irq_sync_unlock(unsigned int irq)
-{
-       struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
-       int offset = irq - ab8500_gpio->irq_base;
-       bool rising = ab8500_gpio->rising & BIT(offset);
-       bool falling = ab8500_gpio->falling & BIT(offset);
-       int ret;
-
-       switch (ab8500_gpio->irq_action)        {
-       case STARTUP:
-               if (rising)
-                       ret = request_threaded_irq(irq_to_rising(irq),
-                                       NULL, handle_rising,
-                                       IRQF_TRIGGER_RISING,
-                                       "ab8500-gpio-r", ab8500_gpio);
-               if (falling)
-                       ret = request_threaded_irq(irq_to_falling(irq),
-                                      NULL, handle_falling,
-                                      IRQF_TRIGGER_FALLING,
-                                      "ab8500-gpio-f", ab8500_gpio);
-               break;
-       case SHUTDOWN:
-               if (rising)
-                       free_irq(irq_to_rising(irq), ab8500_gpio);
-               if (falling)
-                       free_irq(irq_to_falling(irq), ab8500_gpio);
-               break;
-       case MASK:
-               if (rising)
-                       disable_irq(irq_to_rising(irq));
-               if (falling)
-                       disable_irq(irq_to_falling(irq));
-               break;
-       case UNMASK:
-               if (rising)
-                       enable_irq(irq_to_rising(irq));
-               if (falling)
-                       enable_irq(irq_to_falling(irq));
-               break;
-       case NONE:
-               break;
-       }
-       ab8500_gpio->irq_action = NONE;
-       ab8500_gpio->rising &= ~(BIT(offset));
-       ab8500_gpio->falling &= ~(BIT(offset));
-       mutex_unlock(&ab8500_gpio->lock);
-}
-
-
-static void ab8500_gpio_irq_mask(unsigned int irq)
-{
-       struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
-       ab8500_gpio->irq_action = MASK;
-}
-
-static void ab8500_gpio_irq_unmask(unsigned int irq)
-{
-       struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
-       ab8500_gpio->irq_action = UNMASK;
-}
-
-static int ab8500_gpio_irq_set_type(unsigned int irq, unsigned int type)
-{
-       struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
-       int offset = irq - ab8500_gpio->irq_base;
-
-       if (type == IRQ_TYPE_EDGE_BOTH) {
-               ab8500_gpio->rising =  BIT(offset);
-               ab8500_gpio->falling = BIT(offset);
-       } else if (type == IRQ_TYPE_EDGE_RISING) {
-               ab8500_gpio->rising =  BIT(offset);
-       } else  {
-               ab8500_gpio->falling = BIT(offset);
-       }
-       return 0;
-}
-
-unsigned int ab8500_gpio_irq_startup(unsigned int irq)
-{
-       struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
-       ab8500_gpio->irq_action = STARTUP;
-       return 0;
-}
-
-void ab8500_gpio_irq_shutdown(unsigned int irq)
-{
-       struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
-       ab8500_gpio->irq_action = SHUTDOWN;
-}
-
-static struct irq_chip ab8500_gpio_irq_chip = {
-       .name                   = "ab8500-gpio",
-       .startup                = ab8500_gpio_irq_startup,
-       .shutdown               = ab8500_gpio_irq_shutdown,
-       .bus_lock               = ab8500_gpio_irq_lock,
-       .bus_sync_unlock        = ab8500_gpio_irq_sync_unlock,
-       .mask                   = ab8500_gpio_irq_mask,
-       .unmask                 = ab8500_gpio_irq_unmask,
-       .set_type               = ab8500_gpio_irq_set_type,
-};
-
-static int ab8500_gpio_irq_init(struct ab8500_gpio *ab8500_gpio)
-{
-       u32 base = ab8500_gpio->irq_base;
-       int irq;
-
-       for (irq = base; irq < base + AB8500_NUM_VIR_GPIO_IRQ ; irq++) {
-               set_irq_chip_data(irq, ab8500_gpio);
-               set_irq_chip_and_handler(irq, &ab8500_gpio_irq_chip,
-                               handle_simple_irq);
-               set_irq_nested_thread(irq, 1);
-#ifdef CONFIG_ARM
-               set_irq_flags(irq, IRQF_VALID);
-#else
-               set_irq_noprobe(irq);
-#endif
-       }
-
-       return 0;
-}
-
-static void ab8500_gpio_irq_remove(struct ab8500_gpio *ab8500_gpio)
-{
-       int base = ab8500_gpio->irq_base;
-       int irq;
-
-       for (irq = base; irq < base + AB8500_NUM_VIR_GPIO_IRQ; irq++) {
-#ifdef CONFIG_ARM
-               set_irq_flags(irq, 0);
-#endif
-               set_irq_chip_and_handler(irq, NULL, NULL);
-               set_irq_chip_data(irq, NULL);
-       }
-}
-
-static int ab8500_gpio_probe(struct platform_device *pdev)
-{
-       struct ab8500_platform_data *ab8500_pdata =
-                               dev_get_platdata(pdev->dev.parent);
-       struct ab8500_gpio_platform_data *pdata;
-       struct ab8500_gpio *ab8500_gpio;
-       int ret;
-       int i;
-
-       pdata = ab8500_pdata->gpio;
-       if (!pdata)     {
-               dev_err(&pdev->dev, "gpio platform data missing\n");
-               return -ENODEV;
-       }
-
-       ab8500_gpio = kzalloc(sizeof(struct ab8500_gpio), GFP_KERNEL);
-       if (ab8500_gpio == NULL) {
-               dev_err(&pdev->dev, "failed to allocate memory\n");
-               return -ENOMEM;
-       }
-       ab8500_gpio->dev = &pdev->dev;
-       ab8500_gpio->parent = dev_get_drvdata(pdev->dev.parent);
-       ab8500_gpio->chip = ab8500gpio_chip;
-       ab8500_gpio->chip.ngpio = AB8500_NUM_GPIO;
-       ab8500_gpio->chip.dev = &pdev->dev;
-       ab8500_gpio->chip.base = pdata->gpio_base;
-       ab8500_gpio->irq_base = pdata->irq_base;
-       /* initialize the lock */
-       mutex_init(&ab8500_gpio->lock);
-       /*
-        * AB8500 core will handle and clear the IRQ
-        * configre GPIO based on config-reg value.
-        * These values are for selecting the PINs as
-        * GPIO or alternate function
-        */
-       for (i = AB8500_GPIO_SEL1_REG; i <= AB8500_GPIO_SEL6_REG; i++)  {
-               ret = abx500_set_register_interruptible(ab8500_gpio->dev,
-                               AB8500_MISC, i,
-                               pdata->config_reg[i]);
-               if (ret < 0)
-                       goto out_free;
-       }
-       ret = abx500_set_register_interruptible(ab8500_gpio->dev, AB8500_MISC,
-                               AB8500_GPIO_ALTFUN_REG,
-                               pdata->config_reg[ALTFUN_REG_INDEX]);
-       if (ret < 0)
-               goto out_free;
-
-       ret = ab8500_gpio_irq_init(ab8500_gpio);
-       if (ret)
-               goto out_free;
-       ret = gpiochip_add(&ab8500_gpio->chip);
-       if (ret) {
-               dev_err(&pdev->dev, "unable to add gpiochip: %d\n",
-                               ret);
-               goto out_rem_irq;
-       }
-       platform_set_drvdata(pdev, ab8500_gpio);
-       return 0;
-
-out_rem_irq:
-       ab8500_gpio_irq_remove(ab8500_gpio);
-out_free:
-       mutex_destroy(&ab8500_gpio->lock);
-       kfree(ab8500_gpio);
-       return ret;
-}
-
-/*
- * ab8500_gpio_remove() - remove Ab8500-gpio driver
- * @pdev :     Platform device registered
- */
-static int ab8500_gpio_remove(struct platform_device *pdev)
-{
-       struct ab8500_gpio *ab8500_gpio = platform_get_drvdata(pdev);
-       int ret;
-
-       ret = gpiochip_remove(&ab8500_gpio->chip);
-       if (ret < 0) {
-               dev_err(ab8500_gpio->dev, "unable to remove gpiochip: %d\n",
-                       ret);
-               return ret;
-       }
-
-       platform_set_drvdata(pdev, NULL);
-       mutex_destroy(&ab8500_gpio->lock);
-       kfree(ab8500_gpio);
-
-       return 0;
-}
-
-static struct platform_driver ab8500_gpio_driver = {
-       .driver = {
-               .name = "ab8500-gpio",
-               .owner = THIS_MODULE,
-       },
-       .probe = ab8500_gpio_probe,
-       .remove = ab8500_gpio_remove,
-};
-
-static int __init ab8500_gpio_init(void)
-{
-       return platform_driver_register(&ab8500_gpio_driver);
-}
-arch_initcall(ab8500_gpio_init);
-
-static void __exit ab8500_gpio_exit(void)
-{
-       platform_driver_unregister(&ab8500_gpio_driver);
-}
-module_exit(ab8500_gpio_exit);
-
-MODULE_AUTHOR("BIBEK BASU <bibek.basu@stericsson.com>");
-MODULE_DESCRIPTION("Driver allows to use AB8500 unused pins to be used as GPIO");
-MODULE_ALIAS("platform:ab8500-gpio");
-MODULE_LICENSE("GPL v2");
index d542a141811a00b2f49589ba8db583b7b30c0ac0..25b1dbe8921d62705c3e76d10d5bb08437bb7d1b 100644 (file)
@@ -250,7 +250,7 @@ static void of_gpiochip_add_pin_range(struct gpio_chip *chip)
                 * on the same GPIO chip.
                 */
                ret = gpiochip_add_pin_range(chip,
-                                            pinctrl_dev_get_name(pctldev),
+                                            pinctrl_dev_get_devname(pctldev),
                                             0, /* offset in gpiochip */
                                             pinspec.args[0],
                                             pinspec.args[1]);
index a5f3c8ca480e1f078d43f0884f1d4a299fccd660..393b0ecf4ca4f21ec3731db30e9531bf7eaa4043 100644 (file)
@@ -26,6 +26,29 @@ config DEBUG_PINCTRL
        help
          Say Y here to add some extra checks and diagnostics to PINCTRL calls.
 
+config PINCTRL_ABX500
+       bool "ST-Ericsson ABx500 family Mixed Signal Circuit gpio functions"
+       depends on AB8500_CORE
+       select GENERIC_PINCONF
+       help
+         Select this to enable the ABx500 family IC GPIO driver
+
+config PINCTRL_AB8500
+       bool "AB8500 pin controller driver"
+       depends on PINCTRL_ABX500 && ARCH_U8500
+
+config PINCTRL_AB8540
+       bool "AB8540 pin controller driver"
+       depends on PINCTRL_ABX500 && ARCH_U8500
+
+config PINCTRL_AB9540
+       bool "AB9540 pin controller driver"
+       depends on PINCTRL_ABX500 && ARCH_U8500
+
+config PINCTRL_AB8505
+       bool "AB8505 pin controller driver"
+       depends on PINCTRL_ABX500 && ARCH_U8500
+
 config PINCTRL_AT91
        bool "AT91 pinctrl driver"
        depends on OF
@@ -151,6 +174,11 @@ config PINCTRL_SIRF
        depends on ARCH_SIRF
        select PINMUX
 
+config PINCTRL_SUNXI
+       bool
+       select PINMUX
+       select GENERIC_PINCONF
+
 config PINCTRL_TEGRA
        bool
        select PINMUX
@@ -164,6 +192,10 @@ config PINCTRL_TEGRA30
        bool
        select PINCTRL_TEGRA
 
+config PINCTRL_TEGRA114
+       bool
+       select PINCTRL_TEGRA
+
 config PINCTRL_U300
        bool "U300 pin controller driver"
        depends on ARCH_U300
index 6e87e52eab5d4a2676e2baec9fee1c6c85b5962e..0fd5f57fcb57f7e935d960de62e2db954f23038c 100644 (file)
@@ -9,6 +9,11 @@ ifeq ($(CONFIG_OF),y)
 obj-$(CONFIG_PINCTRL)          += devicetree.o
 endif
 obj-$(CONFIG_GENERIC_PINCONF)  += pinconf-generic.o
+obj-$(CONFIG_PINCTRL_ABX500)   += pinctrl-abx500.o
+obj-$(CONFIG_PINCTRL_AB8500)   += pinctrl-ab8500.o
+obj-$(CONFIG_PINCTRL_AB8540)   += pinctrl-ab8540.o
+obj-$(CONFIG_PINCTRL_AB9540)   += pinctrl-ab9540.o
+obj-$(CONFIG_PINCTRL_AB8505)   += pinctrl-ab8505.o
 obj-$(CONFIG_PINCTRL_AT91)     += pinctrl-at91.o
 obj-$(CONFIG_PINCTRL_BCM2835)  += pinctrl-bcm2835.o
 obj-$(CONFIG_PINCTRL_IMX)      += pinctrl-imx.o
@@ -30,9 +35,11 @@ obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o
 obj-$(CONFIG_PINCTRL_PXA910)   += pinctrl-pxa910.o
 obj-$(CONFIG_PINCTRL_SINGLE)   += pinctrl-single.o
 obj-$(CONFIG_PINCTRL_SIRF)     += pinctrl-sirf.o
+obj-$(CONFIG_PINCTRL_SUNXI)    += pinctrl-sunxi.o
 obj-$(CONFIG_PINCTRL_TEGRA)    += pinctrl-tegra.o
 obj-$(CONFIG_PINCTRL_TEGRA20)  += pinctrl-tegra20.o
 obj-$(CONFIG_PINCTRL_TEGRA30)  += pinctrl-tegra30.o
+obj-$(CONFIG_PINCTRL_TEGRA114) += pinctrl-tegra114.o
 obj-$(CONFIG_PINCTRL_U300)     += pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_COH901)   += pinctrl-coh901.o
 obj-$(CONFIG_PINCTRL_SAMSUNG)  += pinctrl-samsung.o
index 59f5a965bdc40ad47e566bc1969f236ba06d8689..b0de6e7f1fdb8cb68566b24f04eee8722ab77862 100644 (file)
@@ -14,6 +14,7 @@
 #define pr_fmt(fmt) "pinctrl core: " fmt
 
 #include <linux/kernel.h>
+#include <linux/kref.h>
 #include <linux/export.h>
 #include <linux/init.h>
 #include <linux/device.h>
 #include "pinmux.h"
 #include "pinconf.h"
 
-/**
- * struct pinctrl_maps - a list item containing part of the mapping table
- * @node: mapping table list node
- * @maps: array of mapping table entries
- * @num_maps: the number of entries in @maps
- */
-struct pinctrl_maps {
-       struct list_head node;
-       struct pinctrl_map const *maps;
-       unsigned num_maps;
-};
 
 static bool pinctrl_dummy_state;
 
@@ -55,13 +45,8 @@ LIST_HEAD(pinctrldev_list);
 static LIST_HEAD(pinctrl_list);
 
 /* List of pinctrl maps (struct pinctrl_maps) */
-static LIST_HEAD(pinctrl_maps);
+LIST_HEAD(pinctrl_maps);
 
-#define for_each_maps(_maps_node_, _i_, _map_) \
-       list_for_each_entry(_maps_node_, &pinctrl_maps, node) \
-               for (_i_ = 0, _map_ = &_maps_node_->maps[_i_]; \
-                       _i_ < _maps_node_->num_maps; \
-                       _i_++, _map_ = &_maps_node_->maps[_i_])
 
 /**
  * pinctrl_provide_dummies() - indicate if pinctrl provides dummy state support
@@ -83,6 +68,12 @@ const char *pinctrl_dev_get_name(struct pinctrl_dev *pctldev)
 }
 EXPORT_SYMBOL_GPL(pinctrl_dev_get_name);
 
+const char *pinctrl_dev_get_devname(struct pinctrl_dev *pctldev)
+{
+       return dev_name(pctldev->dev);
+}
+EXPORT_SYMBOL_GPL(pinctrl_dev_get_devname);
+
 void *pinctrl_dev_get_drvdata(struct pinctrl_dev *pctldev)
 {
        return pctldev->driver_data;
@@ -609,13 +600,16 @@ static int add_setting(struct pinctrl *p, struct pinctrl_map const *map)
 
        setting->pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name);
        if (setting->pctldev == NULL) {
-               dev_info(p->dev, "unknown pinctrl device %s in map entry, deferring probe",
-                       map->ctrl_dev_name);
                kfree(setting);
+               /* Do not defer probing of hogs (circular loop) */
+               if (!strcmp(map->ctrl_dev_name, map->dev_name))
+                       return -ENODEV;
                /*
                 * OK let us guess that the driver is not there yet, and
                 * let's defer obtaining this pinctrl handle to later...
                 */
+               dev_info(p->dev, "unknown pinctrl device %s in map entry, deferring probe",
+                       map->ctrl_dev_name);
                return -EPROBE_DEFER;
        }
 
@@ -694,11 +688,31 @@ static struct pinctrl *create_pinctrl(struct device *dev)
                        continue;
 
                ret = add_setting(p, map);
-               if (ret < 0) {
+               /*
+                * At this point the adding of a setting may:
+                *
+                * - Defer, if the pinctrl device is not yet available
+                * - Fail, if the pinctrl device is not yet available,
+                *   AND the setting is a hog. We cannot defer that, since
+                *   the hog will kick in immediately after the device
+                *   is registered.
+                *
+                * If the error returned was not -EPROBE_DEFER then we
+                * accumulate the errors to see if we end up with
+                * an -EPROBE_DEFER later, as that is the worst case.
+                */
+               if (ret == -EPROBE_DEFER) {
                        pinctrl_put_locked(p, false);
                        return ERR_PTR(ret);
                }
        }
+       if (ret < 0) {
+               /* If some other error than deferral occured, return here */
+               pinctrl_put_locked(p, false);
+               return ERR_PTR(ret);
+       }
+
+       kref_init(&p->users);
 
        /* Add the pinctrl handle to the global list */
        list_add_tail(&p->node, &pinctrl_list);
@@ -713,9 +727,17 @@ static struct pinctrl *pinctrl_get_locked(struct device *dev)
        if (WARN_ON(!dev))
                return ERR_PTR(-EINVAL);
 
+       /*
+        * See if somebody else (such as the device core) has already
+        * obtained a handle to the pinctrl for this device. In that case,
+        * return another pointer to it.
+        */
        p = find_pinctrl(dev);
-       if (p != NULL)
-               return ERR_PTR(-EBUSY);
+       if (p != NULL) {
+               dev_dbg(dev, "obtain a copy of previously claimed pinctrl\n");
+               kref_get(&p->users);
+               return p;
+       }
 
        return create_pinctrl(dev);
 }
@@ -771,13 +793,24 @@ static void pinctrl_put_locked(struct pinctrl *p, bool inlist)
 }
 
 /**
- * pinctrl_put() - release a previously claimed pinctrl handle
+ * pinctrl_release() - release the pinctrl handle
+ * @kref: the kref in the pinctrl being released
+ */
+static void pinctrl_release(struct kref *kref)
+{
+       struct pinctrl *p = container_of(kref, struct pinctrl, users);
+
+       pinctrl_put_locked(p, true);
+}
+
+/**
+ * pinctrl_put() - decrease use count on a previously claimed pinctrl handle
  * @p: the pinctrl handle to release
  */
 void pinctrl_put(struct pinctrl *p)
 {
        mutex_lock(&pinctrl_mutex);
-       pinctrl_put_locked(p, true);
+       kref_put(&p->users, pinctrl_release);
        mutex_unlock(&pinctrl_mutex);
 }
 EXPORT_SYMBOL_GPL(pinctrl_put);
@@ -1055,6 +1088,30 @@ void pinctrl_unregister_map(struct pinctrl_map const *map)
        }
 }
 
+/**
+ * pinctrl_force_sleep() - turn a given controller device into sleep state
+ * @pctldev: pin controller device
+ */
+int pinctrl_force_sleep(struct pinctrl_dev *pctldev)
+{
+       if (!IS_ERR(pctldev->p) && !IS_ERR(pctldev->hog_sleep))
+               return pinctrl_select_state(pctldev->p, pctldev->hog_sleep);
+       return 0;
+}
+EXPORT_SYMBOL_GPL(pinctrl_force_sleep);
+
+/**
+ * pinctrl_force_default() - turn a given controller device into default state
+ * @pctldev: pin controller device
+ */
+int pinctrl_force_default(struct pinctrl_dev *pctldev)
+{
+       if (!IS_ERR(pctldev->p) && !IS_ERR(pctldev->hog_default))
+               return pinctrl_select_state(pctldev->p, pctldev->hog_default);
+       return 0;
+}
+EXPORT_SYMBOL_GPL(pinctrl_force_default);
+
 #ifdef CONFIG_DEBUG_FS
 
 static int pinctrl_pins_show(struct seq_file *s, void *what)
@@ -1500,16 +1557,23 @@ struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
 
        pctldev->p = pinctrl_get_locked(pctldev->dev);
        if (!IS_ERR(pctldev->p)) {
-               struct pinctrl_state *s =
+               pctldev->hog_default =
                        pinctrl_lookup_state_locked(pctldev->p,
                                                    PINCTRL_STATE_DEFAULT);
-               if (IS_ERR(s)) {
+               if (IS_ERR(pctldev->hog_default)) {
                        dev_dbg(dev, "failed to lookup the default state\n");
                } else {
-                       if (pinctrl_select_state_locked(pctldev->p, s))
+                       if (pinctrl_select_state_locked(pctldev->p,
+                                               pctldev->hog_default))
                                dev_err(dev,
                                        "failed to select default state\n");
                }
+
+               pctldev->hog_sleep =
+                       pinctrl_lookup_state_locked(pctldev->p,
+                                                   PINCTRL_STATE_SLEEP);
+               if (IS_ERR(pctldev->hog_sleep))
+                       dev_dbg(dev, "failed to lookup the sleep state\n");
        }
 
        mutex_unlock(&pinctrl_mutex);
index 12f5694f3d5d9f02020cd2369603d6202e488b24..ee72f1f6d86239ac91ba6e29be716356502ced5b 100644 (file)
@@ -9,6 +9,7 @@
  * License terms: GNU General Public License (GPL) version 2
  */
 
+#include <linux/kref.h>
 #include <linux/mutex.h>
 #include <linux/radix-tree.h>
 #include <linux/pinctrl/pinconf.h>
@@ -30,6 +31,8 @@ struct pinctrl_gpio_range;
  * @driver_data: driver data for drivers registering to the pin controller
  *     subsystem
  * @p: result of pinctrl_get() for this device
+ * @hog_default: default state for pins hogged by this device
+ * @hog_sleep: sleep state for pins hogged by this device
  * @device_root: debugfs root for this device
  */
 struct pinctrl_dev {
@@ -41,6 +44,8 @@ struct pinctrl_dev {
        struct module *owner;
        void *driver_data;
        struct pinctrl *p;
+       struct pinctrl_state *hog_default;
+       struct pinctrl_state *hog_sleep;
 #ifdef CONFIG_DEBUG_FS
        struct dentry *device_root;
 #endif
@@ -54,6 +59,7 @@ struct pinctrl_dev {
  * @state: the current state
  * @dt_maps: the mapping table chunks dynamically parsed from device tree for
  *     this device, if any
+ * @users: reference count
  */
 struct pinctrl {
        struct list_head node;
@@ -61,6 +67,7 @@ struct pinctrl {
        struct list_head states;
        struct pinctrl_state *state;
        struct list_head dt_maps;
+       struct kref users;
 };
 
 /**
@@ -148,6 +155,18 @@ struct pin_desc {
 #endif
 };
 
+/**
+ * struct pinctrl_maps - a list item containing part of the mapping table
+ * @node: mapping table list node
+ * @maps: array of mapping table entries
+ * @num_maps: the number of entries in @maps
+ */
+struct pinctrl_maps {
+       struct list_head node;
+       struct pinctrl_map const *maps;
+       unsigned num_maps;
+};
+
 struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *dev_name);
 int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name);
 const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin);
@@ -164,5 +183,15 @@ int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps,
                         bool dup, bool locked);
 void pinctrl_unregister_map(struct pinctrl_map const *map);
 
+extern int pinctrl_force_sleep(struct pinctrl_dev *pctldev);
+extern int pinctrl_force_default(struct pinctrl_dev *pctldev);
+
 extern struct mutex pinctrl_mutex;
 extern struct list_head pinctrldev_list;
+extern struct list_head pinctrl_maps;
+
+#define for_each_maps(_maps_node_, _i_, _map_) \
+       list_for_each_entry(_maps_node_, &pinctrl_maps, node) \
+               for (_i_ = 0, _map_ = &_maps_node_->maps[_i_]; \
+                       _i_ < _maps_node_->num_maps; \
+                       _i_++, _map_ = &_maps_node_->maps[_i_])
index fe2d1af7cfa0d0bce2eeb8a8391a4567da70bdd8..fd40a11ad645a38e9a82739c9d0aaa58124db0d0 100644 (file)
@@ -141,6 +141,11 @@ static int dt_to_map_one_config(struct pinctrl *p, const char *statename,
                pctldev = find_pinctrl_by_of_node(np_pctldev);
                if (pctldev)
                        break;
+               /* Do not defer probing of hogs (circular loop) */
+               if (np_pctldev == p->dev->of_node) {
+                       of_node_put(np_pctldev);
+                       return -ENODEV;
+               }
        }
        of_node_put(np_pctldev);
 
index 833a36458157dd4c15ce0361ee84ced454cd93f4..06c304ac6f7da2794d38e380bdd51a8a91736182 100644 (file)
@@ -41,11 +41,13 @@ struct pin_config_item conf_items[] = {
        PCONFDUMP(PIN_CONFIG_DRIVE_PUSH_PULL, "output drive push pull", NULL),
        PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_DRAIN, "output drive open drain", NULL),
        PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_SOURCE, "output drive open source", NULL),
-       PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_DISABLE, "input schmitt disabled", NULL),
+       PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_ENABLE, "input schmitt enabled", NULL),
        PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT, "input schmitt trigger", NULL),
        PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE, "input debounce", "time units"),
        PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector"),
+       PCONFDUMP(PIN_CONFIG_SLEW_RATE, "slew rate", NULL),
        PCONFDUMP(PIN_CONFIG_LOW_POWER_MODE, "pin low power", "mode"),
+       PCONFDUMP(PIN_CONFIG_OUTPUT, "pin output", "level"),
 };
 
 void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev,
index baee2cc46a17a7c5c328f98c7eaa25f8f10d8fba..ac8d382a79bbfe43de8769ea43d1c13ab2fac036 100644 (file)
@@ -574,6 +574,207 @@ static const struct file_operations pinconf_groups_ops = {
        .release        = single_release,
 };
 
+/* 32bit read/write ressources */
+#define MAX_NAME_LEN 16
+char dbg_pinname[MAX_NAME_LEN]; /* shared: name of the state of the pin*/
+char dbg_state_name[MAX_NAME_LEN]; /* shared: state of the pin*/
+static u32 dbg_config; /* shared: config to be read/set for the pin & state*/
+
+static int pinconf_dbg_pinname_print(struct seq_file *s, void *d)
+{
+       if (strlen(dbg_pinname))
+               seq_printf(s, "%s\n", dbg_pinname);
+       else
+               seq_printf(s, "No pin name set\n");
+       return 0;
+}
+
+static int pinconf_dbg_pinname_open(struct inode *inode, struct file *file)
+{
+       return single_open(file, pinconf_dbg_pinname_print, inode->i_private);
+}
+
+static int pinconf_dbg_pinname_write(struct file *file,
+       const char __user *user_buf, size_t count, loff_t *ppos)
+{
+       int err;
+
+       if (count > MAX_NAME_LEN)
+               return -EINVAL;
+
+       err = sscanf(user_buf, "%15s", dbg_pinname);
+
+       if (err != 1)
+               return -EINVAL;
+
+       return count;
+}
+
+static const struct file_operations pinconf_dbg_pinname_fops = {
+       .open = pinconf_dbg_pinname_open,
+       .write = pinconf_dbg_pinname_write,
+       .read = seq_read,
+       .llseek = seq_lseek,
+       .release = single_release,
+       .owner = THIS_MODULE,
+};
+
+static int pinconf_dbg_state_print(struct seq_file *s, void *d)
+{
+       if (strlen(dbg_state_name))
+               seq_printf(s, "%s\n", dbg_pinname);
+       else
+               seq_printf(s, "No pin state set\n");
+       return 0;
+}
+
+static int pinconf_dbg_state_open(struct inode *inode, struct file *file)
+{
+       return single_open(file, pinconf_dbg_state_print, inode->i_private);
+}
+
+static int pinconf_dbg_state_write(struct file *file,
+       const char __user *user_buf, size_t count, loff_t *ppos)
+{
+       int err;
+
+       if (count > MAX_NAME_LEN)
+               return -EINVAL;
+
+       err = sscanf(user_buf, "%15s", dbg_state_name);
+
+       if (err != 1)
+               return -EINVAL;
+
+       return count;
+}
+
+static const struct file_operations pinconf_dbg_pinstate_fops = {
+       .open = pinconf_dbg_state_open,
+       .write = pinconf_dbg_state_write,
+       .read = seq_read,
+       .llseek = seq_lseek,
+       .release = single_release,
+       .owner = THIS_MODULE,
+};
+
+/**
+ * pinconf_dbg_config_print() - display the pinctrl config from the pinctrl
+ * map, of a pin/state pair based on pinname and state that have been
+ * selected with the debugfs entries pinconf-name and pinconf-state
+ * @s: contains the 32bits config to be written
+ * @d: not used
+ */
+static int pinconf_dbg_config_print(struct seq_file *s, void *d)
+{
+       struct pinctrl_maps *maps_node;
+       struct pinctrl_map const *map;
+       struct pinctrl_dev *pctldev = NULL;
+       struct pinconf_ops *confops = NULL;
+       int i, j;
+       bool found = false;
+
+       mutex_lock(&pinctrl_mutex);
+
+       /* Parse the pinctrl map and look for the elected pin/state */
+       for_each_maps(maps_node, i, map) {
+               if (map->type != PIN_MAP_TYPE_CONFIGS_PIN)
+                       continue;
+
+               if (strncmp(map->name, dbg_state_name, MAX_NAME_LEN) > 0)
+                       continue;
+
+               for (j = 0; j < map->data.configs.num_configs; j++) {
+                       if (0 == strncmp(map->data.configs.group_or_pin,
+                                               dbg_pinname, MAX_NAME_LEN)) {
+                               /* We found the right pin / state, read the
+                                * config and store the pctldev */
+                               dbg_config = map->data.configs.configs[j];
+                               pctldev = get_pinctrl_dev_from_devname
+                                       (map->ctrl_dev_name);
+                               found = true;
+                               break;
+                       }
+               }
+       }
+
+       mutex_unlock(&pinctrl_mutex);
+
+       if (found) {
+               seq_printf(s, "Config of %s in state %s: 0x%08X\n", dbg_pinname,
+                                dbg_state_name, dbg_config);
+
+               if (pctldev)
+                       confops = pctldev->desc->confops;
+
+               if (confops && confops->pin_config_config_dbg_show)
+                       confops->pin_config_config_dbg_show(pctldev,
+                                       s, dbg_config);
+       } else {
+               seq_printf(s, "No pin found for defined name/state\n");
+       }
+
+       return 0;
+}
+
+static int pinconf_dbg_config_open(struct inode *inode, struct file *file)
+{
+       return single_open(file, pinconf_dbg_config_print, inode->i_private);
+}
+
+/**
+ * pinconf_dbg_config_write() - overwrite the pinctrl config in thepinctrl
+ * map, of a pin/state pair based on pinname and state that have been
+ * selected with the debugfs entries pinconf-name and pinconf-state
+ */
+static int pinconf_dbg_config_write(struct file *file,
+       const char __user *user_buf, size_t count, loff_t *ppos)
+{
+       int err;
+       unsigned long config;
+       struct pinctrl_maps *maps_node;
+       struct pinctrl_map const *map;
+       int i, j;
+
+       err = kstrtoul_from_user(user_buf, count, 0, &config);
+
+       if (err)
+               return err;
+
+       dbg_config = config;
+
+       mutex_lock(&pinctrl_mutex);
+
+       /* Parse the pinctrl map and look for the selected pin/state */
+       for_each_maps(maps_node, i, map) {
+               if (map->type != PIN_MAP_TYPE_CONFIGS_PIN)
+                       continue;
+
+               if (strncmp(map->name, dbg_state_name, MAX_NAME_LEN) > 0)
+                       continue;
+
+               /*  we found the right pin / state, so overwrite config */
+               for (j = 0; j < map->data.configs.num_configs; j++) {
+                       if (strncmp(map->data.configs.group_or_pin, dbg_pinname,
+                                               MAX_NAME_LEN) == 0)
+                               map->data.configs.configs[j] = dbg_config;
+               }
+       }
+
+       mutex_unlock(&pinctrl_mutex);
+
+       return count;
+}
+
+static const struct file_operations pinconf_dbg_pinconfig_fops = {
+       .open = pinconf_dbg_config_open,
+       .write = pinconf_dbg_config_write,
+       .read = seq_read,
+       .llseek = seq_lseek,
+       .release = single_release,
+       .owner = THIS_MODULE,
+};
+
 void pinconf_init_device_debugfs(struct dentry *devroot,
                         struct pinctrl_dev *pctldev)
 {
@@ -581,6 +782,12 @@ void pinconf_init_device_debugfs(struct dentry *devroot,
                            devroot, pctldev, &pinconf_pins_ops);
        debugfs_create_file("pinconf-groups", S_IFREG | S_IRUGO,
                            devroot, pctldev, &pinconf_groups_ops);
+       debugfs_create_file("pinconf-name", (S_IRUGO | S_IWUSR | S_IWGRP),
+                           devroot, pctldev, &pinconf_dbg_pinname_fops);
+       debugfs_create_file("pinconf-state",  (S_IRUGO | S_IWUSR | S_IWGRP),
+                           devroot, pctldev, &pinconf_dbg_pinstate_fops);
+       debugfs_create_file("pinconf-config",  (S_IRUGO | S_IWUSR | S_IWGRP),
+                           devroot, pctldev, &pinconf_dbg_pinconfig_fops);
 }
 
 #endif
diff --git a/drivers/pinctrl/pinctrl-ab8500.c b/drivers/pinctrl/pinctrl-ab8500.c
new file mode 100644 (file)
index 0000000..3b471d8
--- /dev/null
@@ -0,0 +1,484 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2012
+ *
+ * Author: Patrice Chotard <patrice.chotard@stericsson.com> for ST-Ericsson.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/mfd/abx500/ab8500.h>
+#include "pinctrl-abx500.h"
+
+/* All the pins that can be used for GPIO and some other functions */
+#define ABX500_GPIO(offset)            (offset)
+
+#define AB8500_PIN_T10         ABX500_GPIO(1)
+#define AB8500_PIN_T9          ABX500_GPIO(2)
+#define AB8500_PIN_U9          ABX500_GPIO(3)
+#define AB8500_PIN_W2          ABX500_GPIO(4)
+/* hole */
+#define AB8500_PIN_Y18         ABX500_GPIO(6)
+#define AB8500_PIN_AA20                ABX500_GPIO(7)
+#define AB8500_PIN_W18         ABX500_GPIO(8)
+#define AB8500_PIN_AA19                ABX500_GPIO(9)
+#define AB8500_PIN_U17         ABX500_GPIO(10)
+#define AB8500_PIN_AA18                ABX500_GPIO(11)
+#define AB8500_PIN_U16         ABX500_GPIO(12)
+#define AB8500_PIN_W17         ABX500_GPIO(13)
+#define AB8500_PIN_F14         ABX500_GPIO(14)
+#define AB8500_PIN_B17         ABX500_GPIO(15)
+#define AB8500_PIN_F15         ABX500_GPIO(16)
+#define AB8500_PIN_P5          ABX500_GPIO(17)
+#define AB8500_PIN_R5          ABX500_GPIO(18)
+#define AB8500_PIN_U5          ABX500_GPIO(19)
+#define AB8500_PIN_T5          ABX500_GPIO(20)
+#define AB8500_PIN_H19         ABX500_GPIO(21)
+#define AB8500_PIN_G20         ABX500_GPIO(22)
+#define AB8500_PIN_G19         ABX500_GPIO(23)
+#define AB8500_PIN_T14         ABX500_GPIO(24)
+#define AB8500_PIN_R16         ABX500_GPIO(25)
+#define AB8500_PIN_M16         ABX500_GPIO(26)
+#define AB8500_PIN_J6          ABX500_GPIO(27)
+#define AB8500_PIN_K6          ABX500_GPIO(28)
+#define AB8500_PIN_G6          ABX500_GPIO(29)
+#define AB8500_PIN_H6          ABX500_GPIO(30)
+#define AB8500_PIN_F5          ABX500_GPIO(31)
+#define AB8500_PIN_G5          ABX500_GPIO(32)
+/* hole */
+#define AB8500_PIN_R17         ABX500_GPIO(34)
+#define AB8500_PIN_W15         ABX500_GPIO(35)
+#define AB8500_PIN_A17         ABX500_GPIO(36)
+#define AB8500_PIN_E15         ABX500_GPIO(37)
+#define AB8500_PIN_C17         ABX500_GPIO(38)
+#define AB8500_PIN_E16         ABX500_GPIO(39)
+#define AB8500_PIN_T19         ABX500_GPIO(40)
+#define AB8500_PIN_U19         ABX500_GPIO(41)
+#define AB8500_PIN_U2          ABX500_GPIO(42)
+
+/* indicates the highest GPIO number */
+#define AB8500_GPIO_MAX_NUMBER 42
+
+/*
+ * The names of the pins are denoted by GPIO number and ball name, even
+ * though they can be used for other things than GPIO, this is the first
+ * column in the table of the data sheet and often used on schematics and
+ * such.
+ */
+static const struct pinctrl_pin_desc ab8500_pins[] = {
+       PINCTRL_PIN(AB8500_PIN_T10, "GPIO1_T10"),
+       PINCTRL_PIN(AB8500_PIN_T9, "GPIO2_T9"),
+       PINCTRL_PIN(AB8500_PIN_U9, "GPIO3_U9"),
+       PINCTRL_PIN(AB8500_PIN_W2, "GPIO4_W2"),
+       /* hole */
+       PINCTRL_PIN(AB8500_PIN_Y18, "GPIO6_Y18"),
+       PINCTRL_PIN(AB8500_PIN_AA20, "GPIO7_AA20"),
+       PINCTRL_PIN(AB8500_PIN_W18, "GPIO8_W18"),
+       PINCTRL_PIN(AB8500_PIN_AA19, "GPIO9_AA19"),
+       PINCTRL_PIN(AB8500_PIN_U17, "GPIO10_U17"),
+       PINCTRL_PIN(AB8500_PIN_AA18, "GPIO11_AA18"),
+       PINCTRL_PIN(AB8500_PIN_U16, "GPIO12_U16"),
+       PINCTRL_PIN(AB8500_PIN_W17, "GPIO13_W17"),
+       PINCTRL_PIN(AB8500_PIN_F14, "GPIO14_F14"),
+       PINCTRL_PIN(AB8500_PIN_B17, "GPIO15_B17"),
+       PINCTRL_PIN(AB8500_PIN_F15, "GPIO16_F15"),
+       PINCTRL_PIN(AB8500_PIN_P5, "GPIO17_P5"),
+       PINCTRL_PIN(AB8500_PIN_R5, "GPIO18_R5"),
+       PINCTRL_PIN(AB8500_PIN_U5, "GPIO19_U5"),
+       PINCTRL_PIN(AB8500_PIN_T5, "GPIO20_T5"),
+       PINCTRL_PIN(AB8500_PIN_H19, "GPIO21_H19"),
+       PINCTRL_PIN(AB8500_PIN_G20, "GPIO22_G20"),
+       PINCTRL_PIN(AB8500_PIN_G19, "GPIO23_G19"),
+       PINCTRL_PIN(AB8500_PIN_T14, "GPIO24_T14"),
+       PINCTRL_PIN(AB8500_PIN_R16, "GPIO25_R16"),
+       PINCTRL_PIN(AB8500_PIN_M16, "GPIO26_M16"),
+       PINCTRL_PIN(AB8500_PIN_J6, "GPIO27_J6"),
+       PINCTRL_PIN(AB8500_PIN_K6, "GPIO28_K6"),
+       PINCTRL_PIN(AB8500_PIN_G6, "GPIO29_G6"),
+       PINCTRL_PIN(AB8500_PIN_H6, "GPIO30_H6"),
+       PINCTRL_PIN(AB8500_PIN_F5, "GPIO31_F5"),
+       PINCTRL_PIN(AB8500_PIN_G5, "GPIO32_G5"),
+       /* hole */
+       PINCTRL_PIN(AB8500_PIN_R17, "GPIO34_R17"),
+       PINCTRL_PIN(AB8500_PIN_W15, "GPIO35_W15"),
+       PINCTRL_PIN(AB8500_PIN_A17, "GPIO36_A17"),
+       PINCTRL_PIN(AB8500_PIN_E15, "GPIO37_E15"),
+       PINCTRL_PIN(AB8500_PIN_C17, "GPIO38_C17"),
+       PINCTRL_PIN(AB8500_PIN_E16, "GPIO39_E16"),
+       PINCTRL_PIN(AB8500_PIN_T19, "GPIO40_T19"),
+       PINCTRL_PIN(AB8500_PIN_U19, "GPIO41_U19"),
+       PINCTRL_PIN(AB8500_PIN_U2, "GPIO42_U2"),
+};
+
+/*
+ * Maps local GPIO offsets to local pin numbers
+ */
+static const struct abx500_pinrange ab8500_pinranges[] = {
+       ABX500_PINRANGE(1, 4, ABX500_ALT_A),
+       ABX500_PINRANGE(6, 4, ABX500_ALT_A),
+       ABX500_PINRANGE(10, 4, ABX500_DEFAULT),
+       ABX500_PINRANGE(14, 12, ABX500_ALT_A),
+       ABX500_PINRANGE(26, 1, ABX500_DEFAULT),
+       ABX500_PINRANGE(27, 6, ABX500_ALT_A),
+       ABX500_PINRANGE(34, 1, ABX500_ALT_A),
+       ABX500_PINRANGE(35, 1, ABX500_DEFAULT),
+       ABX500_PINRANGE(36, 7, ABX500_ALT_A),
+};
+
+/*
+ * Read the pin group names like this:
+ * sysclkreq2_d_1 = first groups of pins for sysclkreq2 on default function
+ *
+ * The groups are arranged as sets per altfunction column, so we can
+ * mux in one group at a time by selecting the same altfunction for them
+ * all. When functions require pins on different altfunctions, you need
+ * to combine several groups.
+ */
+
+/* default column */
+static const unsigned sysclkreq2_d_1_pins[] = { AB8500_PIN_T10 };
+static const unsigned sysclkreq3_d_1_pins[] = { AB8500_PIN_T9 };
+static const unsigned sysclkreq4_d_1_pins[] = { AB8500_PIN_U9 };
+static const unsigned sysclkreq6_d_1_pins[] = { AB8500_PIN_W2 };
+static const unsigned ycbcr0123_d_1_pins[] = { AB8500_PIN_Y18, AB8500_PIN_AA20,
+                                       AB8500_PIN_W18, AB8500_PIN_AA19};
+static const unsigned gpio10_d_1_pins[] = { AB8500_PIN_U17 };
+static const unsigned gpio11_d_1_pins[] = { AB8500_PIN_AA18 };
+static const unsigned gpio12_d_1_pins[] = { AB8500_PIN_U16 };
+static const unsigned gpio13_d_1_pins[] = { AB8500_PIN_W17 };
+static const unsigned pwmout1_d_1_pins[] = { AB8500_PIN_F14 };
+static const unsigned pwmout2_d_1_pins[] = { AB8500_PIN_B17 };
+static const unsigned pwmout3_d_1_pins[] = { AB8500_PIN_F15 };
+
+/* audio data interface 1*/
+static const unsigned adi1_d_1_pins[] = { AB8500_PIN_P5, AB8500_PIN_R5,
+                                       AB8500_PIN_U5, AB8500_PIN_T5 };
+/* USBUICC */
+static const unsigned usbuicc_d_1_pins[] = { AB8500_PIN_H19, AB8500_PIN_G20,
+                                       AB8500_PIN_G19 };
+static const unsigned sysclkreq7_d_1_pins[] = { AB8500_PIN_T14 };
+static const unsigned sysclkreq8_d_1_pins[] = { AB8500_PIN_R16 };
+static const unsigned gpio26_d_1_pins[] = { AB8500_PIN_M16 };
+/* Digital microphone 1 and 2 */
+static const unsigned dmic12_d_1_pins[] = { AB8500_PIN_J6, AB8500_PIN_K6 };
+/* Digital microphone 3 and 4 */
+static const unsigned dmic34_d_1_pins[] = { AB8500_PIN_G6, AB8500_PIN_H6 };
+/* Digital microphone 5 and 6 */
+static const unsigned dmic56_d_1_pins[] = { AB8500_PIN_F5, AB8500_PIN_G5 };
+static const unsigned extcpena_d_1_pins[] = { AB8500_PIN_R17 };
+static const unsigned gpio35_d_1_pins[] = { AB8500_PIN_W15 };
+/* APE SPI */
+static const unsigned apespi_d_1_pins[] = { AB8500_PIN_A17, AB8500_PIN_E15,
+                                       AB8500_PIN_C17, AB8500_PIN_E16};
+/* modem SDA/SCL */
+static const unsigned modsclsda_d_1_pins[] = { AB8500_PIN_T19, AB8500_PIN_U19 };
+static const unsigned sysclkreq5_d_1_pins[] = { AB8500_PIN_U2 };
+
+/* Altfunction A column */
+static const unsigned gpio1_a_1_pins[] = { AB8500_PIN_T10 };
+static const unsigned gpio2_a_1_pins[] = { AB8500_PIN_T9 };
+static const unsigned gpio3_a_1_pins[] = { AB8500_PIN_U9 };
+static const unsigned gpio4_a_1_pins[] = { AB8500_PIN_W2 };
+static const unsigned gpio6_a_1_pins[] = { AB8500_PIN_Y18 };
+static const unsigned gpio7_a_1_pins[] = { AB8500_PIN_AA20 };
+static const unsigned gpio8_a_1_pins[] = { AB8500_PIN_W18 };
+static const unsigned gpio9_a_1_pins[] = { AB8500_PIN_AA19 };
+/* YCbCr4 YCbCr5 YCbCr6 YCbCr7*/
+static const unsigned ycbcr4567_a_1_pins[] = { AB8500_PIN_U17, AB8500_PIN_AA18,
+                                       AB8500_PIN_U16, AB8500_PIN_W17};
+static const unsigned gpio14_a_1_pins[] = { AB8500_PIN_F14 };
+static const unsigned gpio15_a_1_pins[] = { AB8500_PIN_B17 };
+static const unsigned gpio16_a_1_pins[] = { AB8500_PIN_F15 };
+static const unsigned gpio17_a_1_pins[] = { AB8500_PIN_P5 };
+static const unsigned gpio18_a_1_pins[] = { AB8500_PIN_R5 };
+static const unsigned gpio19_a_1_pins[] = { AB8500_PIN_U5 };
+static const unsigned gpio20_a_1_pins[] = { AB8500_PIN_T5 };
+static const unsigned gpio21_a_1_pins[] = { AB8500_PIN_H19 };
+static const unsigned gpio22_a_1_pins[] = { AB8500_PIN_G20 };
+static const unsigned gpio23_a_1_pins[] = { AB8500_PIN_G19 };
+static const unsigned gpio24_a_1_pins[] = { AB8500_PIN_T14 };
+static const unsigned gpio25_a_1_pins[] = { AB8500_PIN_R16 };
+static const unsigned gpio27_a_1_pins[] = { AB8500_PIN_J6 };
+static const unsigned gpio28_a_1_pins[] = { AB8500_PIN_K6 };
+static const unsigned gpio29_a_1_pins[] = { AB8500_PIN_G6 };
+static const unsigned gpio30_a_1_pins[] = { AB8500_PIN_H6 };
+static const unsigned gpio31_a_1_pins[] = { AB8500_PIN_F5 };
+static const unsigned gpio32_a_1_pins[] = { AB8500_PIN_G5 };
+static const unsigned gpio34_a_1_pins[] = { AB8500_PIN_R17 };
+static const unsigned gpio36_a_1_pins[] = { AB8500_PIN_A17 };
+static const unsigned gpio37_a_1_pins[] = { AB8500_PIN_E15 };
+static const unsigned gpio38_a_1_pins[] = { AB8500_PIN_C17 };
+static const unsigned gpio39_a_1_pins[] = { AB8500_PIN_E16 };
+static const unsigned gpio40_a_1_pins[] = { AB8500_PIN_T19 };
+static const unsigned gpio41_a_1_pins[] = { AB8500_PIN_U19 };
+static const unsigned gpio42_a_1_pins[] = { AB8500_PIN_U2 };
+
+/* Altfunction B colum */
+static const unsigned hiqclkena_b_1_pins[] = { AB8500_PIN_U17 };
+static const unsigned usbuiccpd_b_1_pins[] = { AB8500_PIN_AA18 };
+static const unsigned i2ctrig1_b_1_pins[] = { AB8500_PIN_U16 };
+static const unsigned i2ctrig2_b_1_pins[] = { AB8500_PIN_W17 };
+
+/* Altfunction C column */
+static const unsigned usbvdat_c_1_pins[] = { AB8500_PIN_W17 };
+
+
+#define AB8500_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins,         \
+                       .npins = ARRAY_SIZE(a##_pins), .altsetting = b }
+
+static const struct abx500_pingroup ab8500_groups[] = {
+       /* default column */
+       AB8500_PIN_GROUP(sysclkreq2_d_1, ABX500_DEFAULT),
+       AB8500_PIN_GROUP(sysclkreq3_d_1, ABX500_DEFAULT),
+       AB8500_PIN_GROUP(sysclkreq4_d_1, ABX500_DEFAULT),
+       AB8500_PIN_GROUP(sysclkreq6_d_1, ABX500_DEFAULT),
+       AB8500_PIN_GROUP(ycbcr0123_d_1, ABX500_DEFAULT),
+       AB8500_PIN_GROUP(gpio10_d_1, ABX500_DEFAULT),
+       AB8500_PIN_GROUP(gpio11_d_1, ABX500_DEFAULT),
+       AB8500_PIN_GROUP(gpio12_d_1, ABX500_DEFAULT),
+       AB8500_PIN_GROUP(gpio13_d_1, ABX500_DEFAULT),
+       AB8500_PIN_GROUP(pwmout1_d_1, ABX500_DEFAULT),
+       AB8500_PIN_GROUP(pwmout2_d_1, ABX500_DEFAULT),
+       AB8500_PIN_GROUP(pwmout3_d_1, ABX500_DEFAULT),
+       AB8500_PIN_GROUP(adi1_d_1, ABX500_DEFAULT),
+       AB8500_PIN_GROUP(usbuicc_d_1, ABX500_DEFAULT),
+       AB8500_PIN_GROUP(sysclkreq7_d_1, ABX500_DEFAULT),
+       AB8500_PIN_GROUP(sysclkreq8_d_1, ABX500_DEFAULT),
+       AB8500_PIN_GROUP(gpio26_d_1, ABX500_DEFAULT),
+       AB8500_PIN_GROUP(dmic12_d_1, ABX500_DEFAULT),
+       AB8500_PIN_GROUP(dmic34_d_1, ABX500_DEFAULT),
+       AB8500_PIN_GROUP(dmic56_d_1, ABX500_DEFAULT),
+       AB8500_PIN_GROUP(extcpena_d_1, ABX500_DEFAULT),
+       AB8500_PIN_GROUP(gpio35_d_1, ABX500_DEFAULT),
+       AB8500_PIN_GROUP(apespi_d_1, ABX500_DEFAULT),
+       AB8500_PIN_GROUP(modsclsda_d_1, ABX500_DEFAULT),
+       AB8500_PIN_GROUP(sysclkreq5_d_1, ABX500_DEFAULT),
+       /* Altfunction A column */
+       AB8500_PIN_GROUP(gpio1_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(gpio2_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(gpio3_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(gpio4_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(gpio6_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(gpio7_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(gpio8_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(gpio9_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(ycbcr4567_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(gpio14_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(gpio15_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(gpio16_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(gpio17_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(gpio18_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(gpio19_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(gpio20_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(gpio21_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(gpio22_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(gpio23_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(gpio24_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(gpio25_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(gpio27_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(gpio28_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(gpio29_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(gpio30_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(gpio31_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(gpio32_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(gpio34_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(gpio36_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(gpio37_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(gpio38_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(gpio39_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(gpio40_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(gpio41_a_1, ABX500_ALT_A),
+       AB8500_PIN_GROUP(gpio42_a_1, ABX500_ALT_A),
+       /* Altfunction B column */
+       AB8500_PIN_GROUP(hiqclkena_b_1, ABX500_ALT_B),
+       AB8500_PIN_GROUP(usbuiccpd_b_1, ABX500_ALT_B),
+       AB8500_PIN_GROUP(i2ctrig1_b_1, ABX500_ALT_B),
+       AB8500_PIN_GROUP(i2ctrig2_b_1, ABX500_ALT_B),
+       /* Altfunction C column */
+       AB8500_PIN_GROUP(usbvdat_c_1, ABX500_ALT_C),
+};
+
+/* We use this macro to define the groups applicable to a function */
+#define AB8500_FUNC_GROUPS(a, b...)       \
+static const char * const a##_groups[] = { b };
+
+AB8500_FUNC_GROUPS(sysclkreq, "sysclkreq2_d_1", "sysclkreq3_d_1",
+               "sysclkreq4_d_1", "sysclkreq5_d_1", "sysclkreq6_d_1",
+               "sysclkreq7_d_1", "sysclkreq8_d_1");
+AB8500_FUNC_GROUPS(ycbcr, "ycbcr0123_d_1", "ycbcr4567_a_1");
+AB8500_FUNC_GROUPS(gpio, "gpio1_a_1", "gpio2_a_1", "gpio3_a_1", "gpio4_a_1",
+               "gpio6_a_1", "gpio7_a_1", "gpio8_a_1", "gpio9_a_1",
+               "gpio10_d_1", "gpio11_d_1", "gpio12_d_1", "gpio13_d_1",
+               "gpio14_a_1", "gpio15_a_1", "gpio16_a_1", "gpio17_a_1",
+               "gpio18_a_1", "gpio19_a_1", "gpio20_a_1", "gpio21_a_1",
+               "gpio22_a_1", "gpio23_a_1", "gpio24_a_1", "gpio25_a_1",
+               "gpio26_d_1", "gpio27_a_1", "gpio28_a_1", "gpio29_a_1",
+               "gpio30_a_1", "gpio31_a_1", "gpio32_a_1", "gpio34_a_1",
+               "gpio35_d_1", "gpio36_a_1", "gpio37_a_1", "gpio38_a_1",
+               "gpio39_a_1", "gpio40_a_1", "gpio41_a_1", "gpio42_a_1");
+AB8500_FUNC_GROUPS(pwmout, "pwmout1_d_1", "pwmout2_d_1", "pwmout3_d_1");
+AB8500_FUNC_GROUPS(adi1, "adi1_d_1");
+AB8500_FUNC_GROUPS(usbuicc, "usbuicc_d_1", "usbuiccpd_b_1");
+AB8500_FUNC_GROUPS(dmic, "dmic12_d_1", "dmic34_d_1", "dmic56_d_1");
+AB8500_FUNC_GROUPS(extcpena, "extcpena_d_1");
+AB8500_FUNC_GROUPS(apespi, "apespi_d_1");
+AB8500_FUNC_GROUPS(modsclsda, "modsclsda_d_1");
+AB8500_FUNC_GROUPS(hiqclkena, "hiqclkena_b_1");
+AB8500_FUNC_GROUPS(i2ctrig, "i2ctrig1_b_1", "i2ctrig2_b_1");
+AB8500_FUNC_GROUPS(usbvdat, "usbvdat_c_1");
+
+#define FUNCTION(fname)                                        \
+       {                                               \
+               .name = #fname,                         \
+               .groups = fname##_groups,               \
+               .ngroups = ARRAY_SIZE(fname##_groups),  \
+       }
+
+static const struct abx500_function ab8500_functions[] = {
+       FUNCTION(sysclkreq),
+       FUNCTION(ycbcr),
+       FUNCTION(gpio),
+       FUNCTION(pwmout),
+       FUNCTION(adi1),
+       FUNCTION(usbuicc),
+       FUNCTION(dmic),
+       FUNCTION(extcpena),
+       FUNCTION(apespi),
+       FUNCTION(modsclsda),
+       FUNCTION(hiqclkena),
+       FUNCTION(i2ctrig),
+       FUNCTION(usbvdat),
+};
+
+/*
+ * this table translates what's is in the AB8500 specification regarding the
+ * balls alternate functions (as for DB, default, ALT_A, ALT_B and ALT_C).
+ * ALTERNATE_FUNCTIONS(GPIO_NUMBER, GPIOSEL bit, ALTERNATFUNC bit1,
+ * ALTERNATEFUNC bit2, ALTA val, ALTB val, ALTC val),
+ *
+ * example :
+ *
+ *     ALTERNATE_FUNCTIONS(13,     4,      3,      4, 0, 1 ,2),
+ *     means that pin AB8500_PIN_W17 (pin 13) supports 4 mux (default/ALT_A,
+ *     ALT_B and ALT_C), so GPIOSEL and ALTERNATFUNC registers are used to
+ *     select the mux.  ALTA, ALTB and ALTC val indicates values to write in
+ *     ALTERNATFUNC register. We need to specifies these values as SOC
+ *     designers didn't apply the same logic on how to select mux in the
+ *     ABx500 family.
+ *
+ *     As this pins supports at least ALT_B mux, default mux is
+ *     selected by writing 1 in GPIOSEL bit :
+ *
+ *             | GPIOSEL bit=4 | alternatfunc bit2=4 | alternatfunc bit1=3
+ *     default |       1       |          0          |          0
+ *     alt_A   |       0       |          0          |          0
+ *     alt_B   |       0       |          0          |          1
+ *     alt_C   |       0       |          1          |          0
+ *
+ *     ALTERNATE_FUNCTIONS(8,      7, UNUSED, UNUSED),
+ *     means that pin AB8500_PIN_W18 (pin 8) supports 2 mux, so only GPIOSEL
+ *     register is used to select the mux. As this pins doesn't support at
+ *     least ALT_B mux, default mux is by writing 0 in GPIOSEL bit :
+ *
+ *             | GPIOSEL bit=7 | alternatfunc bit2=  | alternatfunc bit1=
+ *     default |       0       |          0          |          0
+ *     alt_A   |       1       |          0          |          0
+ */
+
+struct alternate_functions ab8500_alternate_functions[AB8500_GPIO_MAX_NUMBER + 1] = {
+       ALTERNATE_FUNCTIONS(0, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO0 */
+       ALTERNATE_FUNCTIONS(1,      0, UNUSED, UNUSED, 0, 0, 0), /* GPIO1, altA controlled by bit 0 */
+       ALTERNATE_FUNCTIONS(2,      1, UNUSED, UNUSED, 0, 0, 0), /* GPIO2, altA controlled by bit 1 */
+       ALTERNATE_FUNCTIONS(3,      2, UNUSED, UNUSED, 0, 0, 0), /* GPIO3, altA controlled by bit 2*/
+       ALTERNATE_FUNCTIONS(4,      3, UNUSED, UNUSED, 0, 0, 0), /* GPIO4, altA controlled by bit 3*/
+       /* bit 4 reserved */
+       ALTERNATE_FUNCTIONS(5, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO5 */
+       ALTERNATE_FUNCTIONS(6,      5, UNUSED, UNUSED, 0, 0, 0), /* GPIO6, altA controlled by bit 5*/
+       ALTERNATE_FUNCTIONS(7,      6, UNUSED, UNUSED, 0, 0, 0), /* GPIO7, altA controlled by bit 6*/
+       ALTERNATE_FUNCTIONS(8,      7, UNUSED, UNUSED, 0, 0, 0), /* GPIO8, altA controlled by bit 7*/
+
+       ALTERNATE_FUNCTIONS(9,      0, UNUSED, UNUSED, 0, 0, 0), /* GPIO9, altA controlled by bit 0*/
+       ALTERNATE_FUNCTIONS(10,     1,      0, UNUSED, 0, 1, 0), /* GPIO10, altA and altB controlled by bit 0 */
+       ALTERNATE_FUNCTIONS(11,     2,      1, UNUSED, 0, 1, 0), /* GPIO11, altA and altB controlled by bit 1 */
+       ALTERNATE_FUNCTIONS(12,     3,      2, UNUSED, 0, 1, 0), /* GPIO12, altA and altB controlled by bit 2 */
+       ALTERNATE_FUNCTIONS(13,     4,      3,      4, 0, 1, 2), /* GPIO13, altA altB and altC controlled by bit 3 and 4 */
+       ALTERNATE_FUNCTIONS(14,     5, UNUSED, UNUSED, 0, 0, 0), /* GPIO14, altA controlled by bit 5 */
+       ALTERNATE_FUNCTIONS(15,     6, UNUSED, UNUSED, 0, 0, 0), /* GPIO15, altA controlled by bit 6 */
+       ALTERNATE_FUNCTIONS(16,     7, UNUSED, UNUSED, 0, 0, 0), /* GPIO16, altA controlled by bit 7 */
+       /*
+        * pins 17 to 20 are special case, only bit 0 is used to select
+        * alternate function for these 4 pins.
+        * bits 1 to 3 are reserved
+        */
+       ALTERNATE_FUNCTIONS(17,      0, UNUSED, UNUSED, 0, 0, 0), /* GPIO17, altA controlled by bit 0 */
+       ALTERNATE_FUNCTIONS(18,      0, UNUSED, UNUSED, 0, 0, 0), /* GPIO18, altA controlled by bit 0 */
+       ALTERNATE_FUNCTIONS(19,      0, UNUSED, UNUSED, 0, 0, 0), /* GPIO19, altA controlled by bit 0 */
+       ALTERNATE_FUNCTIONS(20,      0, UNUSED, UNUSED, 0, 0, 0), /* GPIO20, altA controlled by bit 0 */
+       ALTERNATE_FUNCTIONS(21,      4, UNUSED, UNUSED, 0, 0, 0), /* GPIO21, altA controlled by bit 4 */
+       ALTERNATE_FUNCTIONS(22,      5, UNUSED, UNUSED, 0, 0, 0), /* GPIO22, altA controlled by bit 5 */
+       ALTERNATE_FUNCTIONS(23,      6, UNUSED, UNUSED, 0, 0, 0), /* GPIO23, altA controlled by bit 6 */
+       ALTERNATE_FUNCTIONS(24,      7, UNUSED, UNUSED, 0, 0, 0), /* GPIO24, altA controlled by bit 7 */
+
+       ALTERNATE_FUNCTIONS(25,      0, UNUSED, UNUSED, 0, 0, 0), /* GPIO25, altA controlled by bit 0 */
+       /* pin 26 special case, no alternate function, bit 1 reserved */
+       ALTERNATE_FUNCTIONS(26, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* GPIO26 */
+       ALTERNATE_FUNCTIONS(27,      2, UNUSED, UNUSED, 0, 0, 0), /* GPIO27, altA controlled by bit 2 */
+       ALTERNATE_FUNCTIONS(28,      3, UNUSED, UNUSED, 0, 0, 0), /* GPIO28, altA controlled by bit 3 */
+       ALTERNATE_FUNCTIONS(29,      4, UNUSED, UNUSED, 0, 0, 0), /* GPIO29, altA controlled by bit 4 */
+       ALTERNATE_FUNCTIONS(30,      5, UNUSED, UNUSED, 0, 0, 0), /* GPIO30, altA controlled by bit 5 */
+       ALTERNATE_FUNCTIONS(31,      6, UNUSED, UNUSED, 0, 0, 0), /* GPIO31, altA controlled by bit 6 */
+       ALTERNATE_FUNCTIONS(32,      7, UNUSED, UNUSED, 0, 0, 0), /* GPIO32, altA controlled by bit 7 */
+
+       ALTERNATE_FUNCTIONS(33, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO33 */
+       ALTERNATE_FUNCTIONS(34,      1, UNUSED, UNUSED, 0, 0, 0), /* GPIO34, altA controlled by bit 1 */
+       /* pin 35 special case, no alternate function, bit 2 reserved */
+       ALTERNATE_FUNCTIONS(35, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* GPIO35 */
+       ALTERNATE_FUNCTIONS(36,      3, UNUSED, UNUSED, 0, 0, 0), /* GPIO36, altA controlled by bit 3 */
+       ALTERNATE_FUNCTIONS(37,      4, UNUSED, UNUSED, 0, 0, 0), /* GPIO37, altA controlled by bit 4 */
+       ALTERNATE_FUNCTIONS(38,      5, UNUSED, UNUSED, 0, 0, 0), /* GPIO38, altA controlled by bit 5 */
+       ALTERNATE_FUNCTIONS(39,      6, UNUSED, UNUSED, 0, 0, 0), /* GPIO39, altA controlled by bit 6 */
+       ALTERNATE_FUNCTIONS(40,      7, UNUSED, UNUSED, 0, 0, 0), /* GPIO40, altA controlled by bit 7 */
+
+       ALTERNATE_FUNCTIONS(41,      0, UNUSED, UNUSED, 0, 0, 0), /* GPIO41, altA controlled by bit 0 */
+       ALTERNATE_FUNCTIONS(42,      1, UNUSED, UNUSED, 0, 0, 0), /* GPIO42, altA controlled by bit 1 */
+};
+
+/*
+ * Only some GPIOs are interrupt capable, and they are
+ * organized in discontiguous clusters:
+ *
+ *     GPIO6 to GPIO13
+ *     GPIO24 and GPIO25
+ *     GPIO36 to GPIO41
+ */
+struct abx500_gpio_irq_cluster ab8500_gpio_irq_cluster[] = {
+       GPIO_IRQ_CLUSTER(6,  13, AB8500_INT_GPIO6R),
+       GPIO_IRQ_CLUSTER(24, 25, AB8500_INT_GPIO24R),
+       GPIO_IRQ_CLUSTER(36, 41, AB8500_INT_GPIO36R),
+};
+
+static struct abx500_pinctrl_soc_data ab8500_soc = {
+       .gpio_ranges = ab8500_pinranges,
+       .gpio_num_ranges = ARRAY_SIZE(ab8500_pinranges),
+       .pins = ab8500_pins,
+       .npins = ARRAY_SIZE(ab8500_pins),
+       .functions = ab8500_functions,
+       .nfunctions = ARRAY_SIZE(ab8500_functions),
+       .groups = ab8500_groups,
+       .ngroups = ARRAY_SIZE(ab8500_groups),
+       .alternate_functions = ab8500_alternate_functions,
+       .gpio_irq_cluster = ab8500_gpio_irq_cluster,
+       .ngpio_irq_cluster = ARRAY_SIZE(ab8500_gpio_irq_cluster),
+       .irq_gpio_rising_offset = AB8500_INT_GPIO6R,
+       .irq_gpio_falling_offset = AB8500_INT_GPIO6F,
+       .irq_gpio_factor = 1,
+};
+
+void abx500_pinctrl_ab8500_init(struct abx500_pinctrl_soc_data **soc)
+{
+       *soc = &ab8500_soc;
+}
diff --git a/drivers/pinctrl/pinctrl-ab8505.c b/drivers/pinctrl/pinctrl-ab8505.c
new file mode 100644 (file)
index 0000000..3a4238e
--- /dev/null
@@ -0,0 +1,380 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2012
+ *
+ * Author: Patrice Chotard <patrice.chotard@stericsson.com> for ST-Ericsson.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/mfd/abx500/ab8500.h>
+#include "pinctrl-abx500.h"
+
+/* All the pins that can be used for GPIO and some other functions */
+#define ABX500_GPIO(offset)    (offset)
+
+#define AB8505_PIN_N4          ABX500_GPIO(1)
+#define AB8505_PIN_R5          ABX500_GPIO(2)
+#define AB8505_PIN_P5          ABX500_GPIO(3)
+/* hole */
+#define AB8505_PIN_B16         ABX500_GPIO(10)
+#define AB8505_PIN_B17         ABX500_GPIO(11)
+/* hole */
+#define AB8505_PIN_D17         ABX500_GPIO(13)
+#define AB8505_PIN_C16         ABX500_GPIO(14)
+/* hole */
+#define AB8505_PIN_P2          ABX500_GPIO(17)
+#define AB8505_PIN_N3          ABX500_GPIO(18)
+#define AB8505_PIN_T1          ABX500_GPIO(19)
+#define AB8505_PIN_P3          ABX500_GPIO(20)
+/* hole */
+#define AB8505_PIN_H14         ABX500_GPIO(34)
+/* hole */
+#define AB8505_PIN_J15         ABX500_GPIO(40)
+#define AB8505_PIN_J14         ABX500_GPIO(41)
+/* hole */
+#define AB8505_PIN_L4          ABX500_GPIO(50)
+/* hole */
+#define AB8505_PIN_D16         ABX500_GPIO(52)
+#define AB8505_PIN_D15         ABX500_GPIO(53)
+
+/* indicates the higher GPIO number */
+#define AB8505_GPIO_MAX_NUMBER 53
+
+/*
+ * The names of the pins are denoted by GPIO number and ball name, even
+ * though they can be used for other things than GPIO, this is the first
+ * column in the table of the data sheet and often used on schematics and
+ * such.
+ */
+static const struct pinctrl_pin_desc ab8505_pins[] = {
+       PINCTRL_PIN(AB8505_PIN_N4, "GPIO1_N4"),
+       PINCTRL_PIN(AB8505_PIN_R5, "GPIO2_R5"),
+       PINCTRL_PIN(AB8505_PIN_P5, "GPIO3_P5"),
+/* hole */
+       PINCTRL_PIN(AB8505_PIN_B16, "GPIO10_B16"),
+       PINCTRL_PIN(AB8505_PIN_B17, "GPIO11_B17"),
+/* hole */
+       PINCTRL_PIN(AB8505_PIN_D17, "GPIO13_D17"),
+       PINCTRL_PIN(AB8505_PIN_C16, "GPIO14_C16"),
+/* hole */
+       PINCTRL_PIN(AB8505_PIN_P2, "GPIO17_P2"),
+       PINCTRL_PIN(AB8505_PIN_N3, "GPIO18_N3"),
+       PINCTRL_PIN(AB8505_PIN_T1, "GPIO19_T1"),
+       PINCTRL_PIN(AB8505_PIN_P3, "GPIO20_P3"),
+/* hole */
+       PINCTRL_PIN(AB8505_PIN_H14, "GPIO34_H14"),
+/* hole */
+       PINCTRL_PIN(AB8505_PIN_J15, "GPIO40_J15"),
+       PINCTRL_PIN(AB8505_PIN_J14, "GPIO41_J14"),
+/* hole */
+       PINCTRL_PIN(AB8505_PIN_L4, "GPIO50_L4"),
+/* hole */
+       PINCTRL_PIN(AB8505_PIN_D16, "GPIO52_D16"),
+       PINCTRL_PIN(AB8505_PIN_D15, "GPIO53_D15"),
+};
+
+/*
+ * Maps local GPIO offsets to local pin numbers
+ */
+static const struct abx500_pinrange ab8505_pinranges[] = {
+       ABX500_PINRANGE(1, 3, ABX500_ALT_A),
+       ABX500_PINRANGE(10, 2, ABX500_DEFAULT),
+       ABX500_PINRANGE(13, 1, ABX500_DEFAULT),
+       ABX500_PINRANGE(14, 1, ABX500_ALT_A),
+       ABX500_PINRANGE(17, 4, ABX500_ALT_A),
+       ABX500_PINRANGE(34, 1, ABX500_ALT_A),
+       ABX500_PINRANGE(40, 2, ABX500_ALT_A),
+       ABX500_PINRANGE(50, 1, ABX500_DEFAULT),
+       ABX500_PINRANGE(52, 2, ABX500_ALT_A),
+};
+
+/*
+ * Read the pin group names like this:
+ * sysclkreq2_d_1 = first groups of pins for sysclkreq2 on default function
+ *
+ * The groups are arranged as sets per altfunction column, so we can
+ * mux in one group at a time by selecting the same altfunction for them
+ * all. When functions require pins on different altfunctions, you need
+ * to combine several groups.
+ */
+
+/* default column */
+static const unsigned sysclkreq2_d_1_pins[] = { AB8505_PIN_N4 };
+static const unsigned sysclkreq3_d_1_pins[] = { AB8505_PIN_R5 };
+static const unsigned sysclkreq4_d_1_pins[] = { AB8505_PIN_P5 };
+static const unsigned gpio10_d_1_pins[] = { AB8505_PIN_B16 };
+static const unsigned gpio11_d_1_pins[] = { AB8505_PIN_B17 };
+static const unsigned gpio13_d_1_pins[] = { AB8505_PIN_D17 };
+static const unsigned pwmout1_d_1_pins[] = { AB8505_PIN_C16 };
+/* audio data interface 2*/
+static const unsigned adi2_d_1_pins[] = { AB8505_PIN_P2, AB8505_PIN_N3,
+                                       AB8505_PIN_T1, AB8505_PIN_P3 };
+static const unsigned extcpena_d_1_pins[] = { AB8505_PIN_H14 };
+/* modem SDA/SCL */
+static const unsigned modsclsda_d_1_pins[] = { AB8505_PIN_J15, AB8505_PIN_J14 };
+static const unsigned gpio50_d_1_pins[] = { AB8505_PIN_L4 };
+static const unsigned resethw_d_1_pins[] = { AB8505_PIN_D16 };
+static const unsigned service_d_1_pins[] = { AB8505_PIN_D15 };
+
+/* Altfunction A column */
+static const unsigned gpio1_a_1_pins[] = { AB8505_PIN_N4 };
+static const unsigned gpio2_a_1_pins[] = { AB8505_PIN_R5 };
+static const unsigned gpio3_a_1_pins[] = { AB8505_PIN_P5 };
+static const unsigned hiqclkena_a_1_pins[] = { AB8505_PIN_B16 };
+static const unsigned pdmclk_a_1_pins[] = { AB8505_PIN_B17 };
+static const unsigned uarttxdata_a_1_pins[] = { AB8505_PIN_D17 };
+static const unsigned gpio14_a_1_pins[] = { AB8505_PIN_C16 };
+static const unsigned gpio17_a_1_pins[] = { AB8505_PIN_P2 };
+static const unsigned gpio18_a_1_pins[] = { AB8505_PIN_N3 };
+static const unsigned gpio19_a_1_pins[] = { AB8505_PIN_T1 };
+static const unsigned gpio20_a_1_pins[] = { AB8505_PIN_P3 };
+static const unsigned gpio34_a_1_pins[] = { AB8505_PIN_H14 };
+static const unsigned gpio40_a_1_pins[] = { AB8505_PIN_J15 };
+static const unsigned gpio41_a_1_pins[] = { AB8505_PIN_J14 };
+static const unsigned uartrxdata_a_1_pins[] = { AB8505_PIN_J14 };
+static const unsigned gpio50_a_1_pins[] = { AB8505_PIN_L4 };
+static const unsigned gpio52_a_1_pins[] = { AB8505_PIN_D16 };
+static const unsigned gpio53_a_1_pins[] = { AB8505_PIN_D15 };
+
+/* Altfunction B colum */
+static const unsigned pdmdata_b_1_pins[] = { AB8505_PIN_B16 };
+static const unsigned extvibrapwm1_b_1_pins[] = { AB8505_PIN_D17 };
+static const unsigned extvibrapwm2_b_1_pins[] = { AB8505_PIN_L4 };
+
+/* Altfunction C column */
+static const unsigned usbvdat_c_1_pins[] = { AB8505_PIN_D17 };
+
+#define AB8505_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins,         \
+                       .npins = ARRAY_SIZE(a##_pins), .altsetting = b }
+
+static const struct abx500_pingroup ab8505_groups[] = {
+       AB8505_PIN_GROUP(sysclkreq2_d_1, ABX500_DEFAULT),
+       AB8505_PIN_GROUP(sysclkreq3_d_1, ABX500_DEFAULT),
+       AB8505_PIN_GROUP(sysclkreq4_d_1, ABX500_DEFAULT),
+       AB8505_PIN_GROUP(gpio10_d_1, ABX500_DEFAULT),
+       AB8505_PIN_GROUP(gpio11_d_1, ABX500_DEFAULT),
+       AB8505_PIN_GROUP(gpio13_d_1, ABX500_DEFAULT),
+       AB8505_PIN_GROUP(pwmout1_d_1, ABX500_DEFAULT),
+       AB8505_PIN_GROUP(adi2_d_1, ABX500_DEFAULT),
+       AB8505_PIN_GROUP(extcpena_d_1, ABX500_DEFAULT),
+       AB8505_PIN_GROUP(modsclsda_d_1, ABX500_DEFAULT),
+       AB8505_PIN_GROUP(gpio50_d_1, ABX500_DEFAULT),
+       AB8505_PIN_GROUP(resethw_d_1, ABX500_DEFAULT),
+       AB8505_PIN_GROUP(service_d_1, ABX500_DEFAULT),
+       AB8505_PIN_GROUP(gpio1_a_1, ABX500_ALT_A),
+       AB8505_PIN_GROUP(gpio2_a_1, ABX500_ALT_A),
+       AB8505_PIN_GROUP(gpio3_a_1, ABX500_ALT_A),
+       AB8505_PIN_GROUP(hiqclkena_a_1, ABX500_ALT_A),
+       AB8505_PIN_GROUP(pdmclk_a_1, ABX500_ALT_A),
+       AB8505_PIN_GROUP(uarttxdata_a_1, ABX500_ALT_A),
+       AB8505_PIN_GROUP(gpio14_a_1, ABX500_ALT_A),
+       AB8505_PIN_GROUP(gpio17_a_1, ABX500_ALT_A),
+       AB8505_PIN_GROUP(gpio18_a_1, ABX500_ALT_A),
+       AB8505_PIN_GROUP(gpio19_a_1, ABX500_ALT_A),
+       AB8505_PIN_GROUP(gpio20_a_1, ABX500_ALT_A),
+       AB8505_PIN_GROUP(gpio34_a_1, ABX500_ALT_A),
+       AB8505_PIN_GROUP(gpio40_a_1, ABX500_ALT_A),
+       AB8505_PIN_GROUP(gpio41_a_1, ABX500_ALT_A),
+       AB8505_PIN_GROUP(uartrxdata_a_1, ABX500_ALT_A),
+       AB8505_PIN_GROUP(gpio52_a_1, ABX500_ALT_A),
+       AB8505_PIN_GROUP(gpio53_a_1, ABX500_ALT_A),
+       AB8505_PIN_GROUP(pdmdata_b_1, ABX500_ALT_B),
+       AB8505_PIN_GROUP(extvibrapwm1_b_1, ABX500_ALT_B),
+       AB8505_PIN_GROUP(extvibrapwm2_b_1, ABX500_ALT_B),
+       AB8505_PIN_GROUP(usbvdat_c_1, ABX500_ALT_C),
+};
+
+/* We use this macro to define the groups applicable to a function */
+#define AB8505_FUNC_GROUPS(a, b...)       \
+static const char * const a##_groups[] = { b };
+
+AB8505_FUNC_GROUPS(sysclkreq, "sysclkreq2_d_1", "sysclkreq3_d_1",
+               "sysclkreq4_d_1");
+AB8505_FUNC_GROUPS(gpio, "gpio1_a_1", "gpio2_a_1", "gpio3_a_1",
+               "gpio10_d_1", "gpio11_d_1", "gpio13_d_1", "gpio14_a_1",
+               "gpio17_a_1", "gpio18_a_1", "gpio19_a_1", "gpio20_a_1",
+               "gpio34_a_1", "gpio40_a_1", "gpio41_a_1", "gpio50_d_1",
+               "gpio52_a_1", "gpio53_a_1");
+AB8505_FUNC_GROUPS(pwmout, "pwmout1_d_1");
+AB8505_FUNC_GROUPS(adi2, "adi2_d_1");
+AB8505_FUNC_GROUPS(extcpena, "extcpena_d_1");
+AB8505_FUNC_GROUPS(modsclsda, "modsclsda_d_1");
+AB8505_FUNC_GROUPS(resethw, "resethw_d_1");
+AB8505_FUNC_GROUPS(service, "service_d_1");
+AB8505_FUNC_GROUPS(hiqclkena, "hiqclkena_a_1");
+AB8505_FUNC_GROUPS(pdm, "pdmclk_a_1", "pdmdata_b_1");
+AB8505_FUNC_GROUPS(uartdata, "uarttxdata_a_1", "uartrxdata_a_1");
+AB8505_FUNC_GROUPS(extvibra, "extvibrapwm1_b_1", "extvibrapwm2_b_1");
+AB8505_FUNC_GROUPS(usbvdat, "usbvdat_c_1");
+
+#define FUNCTION(fname)                                        \
+       {                                               \
+               .name = #fname,                         \
+               .groups = fname##_groups,               \
+               .ngroups = ARRAY_SIZE(fname##_groups),  \
+       }
+
+static const struct abx500_function ab8505_functions[] = {
+       FUNCTION(sysclkreq),
+       FUNCTION(gpio),
+       FUNCTION(pwmout),
+       FUNCTION(adi2),
+       FUNCTION(extcpena),
+       FUNCTION(modsclsda),
+       FUNCTION(resethw),
+       FUNCTION(service),
+       FUNCTION(hiqclkena),
+       FUNCTION(pdm),
+       FUNCTION(uartdata),
+       FUNCTION(extvibra),
+       FUNCTION(extvibra),
+       FUNCTION(usbvdat),
+};
+
+/*
+ * this table translates what's is in the AB8505 specification regarding the
+ * balls alternate functions (as for DB, default, ALT_A, ALT_B and ALT_C).
+ * ALTERNATE_FUNCTIONS(GPIO_NUMBER, GPIOSEL bit, ALTERNATFUNC bit1,
+ * ALTERNATEFUNC bit2, ALTA val, ALTB val, ALTC val),
+ *
+ * example :
+ *
+ *     ALTERNATE_FUNCTIONS(13,     4,      3,      4, 1, 0, 2),
+ *     means that pin AB8505_PIN_D18 (pin 13) supports 4 mux (default/ALT_A,
+ *     ALT_B and ALT_C), so GPIOSEL and ALTERNATFUNC registers are used to
+ *     select the mux. ALTA, ALTB and ALTC val indicates values to write in
+ *     ALTERNATFUNC register. We need to specifies these values as SOC
+ *     designers didn't apply the same logic on how to select mux in the
+ *     ABx500 family.
+ *
+ *     As this pins supports at least ALT_B mux, default mux is
+ *     selected by writing 1 in GPIOSEL bit :
+ *
+ *             | GPIOSEL bit=4 | alternatfunc bit2=4 | alternatfunc bit1=3
+ *     default |       1       |          0          |          0
+ *     alt_A   |       0       |          0          |          1
+ *     alt_B   |       0       |          0          |          0
+ *     alt_C   |       0       |          1          |          0
+ *
+ *     ALTERNATE_FUNCTIONS(1,      0, UNUSED, UNUSED),
+ *     means that pin AB9540_PIN_R4 (pin 1) supports 2 mux, so only GPIOSEL
+ *     register is used to select the mux. As this pins doesn't support at
+ *     least ALT_B mux, default mux is by writing 0 in GPIOSEL bit :
+ *
+ *             | GPIOSEL bit=0 | alternatfunc bit2=  | alternatfunc bit1=
+ *     default |       0       |          0          |          0
+ *     alt_A   |       1       |          0          |          0
+ */
+
+struct alternate_functions ab8505_alternate_functions[AB8505_GPIO_MAX_NUMBER + 1] = {
+       ALTERNATE_FUNCTIONS(0, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO0 */
+       ALTERNATE_FUNCTIONS(1,      0, UNUSED, UNUSED, 0, 0, 0), /* GPIO1, altA controlled by bit 0 */
+       ALTERNATE_FUNCTIONS(2,      1, UNUSED, UNUSED, 0, 0, 0), /* GPIO2, altA controlled by bit 1 */
+       ALTERNATE_FUNCTIONS(3,      2, UNUSED, UNUSED, 0, 0, 0), /* GPIO3, altA controlled by bit 2*/
+       ALTERNATE_FUNCTIONS(4, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO4, bit 3 reserved */
+       ALTERNATE_FUNCTIONS(5, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO5, bit 4 reserved */
+       ALTERNATE_FUNCTIONS(6, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO6, bit 5 reserved */
+       ALTERNATE_FUNCTIONS(7, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO7, bit 6 reserved */
+       ALTERNATE_FUNCTIONS(8, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO8, bit 7 reserved */
+
+       ALTERNATE_FUNCTIONS(9, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO9, bit 0 reserved */
+       ALTERNATE_FUNCTIONS(10,      1,      0, UNUSED, 1, 0, 0), /* GPIO10, altA and altB controlled by bit 0 */
+       ALTERNATE_FUNCTIONS(11,      2, UNUSED, UNUSED, 0, 0, 0), /* GPIO11, altA controlled by bit 2 */
+       ALTERNATE_FUNCTIONS(12, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO12, bit3 reseved */
+       ALTERNATE_FUNCTIONS(13,      4,      3,      4, 1, 0, 2), /* GPIO13, altA altB and altC controlled by bit 3 and 4 */
+       ALTERNATE_FUNCTIONS(14,      5, UNUSED, UNUSED, 0, 0, 0), /* GPIO14, altA controlled by bit 5 */
+       ALTERNATE_FUNCTIONS(15, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO15, bit 6 reserved */
+       ALTERNATE_FUNCTIONS(16, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO15, bit 7 reserved  */
+       /*
+        * pins 17 to 20 are special case, only bit 0 is used to select
+        * alternate function for these 4 pins.
+        * bits 1 to 3 are reserved
+        */
+       ALTERNATE_FUNCTIONS(17,      0, UNUSED, UNUSED, 0, 0, 0), /* GPIO17, altA controlled by bit 0 */
+       ALTERNATE_FUNCTIONS(18,      0, UNUSED, UNUSED, 0, 0, 0), /* GPIO18, altA controlled by bit 0 */
+       ALTERNATE_FUNCTIONS(19,      0, UNUSED, UNUSED, 0, 0, 0), /* GPIO19, altA controlled by bit 0 */
+       ALTERNATE_FUNCTIONS(20,      0, UNUSED, UNUSED, 0, 0, 0), /* GPIO20, altA controlled by bit 0 */
+       ALTERNATE_FUNCTIONS(21, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO21, bit 4 reserved */
+       ALTERNATE_FUNCTIONS(22, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO22, bit 5 reserved */
+       ALTERNATE_FUNCTIONS(23, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO23, bit 6 reserved */
+       ALTERNATE_FUNCTIONS(24, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO24, bit 7 reserved */
+
+       ALTERNATE_FUNCTIONS(25, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO25, bit 0 reserved */
+       ALTERNATE_FUNCTIONS(26, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO26, bit 1 reserved */
+       ALTERNATE_FUNCTIONS(27, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO27, bit 2 reserved */
+       ALTERNATE_FUNCTIONS(28, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO28, bit 3 reserved */
+       ALTERNATE_FUNCTIONS(29, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO29, bit 4 reserved */
+       ALTERNATE_FUNCTIONS(30, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO30, bit 5 reserved */
+       ALTERNATE_FUNCTIONS(31, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO31, bit 6 reserved */
+       ALTERNATE_FUNCTIONS(32, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO32, bit 7 reserved */
+
+       ALTERNATE_FUNCTIONS(33, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO33, bit 0 reserved */
+       ALTERNATE_FUNCTIONS(34,      1, UNUSED, UNUSED, 0, 0, 0), /* GPIO34, altA controlled by bit 1 */
+       ALTERNATE_FUNCTIONS(35, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO35, bit 2 reserved */
+       ALTERNATE_FUNCTIONS(36, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO36, bit 2 reserved */
+       ALTERNATE_FUNCTIONS(37, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO37, bit 2 reserved */
+       ALTERNATE_FUNCTIONS(38, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO38, bit 2 reserved */
+       ALTERNATE_FUNCTIONS(39, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO39, bit 2 reserved */
+       ALTERNATE_FUNCTIONS(40,      7, UNUSED, UNUSED, 0, 0, 0), /* GPIO40, altA controlled by bit 7*/
+
+       ALTERNATE_FUNCTIONS(41,      0, UNUSED, UNUSED, 0, 0, 0), /* GPIO41, altA controlled by bit 0 */
+       ALTERNATE_FUNCTIONS(42, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO42, bit 1 reserved */
+       ALTERNATE_FUNCTIONS(43, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO43, bit 2 reserved */
+       ALTERNATE_FUNCTIONS(44, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO44, bit 3 reserved */
+       ALTERNATE_FUNCTIONS(45, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO45, bit 4 reserved */
+       ALTERNATE_FUNCTIONS(46, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO46, bit 5 reserved */
+       ALTERNATE_FUNCTIONS(47, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO47, bit 6 reserved */
+       ALTERNATE_FUNCTIONS(48, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO48, bit 7 reserved */
+
+       ALTERNATE_FUNCTIONS(49, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO49, bit 0 reserved */
+       ALTERNATE_FUNCTIONS(50,      1,      2, UNUSED, 1, 0, 0), /* GPIO50, altA controlled by bit 1 */
+       ALTERNATE_FUNCTIONS(51, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO49, bit 0 reserved */
+       ALTERNATE_FUNCTIONS(52,      3, UNUSED, UNUSED, 0, 0, 0), /* GPIO52, altA controlled by bit 3 */
+       ALTERNATE_FUNCTIONS(53,      4, UNUSED, UNUSED, 0, 0, 0), /* GPIO53, altA controlled by bit 4 */
+};
+
+/*
+ * For AB8505 Only some GPIOs are interrupt capable, and they are
+ * organized in discontiguous clusters:
+ *
+ *     GPIO10 to GPIO11
+ *     GPIO13
+ *     GPIO40 and GPIO41
+ *     GPIO50
+ *     GPIO52 to GPIO53
+ */
+struct abx500_gpio_irq_cluster ab8505_gpio_irq_cluster[] = {
+       GPIO_IRQ_CLUSTER(10, 11, AB8500_INT_GPIO10R),
+       GPIO_IRQ_CLUSTER(13, 13, AB8500_INT_GPIO13R),
+       GPIO_IRQ_CLUSTER(40, 41, AB8500_INT_GPIO40R),
+       GPIO_IRQ_CLUSTER(50, 50, AB9540_INT_GPIO50R),
+       GPIO_IRQ_CLUSTER(52, 53, AB9540_INT_GPIO52R),
+};
+
+static struct abx500_pinctrl_soc_data ab8505_soc = {
+       .gpio_ranges = ab8505_pinranges,
+       .gpio_num_ranges = ARRAY_SIZE(ab8505_pinranges),
+       .pins = ab8505_pins,
+       .npins = ARRAY_SIZE(ab8505_pins),
+       .functions = ab8505_functions,
+       .nfunctions = ARRAY_SIZE(ab8505_functions),
+       .groups = ab8505_groups,
+       .ngroups = ARRAY_SIZE(ab8505_groups),
+       .alternate_functions = ab8505_alternate_functions,
+       .gpio_irq_cluster = ab8505_gpio_irq_cluster,
+       .ngpio_irq_cluster = ARRAY_SIZE(ab8505_gpio_irq_cluster),
+       .irq_gpio_rising_offset = AB8500_INT_GPIO6R,
+       .irq_gpio_falling_offset = AB8500_INT_GPIO6F,
+       .irq_gpio_factor = 1,
+};
+
+void
+abx500_pinctrl_ab8505_init(struct abx500_pinctrl_soc_data **soc)
+{
+       *soc = &ab8505_soc;
+}
diff --git a/drivers/pinctrl/pinctrl-ab8540.c b/drivers/pinctrl/pinctrl-ab8540.c
new file mode 100644 (file)
index 0000000..8ee1e8d
--- /dev/null
@@ -0,0 +1,407 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2012
+ *
+ * Author: Patrice Chotard <patrice.chotard@stericsson.com> for ST-Ericsson.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/mfd/abx500/ab8500.h>
+#include "pinctrl-abx500.h"
+
+/* All the pins that can be used for GPIO and some other functions */
+#define ABX500_GPIO(offset)            (offset)
+
+#define AB8540_PIN_J16         ABX500_GPIO(1)
+#define AB8540_PIN_D17         ABX500_GPIO(2)
+#define AB8540_PIN_C12         ABX500_GPIO(3)
+#define AB8540_PIN_G12         ABX500_GPIO(4)
+/* hole */
+#define AB8540_PIN_D16         ABX500_GPIO(14)
+#define AB8540_PIN_F15         ABX500_GPIO(15)
+#define AB8540_PIN_J8          ABX500_GPIO(16)
+#define AB8540_PIN_K16         ABX500_GPIO(17)
+#define AB8540_PIN_G15         ABX500_GPIO(18)
+#define AB8540_PIN_F17         ABX500_GPIO(19)
+#define AB8540_PIN_E17         ABX500_GPIO(20)
+/* hole */
+#define AB8540_PIN_AA16                ABX500_GPIO(27)
+#define AB8540_PIN_W18         ABX500_GPIO(28)
+#define AB8540_PIN_Y15         ABX500_GPIO(29)
+#define AB8540_PIN_W16         ABX500_GPIO(30)
+#define AB8540_PIN_V15         ABX500_GPIO(31)
+#define AB8540_PIN_W17         ABX500_GPIO(32)
+/* hole */
+#define AB8540_PIN_D12         ABX500_GPIO(42)
+#define AB8540_PIN_P4          ABX500_GPIO(43)
+#define AB8540_PIN_AB1         ABX500_GPIO(44)
+#define AB8540_PIN_K7          ABX500_GPIO(45)
+#define AB8540_PIN_L7          ABX500_GPIO(46)
+#define AB8540_PIN_G10         ABX500_GPIO(47)
+#define AB8540_PIN_K12         ABX500_GPIO(48)
+/* hole */
+#define AB8540_PIN_N8          ABX500_GPIO(51)
+#define AB8540_PIN_P12         ABX500_GPIO(52)
+#define AB8540_PIN_K8          ABX500_GPIO(53)
+#define AB8540_PIN_J11         ABX500_GPIO(54)
+#define AB8540_PIN_AC2         ABX500_GPIO(55)
+#define AB8540_PIN_AB2         ABX500_GPIO(56)
+
+/* indicates the highest GPIO number */
+#define AB8540_GPIO_MAX_NUMBER 56
+
+/*
+ * The names of the pins are denoted by GPIO number and ball name, even
+ * though they can be used for other things than GPIO, this is the first
+ * column in the table of the data sheet and often used on schematics and
+ * such.
+ */
+static const struct pinctrl_pin_desc ab8540_pins[] = {
+       PINCTRL_PIN(AB8540_PIN_J16, "GPIO1_J16"),
+       PINCTRL_PIN(AB8540_PIN_D17, "GPIO2_D17"),
+       PINCTRL_PIN(AB8540_PIN_C12, "GPIO3_C12"),
+       PINCTRL_PIN(AB8540_PIN_G12, "GPIO4_G12"),
+       /* hole */
+       PINCTRL_PIN(AB8540_PIN_D16, "GPIO14_D16"),
+       PINCTRL_PIN(AB8540_PIN_F15, "GPIO15_F15"),
+       PINCTRL_PIN(AB8540_PIN_J8, "GPIO16_J8"),
+       PINCTRL_PIN(AB8540_PIN_K16, "GPIO17_K16"),
+       PINCTRL_PIN(AB8540_PIN_G15, "GPIO18_G15"),
+       PINCTRL_PIN(AB8540_PIN_F17, "GPIO19_F17"),
+       PINCTRL_PIN(AB8540_PIN_E17, "GPIO20_E17"),
+       /* hole */
+       PINCTRL_PIN(AB8540_PIN_AA16, "GPIO27_AA16"),
+       PINCTRL_PIN(AB8540_PIN_W18, "GPIO28_W18"),
+       PINCTRL_PIN(AB8540_PIN_Y15, "GPIO29_Y15"),
+       PINCTRL_PIN(AB8540_PIN_W16, "GPIO30_W16"),
+       PINCTRL_PIN(AB8540_PIN_V15, "GPIO31_V15"),
+       PINCTRL_PIN(AB8540_PIN_W17, "GPIO32_W17"),
+       /* hole */
+       PINCTRL_PIN(AB8540_PIN_D12, "GPIO42_D12"),
+       PINCTRL_PIN(AB8540_PIN_P4, "GPIO43_P4"),
+       PINCTRL_PIN(AB8540_PIN_AB1, "GPIO44_AB1"),
+       PINCTRL_PIN(AB8540_PIN_K7, "GPIO45_K7"),
+       PINCTRL_PIN(AB8540_PIN_L7, "GPIO46_L7"),
+       PINCTRL_PIN(AB8540_PIN_G10, "GPIO47_G10"),
+       PINCTRL_PIN(AB8540_PIN_K12, "GPIO48_K12"),
+       /* hole */
+       PINCTRL_PIN(AB8540_PIN_N8, "GPIO51_N8"),
+       PINCTRL_PIN(AB8540_PIN_P12, "GPIO52_P12"),
+       PINCTRL_PIN(AB8540_PIN_K8, "GPIO53_K8"),
+       PINCTRL_PIN(AB8540_PIN_J11, "GPIO54_J11"),
+       PINCTRL_PIN(AB8540_PIN_AC2, "GPIO55_AC2"),
+       PINCTRL_PIN(AB8540_PIN_AB2, "GPIO56_AB2"),
+};
+
+/*
+ * Maps local GPIO offsets to local pin numbers
+ */
+static const struct abx500_pinrange ab8540_pinranges[] = {
+       ABX500_PINRANGE(1, 4, ABX500_ALT_A),
+       ABX500_PINRANGE(14, 7, ABX500_ALT_A),
+       ABX500_PINRANGE(27, 6, ABX500_ALT_A),
+       ABX500_PINRANGE(42, 7, ABX500_ALT_A),
+       ABX500_PINRANGE(51, 6, ABX500_ALT_A),
+};
+
+/*
+ * Read the pin group names like this:
+ * sysclkreq2_d_1 = first groups of pins for sysclkreq2 on default function
+ *
+ * The groups are arranged as sets per altfunction column, so we can
+ * mux in one group at a time by selecting the same altfunction for them
+ * all. When functions require pins on different altfunctions, you need
+ * to combine several groups.
+ */
+
+/* default column */
+static const unsigned sysclkreq2_d_1_pins[] = { AB8540_PIN_J16 };
+static const unsigned sysclkreq3_d_1_pins[] = { AB8540_PIN_D17 };
+static const unsigned sysclkreq4_d_1_pins[] = { AB8540_PIN_C12 };
+static const unsigned sysclkreq6_d_1_pins[] = { AB8540_PIN_G12 };
+static const unsigned pwmout1_d_1_pins[] = { AB8540_PIN_D16 };
+static const unsigned pwmout2_d_1_pins[] = { AB8540_PIN_F15 };
+static const unsigned pwmout3_d_1_pins[] = { AB8540_PIN_J8 };
+
+/* audio data interface 1*/
+static const unsigned adi1_d_1_pins[] = { AB8540_PIN_K16, AB8540_PIN_G15,
+                                       AB8540_PIN_F17, AB8540_PIN_E17 };
+/* Digital microphone 1 and 2 */
+static const unsigned dmic12_d_1_pins[] = { AB8540_PIN_AA16, AB8540_PIN_W18 };
+/* Digital microphone 3 and 4 */
+static const unsigned dmic34_d_1_pins[] = { AB8540_PIN_Y15, AB8540_PIN_W16 };
+/* Digital microphone 5 and 6 */
+static const unsigned dmic56_d_1_pins[] = { AB8540_PIN_V15, AB8540_PIN_W17 };
+static const unsigned sysclkreq5_d_1_pins[] = { AB8540_PIN_D12 };
+static const unsigned batremn_d_1_pins[] = { AB8540_PIN_P4 };
+static const unsigned service_d_1_pins[] = { AB8540_PIN_AB1 };
+static const unsigned pwrctrl0_d_1_pins[] = { AB8540_PIN_K7 };
+static const unsigned pwrctrl1_d_1_pins[] = { AB8540_PIN_L7 };
+static const unsigned pwmextvibra1_d_1_pins[] = { AB8540_PIN_G10 };
+static const unsigned pwmextvibra2_d_1_pins[] = { AB8540_PIN_K12 };
+static const unsigned gpio1_vbat_d_1_pins[] = { AB8540_PIN_N8 };
+static const unsigned gpio2_vbat_d_1_pins[] = { AB8540_PIN_P12 };
+static const unsigned gpio3_vbat_d_1_pins[] = { AB8540_PIN_K8 };
+static const unsigned gpio4_vbat_d_1_pins[] = { AB8540_PIN_J11 };
+static const unsigned pdmclkdat_d_1_pins[] = { AB8540_PIN_AC2, AB8540_PIN_AB2 };
+
+/* Altfunction A column */
+static const unsigned gpio1_a_1_pins[] = { AB8540_PIN_J16 };
+static const unsigned gpio2_a_1_pins[] = { AB8540_PIN_D17 };
+static const unsigned gpio3_a_1_pins[] = { AB8540_PIN_C12 };
+static const unsigned gpio4_a_1_pins[] = { AB8540_PIN_G12 };
+static const unsigned gpio14_a_1_pins[] = { AB8540_PIN_D16 };
+static const unsigned gpio15_a_1_pins[] = { AB8540_PIN_F15 };
+static const unsigned gpio16_a_1_pins[] = { AB8540_PIN_J8 };
+static const unsigned gpio17_a_1_pins[] = { AB8540_PIN_K16 };
+static const unsigned gpio18_a_1_pins[] = { AB8540_PIN_G15 };
+static const unsigned gpio19_a_1_pins[] = { AB8540_PIN_F17 };
+static const unsigned gpio20_a_1_pins[] = { AB8540_PIN_E17 };
+static const unsigned gpio27_a_1_pins[] = { AB8540_PIN_AA16 };
+static const unsigned gpio28_a_1_pins[] = { AB8540_PIN_W18 };
+static const unsigned gpio29_a_1_pins[] = { AB8540_PIN_Y15 };
+static const unsigned gpio30_a_1_pins[] = { AB8540_PIN_W16 };
+static const unsigned gpio31_a_1_pins[] = { AB8540_PIN_V15 };
+static const unsigned gpio32_a_1_pins[] = { AB8540_PIN_W17 };
+static const unsigned gpio42_a_1_pins[] = { AB8540_PIN_D12 };
+static const unsigned gpio43_a_1_pins[] = { AB8540_PIN_P4 };
+static const unsigned gpio44_a_1_pins[] = { AB8540_PIN_AB1 };
+static const unsigned gpio45_a_1_pins[] = { AB8540_PIN_K7 };
+static const unsigned gpio46_a_1_pins[] = { AB8540_PIN_L7 };
+static const unsigned gpio47_a_1_pins[] = { AB8540_PIN_G10 };
+static const unsigned gpio48_a_1_pins[] = { AB8540_PIN_K12 };
+static const unsigned gpio51_a_1_pins[] = { AB8540_PIN_N8 };
+static const unsigned gpio52_a_1_pins[] = { AB8540_PIN_P12 };
+static const unsigned gpio53_a_1_pins[] = { AB8540_PIN_K8 };
+static const unsigned gpio54_a_1_pins[] = { AB8540_PIN_J11 };
+static const unsigned gpio55_a_1_pins[] = { AB8540_PIN_AC2 };
+static const unsigned gpio56_a_1_pins[] = { AB8540_PIN_AB2 };
+
+#define AB8540_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins,         \
+                       .npins = ARRAY_SIZE(a##_pins), .altsetting = b }
+
+static const struct abx500_pingroup ab8540_groups[] = {
+       /* default column */
+       AB8540_PIN_GROUP(sysclkreq2_d_1, ABX500_DEFAULT),
+       AB8540_PIN_GROUP(sysclkreq3_d_1, ABX500_DEFAULT),
+       AB8540_PIN_GROUP(sysclkreq4_d_1, ABX500_DEFAULT),
+       AB8540_PIN_GROUP(sysclkreq6_d_1, ABX500_DEFAULT),
+       AB8540_PIN_GROUP(pwmout1_d_1, ABX500_DEFAULT),
+       AB8540_PIN_GROUP(pwmout2_d_1, ABX500_DEFAULT),
+       AB8540_PIN_GROUP(pwmout3_d_1, ABX500_DEFAULT),
+       AB8540_PIN_GROUP(adi1_d_1, ABX500_DEFAULT),
+       AB8540_PIN_GROUP(dmic12_d_1, ABX500_DEFAULT),
+       AB8540_PIN_GROUP(dmic34_d_1, ABX500_DEFAULT),
+       AB8540_PIN_GROUP(dmic56_d_1, ABX500_DEFAULT),
+       AB8540_PIN_GROUP(sysclkreq5_d_1, ABX500_DEFAULT),
+       AB8540_PIN_GROUP(batremn_d_1, ABX500_DEFAULT),
+       AB8540_PIN_GROUP(service_d_1, ABX500_DEFAULT),
+       AB8540_PIN_GROUP(pwrctrl0_d_1, ABX500_DEFAULT),
+       AB8540_PIN_GROUP(pwrctrl1_d_1, ABX500_DEFAULT),
+       AB8540_PIN_GROUP(pwmextvibra1_d_1, ABX500_DEFAULT),
+       AB8540_PIN_GROUP(pwmextvibra2_d_1, ABX500_DEFAULT),
+       AB8540_PIN_GROUP(gpio1_vbat_d_1, ABX500_DEFAULT),
+       AB8540_PIN_GROUP(gpio2_vbat_d_1, ABX500_DEFAULT),
+       AB8540_PIN_GROUP(gpio3_vbat_d_1, ABX500_DEFAULT),
+       AB8540_PIN_GROUP(gpio4_vbat_d_1, ABX500_DEFAULT),
+       AB8540_PIN_GROUP(pdmclkdat_d_1, ABX500_DEFAULT),
+       /* Altfunction A column */
+       AB8540_PIN_GROUP(gpio1_a_1, ABX500_ALT_A),
+       AB8540_PIN_GROUP(gpio2_a_1, ABX500_ALT_A),
+       AB8540_PIN_GROUP(gpio3_a_1, ABX500_ALT_A),
+       AB8540_PIN_GROUP(gpio4_a_1, ABX500_ALT_A),
+       AB8540_PIN_GROUP(gpio14_a_1, ABX500_ALT_A),
+       AB8540_PIN_GROUP(gpio15_a_1, ABX500_ALT_A),
+       AB8540_PIN_GROUP(gpio16_a_1, ABX500_ALT_A),
+       AB8540_PIN_GROUP(gpio17_a_1, ABX500_ALT_A),
+       AB8540_PIN_GROUP(gpio18_a_1, ABX500_ALT_A),
+       AB8540_PIN_GROUP(gpio19_a_1, ABX500_ALT_A),
+       AB8540_PIN_GROUP(gpio20_a_1, ABX500_ALT_A),
+       AB8540_PIN_GROUP(gpio27_a_1, ABX500_ALT_A),
+       AB8540_PIN_GROUP(gpio28_a_1, ABX500_ALT_A),
+       AB8540_PIN_GROUP(gpio29_a_1, ABX500_ALT_A),
+       AB8540_PIN_GROUP(gpio30_a_1, ABX500_ALT_A),
+       AB8540_PIN_GROUP(gpio31_a_1, ABX500_ALT_A),
+       AB8540_PIN_GROUP(gpio32_a_1, ABX500_ALT_A),
+       AB8540_PIN_GROUP(gpio42_a_1, ABX500_ALT_A),
+       AB8540_PIN_GROUP(gpio43_a_1, ABX500_ALT_A),
+       AB8540_PIN_GROUP(gpio44_a_1, ABX500_ALT_A),
+       AB8540_PIN_GROUP(gpio45_a_1, ABX500_ALT_A),
+       AB8540_PIN_GROUP(gpio46_a_1, ABX500_ALT_A),
+       AB8540_PIN_GROUP(gpio47_a_1, ABX500_ALT_A),
+       AB8540_PIN_GROUP(gpio48_a_1, ABX500_ALT_A),
+       AB8540_PIN_GROUP(gpio51_a_1, ABX500_ALT_A),
+       AB8540_PIN_GROUP(gpio52_a_1, ABX500_ALT_A),
+       AB8540_PIN_GROUP(gpio53_a_1, ABX500_ALT_A),
+       AB8540_PIN_GROUP(gpio54_a_1, ABX500_ALT_A),
+       AB8540_PIN_GROUP(gpio55_a_1, ABX500_ALT_A),
+       AB8540_PIN_GROUP(gpio56_a_1, ABX500_ALT_A),
+};
+
+/* We use this macro to define the groups applicable to a function */
+#define AB8540_FUNC_GROUPS(a, b...)       \
+static const char * const a##_groups[] = { b };
+
+AB8540_FUNC_GROUPS(sysclkreq, "sysclkreq2_d_1", "sysclkreq3_d_1",
+               "sysclkreq4_d_1", "sysclkreq5_d_1", "sysclkreq6_d_1");
+AB8540_FUNC_GROUPS(gpio, "gpio1_a_1", "gpio2_a_1", "gpio3_a_1", "gpio4_a_1",
+               "gpio14_a_1", "gpio15_a_1", "gpio16_a_1", "gpio17_a_1",
+               "gpio18_a_1", "gpio19_a_1", "gpio20_a_1", "gpio27_a_1",
+               "gpio28_a_1", "gpio29_a_1", "gpio30_a_1", "gpio31_a_1",
+               "gpio32_a_1", "gpio42_a_1", "gpio43_a_1", "gpio44_a_1",
+               "gpio45_a_1", "gpio46_a_1", "gpio47_a_1", "gpio48_a_1",
+               "gpio51_a_1", "gpio52_a_1", "gpio53_a_1", "gpio54_a_1",
+               "gpio55_a_1", "gpio56_a_1");
+AB8540_FUNC_GROUPS(pwmout, "pwmout1_d_1", "pwmout2_d_1", "pwmout3_d_1");
+AB8540_FUNC_GROUPS(adi1, "adi1_d_1");
+AB8540_FUNC_GROUPS(dmic, "dmic12_d_1", "dmic34_d_1", "dmic56_d_1");
+AB8540_FUNC_GROUPS(batremn, "batremn_d_1");
+AB8540_FUNC_GROUPS(service, "service_d_1");
+AB8540_FUNC_GROUPS(pwrctrl, "pwrctrl0_d_1", "pwrctrl1_d_1");
+AB8540_FUNC_GROUPS(pwmextvibra, "pwmextvibra1_d_1", "pwmextvibra2_d_1");
+AB8540_FUNC_GROUPS(gpio_vbat, "gpio1_vbat_d_1", "gpio2_vbat_d_1",
+               "gpio3_vbat_d_1", "gpio4_vbat_d_1");
+AB8540_FUNC_GROUPS(pdm, "pdmclkdat_d_1");
+
+#define FUNCTION(fname)                                        \
+       {                                               \
+               .name = #fname,                         \
+               .groups = fname##_groups,               \
+               .ngroups = ARRAY_SIZE(fname##_groups),  \
+       }
+
+static const struct abx500_function ab8540_functions[] = {
+       FUNCTION(sysclkreq),
+       FUNCTION(gpio),
+       FUNCTION(pwmout),
+       FUNCTION(adi1),
+       FUNCTION(dmic),
+       FUNCTION(batremn),
+       FUNCTION(service),
+       FUNCTION(pwrctrl),
+       FUNCTION(pwmextvibra),
+       FUNCTION(gpio_vbat),
+       FUNCTION(pdm),
+};
+
+/*
+ * this table translates what's is in the AB8540 specification regarding the
+ * balls alternate functions (as for DB, default, ALT_A, ALT_B and ALT_C).
+ * ALTERNATE_FUNCTIONS(GPIO_NUMBER, GPIOSEL bit, ALTERNATFUNC bit1,
+ * ALTERNATEFUNC bit2, ALTA val, ALTB val, ALTC val),
+ * AB8540 only supports DEFAULT and ALTA functions, so ALTERNATFUNC
+ * registers is not used
+ *
+ */
+
+struct alternate_functions ab8540_alternate_functions[AB8540_GPIO_MAX_NUMBER + 1] = {
+       /* GPIOSEL1 - bit 4-7 reserved */
+       ALTERNATE_FUNCTIONS(0, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO0 */
+       ALTERNATE_FUNCTIONS(1,      0, UNUSED, UNUSED, 0, 0, 0), /* GPIO1, altA controlled by bit 0 */
+       ALTERNATE_FUNCTIONS(2,      1, UNUSED, UNUSED, 0, 0, 0), /* GPIO2, altA controlled by bit 1 */
+       ALTERNATE_FUNCTIONS(3,      2, UNUSED, UNUSED, 0, 0, 0), /* GPIO3, altA controlled by bit 2*/
+       ALTERNATE_FUNCTIONS(4,      3, UNUSED, UNUSED, 0, 0, 0), /* GPIO4, altA controlled by bit 3*/
+       ALTERNATE_FUNCTIONS(5, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO5 */
+       ALTERNATE_FUNCTIONS(6, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO6 */
+       ALTERNATE_FUNCTIONS(7, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO7 */
+       ALTERNATE_FUNCTIONS(8, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO8 */
+       /* GPIOSEL2 - bit 0-4 reserved */
+       ALTERNATE_FUNCTIONS(9,  UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO9 */
+       ALTERNATE_FUNCTIONS(10, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO10 */
+       ALTERNATE_FUNCTIONS(11, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO11 */
+       ALTERNATE_FUNCTIONS(12, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO12 */
+       ALTERNATE_FUNCTIONS(13, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO13 */
+       ALTERNATE_FUNCTIONS(14,      5, UNUSED, UNUSED, 0, 0, 0), /* GPIO14, altA controlled by bit 5 */
+       ALTERNATE_FUNCTIONS(15,      6, UNUSED, UNUSED, 0, 0, 0), /* GPIO15, altA controlled by bit 6 */
+       ALTERNATE_FUNCTIONS(16,      7, UNUSED, UNUSED, 0, 0, 0), /* GPIO16, altA controlled by bit 7 */
+       /* GPIOSEL3 - bit 4-7 reserved */
+       ALTERNATE_FUNCTIONS(17,      0, UNUSED, UNUSED, 0, 0, 0), /* GPIO17, altA controlled by bit 0 */
+       ALTERNATE_FUNCTIONS(18,      1, UNUSED, UNUSED, 0, 0, 0), /* GPIO18, altA controlled by bit 1 */
+       ALTERNATE_FUNCTIONS(19,      2, UNUSED, UNUSED, 0, 0, 0), /* GPIO19, altA controlled by bit 2 */
+       ALTERNATE_FUNCTIONS(20,      3, UNUSED, UNUSED, 0, 0, 0), /* GPIO20, altA controlled by bit 3 */
+       ALTERNATE_FUNCTIONS(21, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO21 */
+       ALTERNATE_FUNCTIONS(22, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO22 */
+       ALTERNATE_FUNCTIONS(23, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO23 */
+       ALTERNATE_FUNCTIONS(24, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO24 */
+       /* GPIOSEL4 - bit 0-1 reserved */
+       ALTERNATE_FUNCTIONS(25, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO25 */
+       ALTERNATE_FUNCTIONS(26, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO26 */
+       ALTERNATE_FUNCTIONS(27,      2, UNUSED, UNUSED, 0, 0, 0), /* GPIO27, altA controlled by bit 2 */
+       ALTERNATE_FUNCTIONS(28,      3, UNUSED, UNUSED, 0, 0, 0), /* GPIO28, altA controlled by bit 3 */
+       ALTERNATE_FUNCTIONS(29,      4, UNUSED, UNUSED, 0, 0, 0), /* GPIO29, altA controlled by bit 4 */
+       ALTERNATE_FUNCTIONS(30,      5, UNUSED, UNUSED, 0, 0, 0), /* GPIO30, altA controlled by bit 5 */
+       ALTERNATE_FUNCTIONS(31,      6, UNUSED, UNUSED, 0, 0, 0), /* GPIO31, altA controlled by bit 6 */
+       ALTERNATE_FUNCTIONS(32,      7, UNUSED, UNUSED, 0, 0, 0), /* GPIO32, altA controlled by bit 7 */
+       /* GPIOSEL5 - bit 0-7 reserved */
+       ALTERNATE_FUNCTIONS(33, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO33 */
+       ALTERNATE_FUNCTIONS(34, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO34 */
+       ALTERNATE_FUNCTIONS(35, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO35 */
+       ALTERNATE_FUNCTIONS(36, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO36 */
+       ALTERNATE_FUNCTIONS(37, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO37 */
+       ALTERNATE_FUNCTIONS(38, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO38 */
+       ALTERNATE_FUNCTIONS(39, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO39 */
+       ALTERNATE_FUNCTIONS(40, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO40 */
+       /* GPIOSEL6 - bit 0 reserved */
+       ALTERNATE_FUNCTIONS(41, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO41 */
+       ALTERNATE_FUNCTIONS(42,      1, UNUSED, UNUSED, 0, 0, 0), /* GPIO42, altA controlled by bit 1 */
+       ALTERNATE_FUNCTIONS(43,      2, UNUSED, UNUSED, 0, 0, 0), /* GPIO43, altA controlled by bit 2 */
+       ALTERNATE_FUNCTIONS(44,      3, UNUSED, UNUSED, 0, 0, 0), /* GPIO44, altA controlled by bit 3 */
+       ALTERNATE_FUNCTIONS(45,      4, UNUSED, UNUSED, 0, 0, 0), /* GPIO45, altA controlled by bit 4 */
+       ALTERNATE_FUNCTIONS(46,      5, UNUSED, UNUSED, 0, 0, 0), /* GPIO46, altA controlled by bit 5 */
+       ALTERNATE_FUNCTIONS(47,      6, UNUSED, UNUSED, 0, 0, 0), /* GPIO47, altA controlled by bit 6 */
+       ALTERNATE_FUNCTIONS(48,      7, UNUSED, UNUSED, 0, 0, 0), /* GPIO48, altA controlled by bit 7 */
+       /* GPIOSEL7 - bit 0-1 reserved */
+       ALTERNATE_FUNCTIONS(49, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO49 */
+       ALTERNATE_FUNCTIONS(50, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO50 */
+       ALTERNATE_FUNCTIONS(51,      2, UNUSED, UNUSED, 0, 0, 0), /* GPIO51, altA controlled by bit 2 */
+       ALTERNATE_FUNCTIONS(52,      3, UNUSED, UNUSED, 0, 0, 0), /* GPIO52, altA controlled by bit 3 */
+       ALTERNATE_FUNCTIONS(53,      4, UNUSED, UNUSED, 0, 0, 0), /* GPIO53, altA controlled by bit 4 */
+       ALTERNATE_FUNCTIONS(54,      5, UNUSED, UNUSED, 0, 0, 0), /* GPIO54, altA controlled by bit 5 */
+       ALTERNATE_FUNCTIONS(55,      6, UNUSED, UNUSED, 0, 0, 0), /* GPIO55, altA controlled by bit 6 */
+       ALTERNATE_FUNCTIONS(56,      7, UNUSED, UNUSED, 0, 0, 0), /* GPIO56, altA controlled by bit 7 */
+};
+
+static struct pullud ab8540_pullud = {
+       .first_pin = 51,        /* GPIO1_VBAT */
+       .last_pin = 54,         /* GPIO4_VBAT */
+};
+
+/*
+ * For AB8540 Only some GPIOs are interrupt capable:
+ *     GPIO43 to GPIO44
+ *     GPIO51 to GPIO54
+ */
+struct abx500_gpio_irq_cluster ab8540_gpio_irq_cluster[] = {
+       GPIO_IRQ_CLUSTER(43, 43, AB8540_INT_GPIO43F),
+       GPIO_IRQ_CLUSTER(44, 44, AB8540_INT_GPIO44F),
+       GPIO_IRQ_CLUSTER(51, 54, AB9540_INT_GPIO51R),
+};
+
+static struct abx500_pinctrl_soc_data ab8540_soc = {
+       .gpio_ranges = ab8540_pinranges,
+       .gpio_num_ranges = ARRAY_SIZE(ab8540_pinranges),
+       .pins = ab8540_pins,
+       .npins = ARRAY_SIZE(ab8540_pins),
+       .functions = ab8540_functions,
+       .nfunctions = ARRAY_SIZE(ab8540_functions),
+       .groups = ab8540_groups,
+       .ngroups = ARRAY_SIZE(ab8540_groups),
+       .alternate_functions = ab8540_alternate_functions,
+       .pullud = &ab8540_pullud,
+       .gpio_irq_cluster = ab8540_gpio_irq_cluster,
+       .ngpio_irq_cluster = ARRAY_SIZE(ab8540_gpio_irq_cluster),
+       .irq_gpio_rising_offset = AB8540_INT_GPIO43R,
+       .irq_gpio_falling_offset = AB8540_INT_GPIO43F,
+       .irq_gpio_factor = 2,
+};
+
+void
+abx500_pinctrl_ab8540_init(struct abx500_pinctrl_soc_data **soc)
+{
+       *soc = &ab8540_soc;
+}
diff --git a/drivers/pinctrl/pinctrl-ab9540.c b/drivers/pinctrl/pinctrl-ab9540.c
new file mode 100644 (file)
index 0000000..7610bd0
--- /dev/null
@@ -0,0 +1,485 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2012
+ *
+ * Author: Patrice Chotard <patrice.chotard@stericsson.com> for ST-Ericsson.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/mfd/abx500/ab8500.h>
+#include "pinctrl-abx500.h"
+
+/* All the pins that can be used for GPIO and some other functions */
+#define ABX500_GPIO(offset)            (offset)
+
+#define AB9540_PIN_R4          ABX500_GPIO(1)
+#define AB9540_PIN_V3          ABX500_GPIO(2)
+#define AB9540_PIN_T4          ABX500_GPIO(3)
+#define AB9540_PIN_T5          ABX500_GPIO(4)
+/* hole */
+#define AB9540_PIN_B18         ABX500_GPIO(10)
+#define AB9540_PIN_C18         ABX500_GPIO(11)
+/* hole */
+#define AB9540_PIN_D18         ABX500_GPIO(13)
+#define AB9540_PIN_B19         ABX500_GPIO(14)
+#define AB9540_PIN_C19         ABX500_GPIO(15)
+#define AB9540_PIN_D19         ABX500_GPIO(16)
+#define AB9540_PIN_R3          ABX500_GPIO(17)
+#define AB9540_PIN_T2          ABX500_GPIO(18)
+#define AB9540_PIN_U2          ABX500_GPIO(19)
+#define AB9540_PIN_V2          ABX500_GPIO(20)
+#define AB9540_PIN_N17         ABX500_GPIO(21)
+#define AB9540_PIN_N16         ABX500_GPIO(22)
+#define AB9540_PIN_M19         ABX500_GPIO(23)
+#define AB9540_PIN_T3          ABX500_GPIO(24)
+#define AB9540_PIN_W2          ABX500_GPIO(25)
+/* hole */
+#define AB9540_PIN_H4          ABX500_GPIO(27)
+#define AB9540_PIN_F1          ABX500_GPIO(28)
+#define AB9540_PIN_F4          ABX500_GPIO(29)
+#define AB9540_PIN_F2          ABX500_GPIO(30)
+#define AB9540_PIN_E4          ABX500_GPIO(31)
+#define AB9540_PIN_F3          ABX500_GPIO(32)
+/* hole */
+#define AB9540_PIN_J13         ABX500_GPIO(34)
+/* hole */
+#define AB9540_PIN_L17         ABX500_GPIO(40)
+#define AB9540_PIN_L16         ABX500_GPIO(41)
+#define AB9540_PIN_W3          ABX500_GPIO(42)
+#define AB9540_PIN_N4          ABX500_GPIO(50)
+#define AB9540_PIN_G12         ABX500_GPIO(51)
+#define AB9540_PIN_E17         ABX500_GPIO(52)
+#define AB9540_PIN_D11         ABX500_GPIO(53)
+#define AB9540_PIN_M18         ABX500_GPIO(54)
+
+/* indicates the highest GPIO number */
+#define AB9540_GPIO_MAX_NUMBER 54
+
+/*
+ * The names of the pins are denoted by GPIO number and ball name, even
+ * though they can be used for other things than GPIO, this is the first
+ * column in the table of the data sheet and often used on schematics and
+ * such.
+ */
+static const struct pinctrl_pin_desc ab9540_pins[] = {
+       PINCTRL_PIN(AB9540_PIN_R4, "GPIO1_R4"),
+       PINCTRL_PIN(AB9540_PIN_V3, "GPIO2_V3"),
+       PINCTRL_PIN(AB9540_PIN_T4, "GPIO3_T4"),
+       PINCTRL_PIN(AB9540_PIN_T5, "GPIO4_T5"),
+       /* hole */
+       PINCTRL_PIN(AB9540_PIN_B18, "GPIO10_B18"),
+       PINCTRL_PIN(AB9540_PIN_C18, "GPIO11_C18"),
+       /* hole */
+       PINCTRL_PIN(AB9540_PIN_D18, "GPIO13_D18"),
+       PINCTRL_PIN(AB9540_PIN_B19, "GPIO14_B19"),
+       PINCTRL_PIN(AB9540_PIN_C19, "GPIO15_C19"),
+       PINCTRL_PIN(AB9540_PIN_D19, "GPIO16_D19"),
+       PINCTRL_PIN(AB9540_PIN_R3, "GPIO17_R3"),
+       PINCTRL_PIN(AB9540_PIN_T2, "GPIO18_T2"),
+       PINCTRL_PIN(AB9540_PIN_U2, "GPIO19_U2"),
+       PINCTRL_PIN(AB9540_PIN_V2, "GPIO20_V2"),
+       PINCTRL_PIN(AB9540_PIN_N17, "GPIO21_N17"),
+       PINCTRL_PIN(AB9540_PIN_N16, "GPIO22_N16"),
+       PINCTRL_PIN(AB9540_PIN_M19, "GPIO23_M19"),
+       PINCTRL_PIN(AB9540_PIN_T3, "GPIO24_T3"),
+       PINCTRL_PIN(AB9540_PIN_W2, "GPIO25_W2"),
+       /* hole */
+       PINCTRL_PIN(AB9540_PIN_H4, "GPIO27_H4"),
+       PINCTRL_PIN(AB9540_PIN_F1, "GPIO28_F1"),
+       PINCTRL_PIN(AB9540_PIN_F4, "GPIO29_F4"),
+       PINCTRL_PIN(AB9540_PIN_F2, "GPIO30_F2"),
+       PINCTRL_PIN(AB9540_PIN_E4, "GPIO31_E4"),
+       PINCTRL_PIN(AB9540_PIN_F3, "GPIO32_F3"),
+       /* hole */
+       PINCTRL_PIN(AB9540_PIN_J13, "GPIO34_J13"),
+       /* hole */
+       PINCTRL_PIN(AB9540_PIN_L17, "GPIO40_L17"),
+       PINCTRL_PIN(AB9540_PIN_L16, "GPIO41_L16"),
+       PINCTRL_PIN(AB9540_PIN_W3, "GPIO42_W3"),
+       PINCTRL_PIN(AB9540_PIN_N4, "GPIO50_N4"),
+       PINCTRL_PIN(AB9540_PIN_G12, "GPIO51_G12"),
+       PINCTRL_PIN(AB9540_PIN_E17, "GPIO52_E17"),
+       PINCTRL_PIN(AB9540_PIN_D11, "GPIO53_D11"),
+       PINCTRL_PIN(AB9540_PIN_M18, "GPIO60_M18"),
+};
+
+/*
+ * Maps local GPIO offsets to local pin numbers
+ */
+static const struct abx500_pinrange ab9540_pinranges[] = {
+       ABX500_PINRANGE(1, 4, ABX500_ALT_A),
+       ABX500_PINRANGE(10, 2, ABX500_DEFAULT),
+       ABX500_PINRANGE(13, 1, ABX500_DEFAULT),
+       ABX500_PINRANGE(14, 12, ABX500_ALT_A),
+       ABX500_PINRANGE(27, 6, ABX500_ALT_A),
+       ABX500_PINRANGE(34, 1, ABX500_ALT_A),
+       ABX500_PINRANGE(40, 3, ABX500_ALT_A),
+       ABX500_PINRANGE(50, 1, ABX500_DEFAULT),
+       ABX500_PINRANGE(51, 3, ABX500_ALT_A),
+       ABX500_PINRANGE(54, 1, ABX500_DEFAULT),
+};
+
+/*
+ * Read the pin group names like this:
+ * sysclkreq2_d_1 = first groups of pins for sysclkreq2 on default function
+ *
+ * The groups are arranged as sets per altfunction column, so we can
+ * mux in one group at a time by selecting the same altfunction for them
+ * all. When functions require pins on different altfunctions, you need
+ * to combine several groups.
+ */
+
+/* default column */
+static const unsigned sysclkreq2_d_1_pins[] = { AB9540_PIN_R4 };
+static const unsigned sysclkreq3_d_1_pins[] = { AB9540_PIN_V3 };
+static const unsigned sysclkreq4_d_1_pins[] = { AB9540_PIN_T4 };
+static const unsigned sysclkreq6_d_1_pins[] = { AB9540_PIN_T5 };
+static const unsigned gpio10_d_1_pins[] = { AB9540_PIN_B18 };
+static const unsigned gpio11_d_1_pins[] = { AB9540_PIN_C18 };
+static const unsigned gpio13_d_1_pins[] = { AB9540_PIN_D18 };
+static const unsigned pwmout1_d_1_pins[] = { AB9540_PIN_B19 };
+static const unsigned pwmout2_d_1_pins[] = { AB9540_PIN_C19 };
+static const unsigned pwmout3_d_1_pins[] = { AB9540_PIN_D19 };
+/* audio data interface 1*/
+static const unsigned adi1_d_1_pins[] = { AB9540_PIN_R3, AB9540_PIN_T2,
+                                       AB9540_PIN_U2, AB9540_PIN_V2 };
+/* USBUICC */
+static const unsigned usbuicc_d_1_pins[] = { AB9540_PIN_N17, AB9540_PIN_N16,
+                                       AB9540_PIN_M19 };
+static const unsigned sysclkreq7_d_1_pins[] = { AB9540_PIN_T3 };
+static const unsigned sysclkreq8_d_1_pins[] = { AB9540_PIN_W2 };
+/* Digital microphone 1 and 2 */
+static const unsigned dmic12_d_1_pins[] = { AB9540_PIN_H4, AB9540_PIN_F1 };
+/* Digital microphone 3 and 4 */
+static const unsigned dmic34_d_1_pins[] = { AB9540_PIN_F4, AB9540_PIN_F2 };
+/* Digital microphone 5 and 6 */
+static const unsigned dmic56_d_1_pins[] = { AB9540_PIN_E4, AB9540_PIN_F3 };
+static const unsigned extcpena_d_1_pins[] = { AB9540_PIN_J13 };
+/* modem SDA/SCL */
+static const unsigned modsclsda_d_1_pins[] = { AB9540_PIN_L17, AB9540_PIN_L16 };
+static const unsigned sysclkreq5_d_1_pins[] = { AB9540_PIN_W3 };
+static const unsigned gpio50_d_1_pins[] = { AB9540_PIN_N4 };
+static const unsigned batremn_d_1_pins[] = { AB9540_PIN_G12 };
+static const unsigned resethw_d_1_pins[] = { AB9540_PIN_E17 };
+static const unsigned service_d_1_pins[] = { AB9540_PIN_D11 };
+static const unsigned gpio60_d_1_pins[] = { AB9540_PIN_M18 };
+
+/* Altfunction A column */
+static const unsigned gpio1_a_1_pins[] = { AB9540_PIN_R4 };
+static const unsigned gpio2_a_1_pins[] = { AB9540_PIN_V3 };
+static const unsigned gpio3_a_1_pins[] = { AB9540_PIN_T4 };
+static const unsigned gpio4_a_1_pins[] = { AB9540_PIN_T5 };
+static const unsigned hiqclkena_a_1_pins[] = { AB9540_PIN_B18 };
+static const unsigned pdmclk_a_1_pins[] = { AB9540_PIN_C18 };
+static const unsigned uartdata_a_1_pins[] = { AB9540_PIN_D18, AB9540_PIN_N4 };
+static const unsigned gpio14_a_1_pins[] = { AB9540_PIN_B19 };
+static const unsigned gpio15_a_1_pins[] = { AB9540_PIN_C19 };
+static const unsigned gpio16_a_1_pins[] = { AB9540_PIN_D19 };
+static const unsigned gpio17_a_1_pins[] = { AB9540_PIN_R3 };
+static const unsigned gpio18_a_1_pins[] = { AB9540_PIN_T2 };
+static const unsigned gpio19_a_1_pins[] = { AB9540_PIN_U2 };
+static const unsigned gpio20_a_1_pins[] = { AB9540_PIN_V2 };
+static const unsigned gpio21_a_1_pins[] = { AB9540_PIN_N17 };
+static const unsigned gpio22_a_1_pins[] = { AB9540_PIN_N16 };
+static const unsigned gpio23_a_1_pins[] = { AB9540_PIN_M19 };
+static const unsigned gpio24_a_1_pins[] = { AB9540_PIN_T3 };
+static const unsigned gpio25_a_1_pins[] = { AB9540_PIN_W2 };
+static const unsigned gpio27_a_1_pins[] = { AB9540_PIN_H4 };
+static const unsigned gpio28_a_1_pins[] = { AB9540_PIN_F1 };
+static const unsigned gpio29_a_1_pins[] = { AB9540_PIN_F4 };
+static const unsigned gpio30_a_1_pins[] = { AB9540_PIN_F2 };
+static const unsigned gpio31_a_1_pins[] = { AB9540_PIN_E4 };
+static const unsigned gpio32_a_1_pins[] = { AB9540_PIN_F3 };
+static const unsigned gpio34_a_1_pins[] = { AB9540_PIN_J13 };
+static const unsigned gpio40_a_1_pins[] = { AB9540_PIN_L17 };
+static const unsigned gpio41_a_1_pins[] = { AB9540_PIN_L16 };
+static const unsigned gpio42_a_1_pins[] = { AB9540_PIN_W3 };
+static const unsigned gpio51_a_1_pins[] = { AB9540_PIN_G12 };
+static const unsigned gpio52_a_1_pins[] = { AB9540_PIN_E17 };
+static const unsigned gpio53_a_1_pins[] = { AB9540_PIN_D11 };
+static const unsigned usbuiccpd_a_1_pins[] = { AB9540_PIN_M18 };
+
+/* Altfunction B colum */
+static const unsigned pdmdata_b_1_pins[] = { AB9540_PIN_B18 };
+static const unsigned pwmextvibra1_b_1_pins[] = { AB9540_PIN_D18 };
+static const unsigned pwmextvibra2_b_1_pins[] = { AB9540_PIN_N4 };
+
+/* Altfunction C column */
+static const unsigned usbvdat_c_1_pins[] = { AB9540_PIN_D18 };
+
+#define AB9540_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins,         \
+                       .npins = ARRAY_SIZE(a##_pins), .altsetting = b }
+
+static const struct abx500_pingroup ab9540_groups[] = {
+       /* default column */
+       AB9540_PIN_GROUP(sysclkreq2_d_1, ABX500_DEFAULT),
+       AB9540_PIN_GROUP(sysclkreq3_d_1, ABX500_DEFAULT),
+       AB9540_PIN_GROUP(sysclkreq4_d_1, ABX500_DEFAULT),
+       AB9540_PIN_GROUP(sysclkreq6_d_1, ABX500_DEFAULT),
+       AB9540_PIN_GROUP(gpio10_d_1, ABX500_DEFAULT),
+       AB9540_PIN_GROUP(gpio11_d_1, ABX500_DEFAULT),
+       AB9540_PIN_GROUP(gpio13_d_1, ABX500_DEFAULT),
+       AB9540_PIN_GROUP(pwmout1_d_1, ABX500_DEFAULT),
+       AB9540_PIN_GROUP(pwmout2_d_1, ABX500_DEFAULT),
+       AB9540_PIN_GROUP(pwmout3_d_1, ABX500_DEFAULT),
+       AB9540_PIN_GROUP(adi1_d_1, ABX500_DEFAULT),
+       AB9540_PIN_GROUP(usbuicc_d_1, ABX500_DEFAULT),
+       AB9540_PIN_GROUP(sysclkreq7_d_1, ABX500_DEFAULT),
+       AB9540_PIN_GROUP(sysclkreq8_d_1, ABX500_DEFAULT),
+       AB9540_PIN_GROUP(dmic12_d_1, ABX500_DEFAULT),
+       AB9540_PIN_GROUP(dmic34_d_1, ABX500_DEFAULT),
+       AB9540_PIN_GROUP(dmic56_d_1, ABX500_DEFAULT),
+       AB9540_PIN_GROUP(extcpena_d_1, ABX500_DEFAULT),
+       AB9540_PIN_GROUP(modsclsda_d_1, ABX500_DEFAULT),
+       AB9540_PIN_GROUP(sysclkreq5_d_1, ABX500_DEFAULT),
+       AB9540_PIN_GROUP(gpio50_d_1, ABX500_DEFAULT),
+       AB9540_PIN_GROUP(batremn_d_1, ABX500_DEFAULT),
+       AB9540_PIN_GROUP(resethw_d_1, ABX500_DEFAULT),
+       AB9540_PIN_GROUP(service_d_1, ABX500_DEFAULT),
+       AB9540_PIN_GROUP(gpio60_d_1, ABX500_DEFAULT),
+
+       /* Altfunction A column */
+       AB9540_PIN_GROUP(gpio1_a_1, ABX500_ALT_A),
+       AB9540_PIN_GROUP(gpio2_a_1, ABX500_ALT_A),
+       AB9540_PIN_GROUP(gpio3_a_1, ABX500_ALT_A),
+       AB9540_PIN_GROUP(gpio4_a_1, ABX500_ALT_A),
+       AB9540_PIN_GROUP(hiqclkena_a_1, ABX500_ALT_A),
+       AB9540_PIN_GROUP(pdmclk_a_1, ABX500_ALT_A),
+       AB9540_PIN_GROUP(uartdata_a_1, ABX500_ALT_A),
+       AB9540_PIN_GROUP(gpio14_a_1, ABX500_ALT_A),
+       AB9540_PIN_GROUP(gpio15_a_1, ABX500_ALT_A),
+       AB9540_PIN_GROUP(gpio16_a_1, ABX500_ALT_A),
+       AB9540_PIN_GROUP(gpio17_a_1, ABX500_ALT_A),
+       AB9540_PIN_GROUP(gpio18_a_1, ABX500_ALT_A),
+       AB9540_PIN_GROUP(gpio19_a_1, ABX500_ALT_A),
+       AB9540_PIN_GROUP(gpio20_a_1, ABX500_ALT_A),
+       AB9540_PIN_GROUP(gpio21_a_1, ABX500_ALT_A),
+       AB9540_PIN_GROUP(gpio22_a_1, ABX500_ALT_A),
+       AB9540_PIN_GROUP(gpio23_a_1, ABX500_ALT_A),
+       AB9540_PIN_GROUP(gpio24_a_1, ABX500_ALT_A),
+       AB9540_PIN_GROUP(gpio25_a_1, ABX500_ALT_A),
+       AB9540_PIN_GROUP(gpio27_a_1, ABX500_ALT_A),
+       AB9540_PIN_GROUP(gpio28_a_1, ABX500_ALT_A),
+       AB9540_PIN_GROUP(gpio29_a_1, ABX500_ALT_A),
+       AB9540_PIN_GROUP(gpio30_a_1, ABX500_ALT_A),
+       AB9540_PIN_GROUP(gpio31_a_1, ABX500_ALT_A),
+       AB9540_PIN_GROUP(gpio32_a_1, ABX500_ALT_A),
+       AB9540_PIN_GROUP(gpio34_a_1, ABX500_ALT_A),
+       AB9540_PIN_GROUP(gpio40_a_1, ABX500_ALT_A),
+       AB9540_PIN_GROUP(gpio41_a_1, ABX500_ALT_A),
+       AB9540_PIN_GROUP(gpio42_a_1, ABX500_ALT_A),
+       AB9540_PIN_GROUP(gpio51_a_1, ABX500_ALT_A),
+       AB9540_PIN_GROUP(gpio52_a_1, ABX500_ALT_A),
+       AB9540_PIN_GROUP(gpio53_a_1, ABX500_ALT_A),
+       AB9540_PIN_GROUP(usbuiccpd_a_1, ABX500_ALT_A),
+
+       /* Altfunction B column */
+       AB9540_PIN_GROUP(pdmdata_b_1, ABX500_ALT_B),
+       AB9540_PIN_GROUP(pwmextvibra1_b_1, ABX500_ALT_B),
+       AB9540_PIN_GROUP(pwmextvibra2_b_1, ABX500_ALT_B),
+
+       /* Altfunction C column */
+       AB9540_PIN_GROUP(usbvdat_c_1, ABX500_ALT_C),
+};
+
+/* We use this macro to define the groups applicable to a function */
+#define AB9540_FUNC_GROUPS(a, b...)       \
+static const char * const a##_groups[] = { b };
+
+AB9540_FUNC_GROUPS(sysclkreq, "sysclkreq2_d_1", "sysclkreq3_d_1",
+               "sysclkreq4_d_1", "sysclkreq5_d_1", "sysclkreq6_d_1",
+               "sysclkreq7_d_1", "sysclkreq8_d_1");
+AB9540_FUNC_GROUPS(gpio, "gpio1_a_1", "gpio2_a_1", "gpio3_a_1", "gpio4_a_1",
+               "gpio10_d_1", "gpio11_d_1", "gpio13_d_1", "gpio14_a_1",
+               "gpio15_a_1", "gpio16_a_1", "gpio17_a_1", "gpio18_a_1",
+               "gpio19_a_1", "gpio20_a_1", "gpio21_a_1", "gpio22_a_1",
+               "gpio23_a_1", "gpio24_a_1", "gpio25_a_1", "gpio27_a_1",
+               "gpio28_a_1", "gpio29_a_1", "gpio30_a_1", "gpio31_a_1",
+               "gpio32_a_1", "gpio34_a_1", "gpio40_a_1", "gpio41_a_1",
+               "gpio42_a_1", "gpio50_d_1", "gpio51_a_1", "gpio52_a_1",
+               "gpio53_a_1", "gpio60_d_1");
+AB9540_FUNC_GROUPS(pwmout, "pwmout1_d_1", "pwmout2_d_1", "pwmout3_d_1");
+AB9540_FUNC_GROUPS(adi1, "adi1_d_1");
+AB9540_FUNC_GROUPS(usbuicc, "usbuicc_d_1", "usbuiccpd_a_1");
+AB9540_FUNC_GROUPS(dmic, "dmic12_d_1", "dmic34_d_1", "dmic56_d_1");
+AB9540_FUNC_GROUPS(extcpena, "extcpena_d_1");
+AB9540_FUNC_GROUPS(modsclsda, "modsclsda_d_1");
+AB9540_FUNC_GROUPS(batremn, "batremn_d_1");
+AB9540_FUNC_GROUPS(resethw, "resethw_d_1");
+AB9540_FUNC_GROUPS(service, "service_d_1");
+AB9540_FUNC_GROUPS(hiqclkena, "hiqclkena_a_1");
+AB9540_FUNC_GROUPS(pdm, "pdmdata_b_1", "pdmclk_a_1");
+AB9540_FUNC_GROUPS(uartdata, "uartdata_a_1");
+AB9540_FUNC_GROUPS(pwmextvibra, "pwmextvibra1_b_1", "pwmextvibra2_b_1");
+AB9540_FUNC_GROUPS(usbvdat, "usbvdat_c_1");
+
+#define FUNCTION(fname)                                        \
+       {                                               \
+               .name = #fname,                         \
+               .groups = fname##_groups,               \
+               .ngroups = ARRAY_SIZE(fname##_groups),  \
+       }
+
+static const struct abx500_function ab9540_functions[] = {
+       FUNCTION(sysclkreq),
+       FUNCTION(gpio),
+       FUNCTION(pwmout),
+       FUNCTION(adi1),
+       FUNCTION(usbuicc),
+       FUNCTION(dmic),
+       FUNCTION(extcpena),
+       FUNCTION(modsclsda),
+       FUNCTION(batremn),
+       FUNCTION(resethw),
+       FUNCTION(service),
+       FUNCTION(hiqclkena),
+       FUNCTION(pdm),
+       FUNCTION(uartdata),
+       FUNCTION(pwmextvibra),
+       FUNCTION(usbvdat),
+};
+
+/*
+ * this table translates what's is in the AB9540 specification regarding the
+ * balls alternate functions (as for DB, default, ALT_A, ALT_B and ALT_C).
+ * ALTERNATE_FUNCTIONS(GPIO_NUMBER, GPIOSEL bit, ALTERNATFUNC bit1,
+ * ALTERNATEFUNC bit2, ALTA val, ALTB val, ALTC val),
+ *
+ * example :
+ *
+ *     ALTERNATE_FUNCTIONS(13,     4,      3,      4, 1, 0, 2),
+ *     means that pin AB9540_PIN_D18 (pin 13) supports 4 mux (default/ALT_A,
+ *     ALT_B and ALT_C), so GPIOSEL and ALTERNATFUNC registers are used to
+ *     select the mux. ALTA, ALTB and ALTC val indicates values to write in
+ *     ALTERNATFUNC register. We need to specifies these values as SOC
+ *     designers didn't apply the same logic on how to select mux in the
+ *     ABx500 family.
+ *
+ *     As this pins supports at least ALT_B mux, default mux is
+ *     selected by writing 1 in GPIOSEL bit :
+ *
+ *             | GPIOSEL bit=4 | alternatfunc bit2=4 | alternatfunc bit1=3
+ *     default |       1       |          0          |          0
+ *     alt_A   |       0       |          0          |          1
+ *     alt_B   |       0       |          0          |          0
+ *     alt_C   |       0       |          1          |          0
+ *
+ *     ALTERNATE_FUNCTIONS(1,      0, UNUSED, UNUSED),
+ *     means that pin AB9540_PIN_R4 (pin 1) supports 2 mux, so only GPIOSEL
+ *     register is used to select the mux. As this pins doesn't support at
+ *     least ALT_B mux, default mux is by writing 0 in GPIOSEL bit :
+ *
+ *             | GPIOSEL bit=0 | alternatfunc bit2=  | alternatfunc bit1=
+ *     default |       0       |          0          |          0
+ *     alt_A   |       1       |          0          |          0
+ */
+
+struct alternate_functions ab9540alternate_functions[AB9540_GPIO_MAX_NUMBER + 1] = {
+       /* GPIOSEL1 - bits 4-7 are reserved */
+       ALTERNATE_FUNCTIONS(0, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO0 */
+       ALTERNATE_FUNCTIONS(1,      0, UNUSED, UNUSED, 0, 0, 0), /* GPIO1, altA controlled by bit 0 */
+       ALTERNATE_FUNCTIONS(2,      1, UNUSED, UNUSED, 0, 0, 0), /* GPIO2, altA controlled by bit 1 */
+       ALTERNATE_FUNCTIONS(3,      2, UNUSED, UNUSED, 0, 0, 0), /* GPIO3, altA controlled by bit 2*/
+       ALTERNATE_FUNCTIONS(4,      3, UNUSED, UNUSED, 0, 0, 0), /* GPIO4, altA controlled by bit 3*/
+       ALTERNATE_FUNCTIONS(5, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO5 */
+       ALTERNATE_FUNCTIONS(6, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO6 */
+       ALTERNATE_FUNCTIONS(7, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO7 */
+       ALTERNATE_FUNCTIONS(8, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO8 */
+       /* GPIOSEL2 - bits 0 and 3 are reserved */
+       ALTERNATE_FUNCTIONS(9, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO9 */
+       ALTERNATE_FUNCTIONS(10,      1,      0, UNUSED, 1, 0, 0), /* GPIO10, altA and altB controlled by bit 0 */
+       ALTERNATE_FUNCTIONS(11,      2, UNUSED, UNUSED, 0, 0, 0), /* GPIO11, altA controlled by bit 1 */
+       ALTERNATE_FUNCTIONS(12, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO12 */
+       ALTERNATE_FUNCTIONS(13,      4,      3,      4, 1, 0, 2), /* GPIO13, altA altB and altC controlled by bit 3 and 4 */
+       ALTERNATE_FUNCTIONS(14,      5, UNUSED, UNUSED, 0, 0, 0), /* GPIO14, altA controlled by bit 5 */
+       ALTERNATE_FUNCTIONS(15,      6, UNUSED, UNUSED, 0, 0, 0), /* GPIO15, altA controlled by bit 6 */
+       ALTERNATE_FUNCTIONS(16,      7, UNUSED, UNUSED, 0, 0, 0), /* GPIO16, altA controlled by bit 7 */
+       /* GPIOSEL3 - bit 1-3 reserved
+        * pins 17 to 20 are special case, only bit 0 is used to select
+        * alternate function for these 4 pins.
+        * bits 1 to 3 are reserved
+        */
+       ALTERNATE_FUNCTIONS(17,      0, UNUSED, UNUSED, 0, 0, 0), /* GPIO17, altA controlled by bit 0 */
+       ALTERNATE_FUNCTIONS(18,      0, UNUSED, UNUSED, 0, 0, 0), /* GPIO18, altA controlled by bit 0 */
+       ALTERNATE_FUNCTIONS(19,      0, UNUSED, UNUSED, 0, 0, 0), /* GPIO19, altA controlled by bit 0 */
+       ALTERNATE_FUNCTIONS(20,      0, UNUSED, UNUSED, 0, 0, 0), /* GPIO20, altA controlled by bit 0 */
+       ALTERNATE_FUNCTIONS(21,      4, UNUSED, UNUSED, 0, 0, 0), /* GPIO21, altA controlled by bit 4 */
+       ALTERNATE_FUNCTIONS(22,      5, UNUSED, UNUSED, 0, 0, 0), /* GPIO22, altA controlled by bit 5 */
+       ALTERNATE_FUNCTIONS(23,      6, UNUSED, UNUSED, 0, 0, 0), /* GPIO23, altA controlled by bit 6 */
+       ALTERNATE_FUNCTIONS(24,      7, UNUSED, UNUSED, 0, 0, 0), /* GPIO24, altA controlled by bit 7 */
+       /* GPIOSEL4 - bit 1 reserved */
+       ALTERNATE_FUNCTIONS(25,      0, UNUSED, UNUSED, 0, 0, 0), /* GPIO25, altA controlled by bit 0 */
+       ALTERNATE_FUNCTIONS(26, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO26 */
+       ALTERNATE_FUNCTIONS(27,      2, UNUSED, UNUSED, 0, 0, 0), /* GPIO27, altA controlled by bit 2 */
+       ALTERNATE_FUNCTIONS(28,      3, UNUSED, UNUSED, 0, 0, 0), /* GPIO28, altA controlled by bit 3 */
+       ALTERNATE_FUNCTIONS(29,      4, UNUSED, UNUSED, 0, 0, 0), /* GPIO29, altA controlled by bit 4 */
+       ALTERNATE_FUNCTIONS(30,      5, UNUSED, UNUSED, 0, 0, 0), /* GPIO30, altA controlled by bit 5 */
+       ALTERNATE_FUNCTIONS(31,      6, UNUSED, UNUSED, 0, 0, 0), /* GPIO31, altA controlled by bit 6 */
+       ALTERNATE_FUNCTIONS(32,      7, UNUSED, UNUSED, 0, 0, 0), /* GPIO32, altA controlled by bit 7 */
+       /* GPIOSEL5 - bit 0, 2-6 are reserved */
+       ALTERNATE_FUNCTIONS(33, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO33 */
+       ALTERNATE_FUNCTIONS(34,      1, UNUSED, UNUSED, 0, 0, 0), /* GPIO34, altA controlled by bit 1 */
+       ALTERNATE_FUNCTIONS(35, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO35 */
+       ALTERNATE_FUNCTIONS(36, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO36 */
+       ALTERNATE_FUNCTIONS(37, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO37 */
+       ALTERNATE_FUNCTIONS(38, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO38 */
+       ALTERNATE_FUNCTIONS(39, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO39 */
+       ALTERNATE_FUNCTIONS(40,      7, UNUSED, UNUSED, 0, 0, 0), /* GPIO40, altA controlled by bit 7 */
+       /* GPIOSEL6 - bit 2-7 are reserved */
+       ALTERNATE_FUNCTIONS(41,      0, UNUSED, UNUSED, 0, 0, 0), /* GPIO41, altA controlled by bit 0 */
+       ALTERNATE_FUNCTIONS(42,      1, UNUSED, UNUSED, 0, 0, 0), /* GPIO42, altA controlled by bit 1 */
+       ALTERNATE_FUNCTIONS(43, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO43 */
+       ALTERNATE_FUNCTIONS(44, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO44 */
+       ALTERNATE_FUNCTIONS(45, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO45 */
+       ALTERNATE_FUNCTIONS(46, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO46 */
+       ALTERNATE_FUNCTIONS(47, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO47 */
+       ALTERNATE_FUNCTIONS(48, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO48 */
+       /*
+        * GPIOSEL7 - bit 0 and 6-7 are reserved
+        * special case with GPIO60, wich is located at offset 5 of gpiosel7
+        * don't know why it has been called GPIO60 in AB9540 datasheet,
+        * GPIO54 would be logical..., so at SOC point of view we consider
+        * GPIO60 = GPIO54
+        */
+       ALTERNATE_FUNCTIONS(49,      0, UNUSED, UNUSED, 0, 0, 0), /* no GPIO49 */
+       ALTERNATE_FUNCTIONS(50,      1,      2, UNUSED, 1, 0, 0), /* GPIO50, altA and altB controlled by bit 1 */
+       ALTERNATE_FUNCTIONS(51,      2, UNUSED, UNUSED, 0, 0, 0), /* GPIO51, altA controlled by bit 2 */
+       ALTERNATE_FUNCTIONS(52,      3, UNUSED, UNUSED, 0, 0, 0), /* GPIO52, altA controlled by bit 3 */
+       ALTERNATE_FUNCTIONS(53,      4, UNUSED, UNUSED, 0, 0, 0), /* GPIO53, altA controlled by bit 4 */
+       ALTERNATE_FUNCTIONS(54,      5, UNUSED, UNUSED, 0, 0, 0), /* GPIO54 = GPIO60, altA controlled by bit 5 */
+};
+
+struct abx500_gpio_irq_cluster ab9540_gpio_irq_cluster[] = {
+       GPIO_IRQ_CLUSTER(10, 13, AB8500_INT_GPIO10R),
+       GPIO_IRQ_CLUSTER(24, 25, AB8500_INT_GPIO24R),
+       GPIO_IRQ_CLUSTER(40, 41, AB8500_INT_GPIO40R),
+       GPIO_IRQ_CLUSTER(50, 54, AB9540_INT_GPIO50R),
+};
+
+static struct abx500_pinctrl_soc_data ab9540_soc = {
+       .gpio_ranges = ab9540_pinranges,
+       .gpio_num_ranges = ARRAY_SIZE(ab9540_pinranges),
+       .pins = ab9540_pins,
+       .npins = ARRAY_SIZE(ab9540_pins),
+       .functions = ab9540_functions,
+       .nfunctions = ARRAY_SIZE(ab9540_functions),
+       .groups = ab9540_groups,
+       .ngroups = ARRAY_SIZE(ab9540_groups),
+       .alternate_functions = ab9540alternate_functions,
+       .gpio_irq_cluster = ab9540_gpio_irq_cluster,
+       .ngpio_irq_cluster = ARRAY_SIZE(ab9540_gpio_irq_cluster),
+       .irq_gpio_rising_offset = AB8500_INT_GPIO6R,
+       .irq_gpio_falling_offset = AB8500_INT_GPIO6F,
+       .irq_gpio_factor = 1,
+};
+
+void
+abx500_pinctrl_ab9540_init(struct abx500_pinctrl_soc_data **soc)
+{
+       *soc = &ab9540_soc;
+}
diff --git a/drivers/pinctrl/pinctrl-abx500.c b/drivers/pinctrl/pinctrl-abx500.c
new file mode 100644 (file)
index 0000000..caecdd3
--- /dev/null
@@ -0,0 +1,1012 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2013
+ *
+ * Author: Patrice Chotard <patrice.chotard@st.com>
+ * License terms: GNU General Public License (GPL) version 2
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/interrupt.h>
+#include <linux/bitops.h>
+#include <linux/mfd/abx500.h>
+#include <linux/mfd/abx500/ab8500.h>
+#include <linux/mfd/abx500/ab8500-gpio.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+
+#include "pinctrl-abx500.h"
+
+/*
+ * The AB9540 and AB8540 GPIO support are extended versions
+ * of the AB8500 GPIO support.
+ * The AB9540 supports an additional (7th) register so that
+ * more GPIO may be configured and used.
+ * The AB8540 supports 4 new gpios (GPIOx_VBAT) that have
+ * internal pull-up and pull-down capabilities.
+ */
+
+/*
+ * GPIO registers offset
+ * Bank: 0x10
+ */
+#define AB8500_GPIO_SEL1_REG   0x00
+#define AB8500_GPIO_SEL2_REG   0x01
+#define AB8500_GPIO_SEL3_REG   0x02
+#define AB8500_GPIO_SEL4_REG   0x03
+#define AB8500_GPIO_SEL5_REG   0x04
+#define AB8500_GPIO_SEL6_REG   0x05
+#define AB9540_GPIO_SEL7_REG   0x06
+
+#define AB8500_GPIO_DIR1_REG   0x10
+#define AB8500_GPIO_DIR2_REG   0x11
+#define AB8500_GPIO_DIR3_REG   0x12
+#define AB8500_GPIO_DIR4_REG   0x13
+#define AB8500_GPIO_DIR5_REG   0x14
+#define AB8500_GPIO_DIR6_REG   0x15
+#define AB9540_GPIO_DIR7_REG   0x16
+
+#define AB8500_GPIO_OUT1_REG   0x20
+#define AB8500_GPIO_OUT2_REG   0x21
+#define AB8500_GPIO_OUT3_REG   0x22
+#define AB8500_GPIO_OUT4_REG   0x23
+#define AB8500_GPIO_OUT5_REG   0x24
+#define AB8500_GPIO_OUT6_REG   0x25
+#define AB9540_GPIO_OUT7_REG   0x26
+
+#define AB8500_GPIO_PUD1_REG   0x30
+#define AB8500_GPIO_PUD2_REG   0x31
+#define AB8500_GPIO_PUD3_REG   0x32
+#define AB8500_GPIO_PUD4_REG   0x33
+#define AB8500_GPIO_PUD5_REG   0x34
+#define AB8500_GPIO_PUD6_REG   0x35
+#define AB9540_GPIO_PUD7_REG   0x36
+
+#define AB8500_GPIO_IN1_REG    0x40
+#define AB8500_GPIO_IN2_REG    0x41
+#define AB8500_GPIO_IN3_REG    0x42
+#define AB8500_GPIO_IN4_REG    0x43
+#define AB8500_GPIO_IN5_REG    0x44
+#define AB8500_GPIO_IN6_REG    0x45
+#define AB9540_GPIO_IN7_REG    0x46
+#define AB8540_GPIO_VINSEL_REG 0x47
+#define AB8540_GPIO_PULL_UPDOWN_REG    0x48
+#define AB8500_GPIO_ALTFUN_REG 0x50
+#define AB8540_GPIO_PULL_UPDOWN_MASK   0x03
+#define AB8540_GPIO_VINSEL_MASK        0x03
+#define AB8540_GPIOX_VBAT_START        51
+#define AB8540_GPIOX_VBAT_END  54
+
+struct abx500_pinctrl {
+       struct device *dev;
+       struct pinctrl_dev *pctldev;
+       struct abx500_pinctrl_soc_data *soc;
+       struct gpio_chip chip;
+       struct ab8500 *parent;
+       struct mutex lock;
+       struct abx500_gpio_irq_cluster *irq_cluster;
+       int irq_cluster_size;
+};
+
+/**
+ * to_abx500_pinctrl() - get the pointer to abx500_pinctrl
+ * @chip:      Member of the structure abx500_pinctrl
+ */
+static inline struct abx500_pinctrl *to_abx500_pinctrl(struct gpio_chip *chip)
+{
+       return container_of(chip, struct abx500_pinctrl, chip);
+}
+
+static int abx500_gpio_get_bit(struct gpio_chip *chip, u8 reg,
+                              unsigned offset, bool *bit)
+{
+       struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
+       u8 pos = offset % 8;
+       u8 val;
+       int ret;
+
+       reg += offset / 8;
+       ret = abx500_get_register_interruptible(pct->dev,
+                                               AB8500_MISC, reg, &val);
+
+       *bit = !!(val & BIT(pos));
+
+       if (ret < 0)
+               dev_err(pct->dev,
+                       "%s read reg =%x, offset=%x failed\n",
+                       __func__, reg, offset);
+
+       return ret;
+}
+
+static int abx500_gpio_set_bits(struct gpio_chip *chip, u8 reg,
+                               unsigned offset, int val)
+{
+       struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
+       u8 pos = offset % 8;
+       int ret;
+
+       reg += offset / 8;
+       ret = abx500_mask_and_set_register_interruptible(pct->dev,
+                               AB8500_MISC, reg, BIT(pos), val << pos);
+       if (ret < 0)
+               dev_err(pct->dev, "%s write failed\n", __func__);
+
+       return ret;
+}
+
+/**
+ * abx500_gpio_get() - Get the particular GPIO value
+ * @chip:      Gpio device
+ * @offset:    GPIO number to read
+ */
+static int abx500_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+       struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
+       bool bit;
+       int ret;
+
+       ret = abx500_gpio_get_bit(chip, AB8500_GPIO_IN1_REG,
+                                 offset, &bit);
+       if (ret < 0) {
+               dev_err(pct->dev, "%s failed\n", __func__);
+               return ret;
+       }
+
+       return bit;
+}
+
+static void abx500_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
+{
+       struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
+       int ret;
+
+       ret = abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
+       if (ret < 0)
+               dev_err(pct->dev, "%s write failed\n", __func__);
+}
+
+static int abx500_config_pull_updown(struct abx500_pinctrl *pct,
+                                    int offset, enum abx500_gpio_pull_updown val)
+{
+       u8 pos;
+       int ret;
+       struct pullud *pullud;
+
+       if (!pct->soc->pullud) {
+               dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature",
+                               __func__);
+               ret = -EPERM;
+               goto out;
+       }
+
+       pullud = pct->soc->pullud;
+
+       if ((offset < pullud->first_pin)
+               || (offset > pullud->last_pin)) {
+               ret = -EINVAL;
+               goto out;
+       }
+
+       pos = offset << 1;
+
+       ret = abx500_mask_and_set_register_interruptible(pct->dev,
+                       AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG,
+                       AB8540_GPIO_PULL_UPDOWN_MASK << pos, val << pos);
+
+out:
+       if (ret < 0)
+               dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
+
+       return ret;
+}
+
+static int abx500_gpio_direction_output(struct gpio_chip *chip,
+                                       unsigned offset,
+                                       int val)
+{
+       struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
+       struct pullud *pullud = pct->soc->pullud;
+       unsigned gpio;
+       int ret;
+
+       /* set direction as output */
+       ret = abx500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 1);
+       if (ret < 0)
+               return ret;
+
+       /* disable pull down */
+       ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG, offset, 1);
+       if (ret < 0)
+               return ret;
+
+       /* if supported, disable both pull down and pull up */
+       gpio = offset + 1;
+       if (pullud && gpio >= pullud->first_pin && gpio <= pullud->last_pin) {
+               ret = abx500_config_pull_updown(pct,
+                               gpio,
+                               ABX500_GPIO_PULL_NONE);
+               if (ret < 0)
+                       return ret;
+       }
+
+       /* set the output as 1 or 0 */
+       return abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
+}
+
+static int abx500_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+       /* set the register as input */
+       return abx500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 0);
+}
+
+static int abx500_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+       struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
+       /* The AB8500 GPIO numbers are off by one */
+       int gpio = offset + 1;
+       int hwirq;
+       int i;
+
+       for (i = 0; i < pct->irq_cluster_size; i++) {
+               struct abx500_gpio_irq_cluster *cluster =
+                       &pct->irq_cluster[i];
+
+               if (gpio >= cluster->start && gpio <= cluster->end) {
+                       /*
+                        * The ABx500 GPIO's associated IRQs are clustered together
+                        * throughout the interrupt numbers at irregular intervals.
+                        * To solve this quandry, we have placed the read-in values
+                        * into the cluster information table.
+                        */
+                       hwirq = gpio - cluster->start + cluster->to_irq;
+                       return irq_create_mapping(pct->parent->domain, hwirq);
+               }
+       }
+
+       return -EINVAL;
+}
+
+static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
+                          unsigned gpio, int alt_setting)
+{
+       struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
+       struct alternate_functions af = pct->soc->alternate_functions[gpio];
+       int ret;
+       int val;
+       unsigned offset;
+
+       const char *modes[] = {
+               [ABX500_DEFAULT]        = "default",
+               [ABX500_ALT_A]          = "altA",
+               [ABX500_ALT_B]          = "altB",
+               [ABX500_ALT_C]          = "altC",
+       };
+
+       /* sanity check */
+       if (((alt_setting == ABX500_ALT_A) && (af.gpiosel_bit == UNUSED)) ||
+           ((alt_setting == ABX500_ALT_B) && (af.alt_bit1 == UNUSED)) ||
+           ((alt_setting == ABX500_ALT_C) && (af.alt_bit2 == UNUSED))) {
+               dev_dbg(pct->dev, "pin %d doesn't support %s mode\n", gpio,
+                               modes[alt_setting]);
+               return -EINVAL;
+       }
+
+       /* on ABx5xx, there is no GPIO0, so adjust the offset */
+       offset = gpio - 1;
+
+       switch (alt_setting) {
+       case ABX500_DEFAULT:
+               /*
+                * for ABx5xx family, default mode is always selected by
+                * writing 0 to GPIOSELx register, except for pins which
+                * support at least ALT_B mode, default mode is selected
+                * by writing 1 to GPIOSELx register
+                */
+               val = 0;
+               if (af.alt_bit1 != UNUSED)
+                       val++;
+
+               ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
+                                          offset, val);
+               break;
+
+       case ABX500_ALT_A:
+               /*
+                * for ABx5xx family, alt_a mode is always selected by
+                * writing 1 to GPIOSELx register, except for pins which
+                * support at least ALT_B mode, alt_a mode is selected
+                * by writing 0 to GPIOSELx register and 0 in ALTFUNC
+                * register
+                */
+               if (af.alt_bit1 != UNUSED) {
+                       ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
+                                       offset, 0);
+                       ret = abx500_gpio_set_bits(chip,
+                                       AB8500_GPIO_ALTFUN_REG,
+                                       af.alt_bit1,
+                                       !!(af.alta_val && BIT(0)));
+                       if (af.alt_bit2 != UNUSED)
+                               ret = abx500_gpio_set_bits(chip,
+                                       AB8500_GPIO_ALTFUN_REG,
+                                       af.alt_bit2,
+                                       !!(af.alta_val && BIT(1)));
+               } else
+                       ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
+                                       offset, 1);
+               break;
+
+       case ABX500_ALT_B:
+               ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
+                               offset, 0);
+               ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
+                               af.alt_bit1, !!(af.altb_val && BIT(0)));
+               if (af.alt_bit2 != UNUSED)
+                       ret = abx500_gpio_set_bits(chip,
+                                       AB8500_GPIO_ALTFUN_REG,
+                                       af.alt_bit2,
+                                       !!(af.altb_val && BIT(1)));
+               break;
+
+       case ABX500_ALT_C:
+               ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
+                               offset, 0);
+               ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
+                               af.alt_bit2, !!(af.altc_val && BIT(0)));
+               ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
+                               af.alt_bit2, !!(af.altc_val && BIT(1)));
+               break;
+
+       default:
+               dev_dbg(pct->dev, "unknow alt_setting %d\n", alt_setting);
+
+               return -EINVAL;
+       }
+
+       return ret;
+}
+
+static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
+                         unsigned gpio)
+{
+       u8 mode;
+       bool bit_mode;
+       bool alt_bit1;
+       bool alt_bit2;
+       struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
+       struct alternate_functions af = pct->soc->alternate_functions[gpio];
+       /* on ABx5xx, there is no GPIO0, so adjust the offset */
+       unsigned offset = gpio - 1;
+
+       /*
+        * if gpiosel_bit is set to unused,
+        * it means no GPIO or special case
+        */
+       if (af.gpiosel_bit == UNUSED)
+               return ABX500_DEFAULT;
+
+       /* read GpioSelx register */
+       abx500_gpio_get_bit(chip, AB8500_GPIO_SEL1_REG + (offset / 8),
+                       af.gpiosel_bit, &bit_mode);
+       mode = bit_mode;
+
+       /* sanity check */
+       if ((af.alt_bit1 < UNUSED) || (af.alt_bit1 > 7) ||
+           (af.alt_bit2 < UNUSED) || (af.alt_bit2 > 7)) {
+               dev_err(pct->dev,
+                       "alt_bitX value not in correct range (-1 to 7)\n");
+               return -EINVAL;
+       }
+
+       /* if alt_bit2 is used, alt_bit1 must be used too */
+       if ((af.alt_bit2 != UNUSED) && (af.alt_bit1 == UNUSED)) {
+               dev_err(pct->dev,
+                       "if alt_bit2 is used, alt_bit1 can't be unused\n");
+               return -EINVAL;
+       }
+
+       /* check if pin use AlternateFunction register */
+       if ((af.alt_bit1 == UNUSED) && (af.alt_bit1 == UNUSED))
+               return mode;
+       /*
+        * if pin GPIOSEL bit is set and pin supports alternate function,
+        * it means DEFAULT mode
+        */
+       if (mode)
+               return ABX500_DEFAULT;
+
+       /*
+        * pin use the AlternatFunction register
+        * read alt_bit1 value
+        */
+       abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG,
+                           af.alt_bit1, &alt_bit1);
+
+       if (af.alt_bit2 != UNUSED)
+               /* read alt_bit2 value */
+               abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, af.alt_bit2,
+                               &alt_bit2);
+       else
+               alt_bit2 = 0;
+
+       mode = (alt_bit2 << 1) + alt_bit1;
+       if (mode == af.alta_val)
+               return ABX500_ALT_A;
+       else if (mode == af.altb_val)
+               return ABX500_ALT_B;
+       else
+               return ABX500_ALT_C;
+}
+
+#ifdef CONFIG_DEBUG_FS
+
+#include <linux/seq_file.h>
+
+static void abx500_gpio_dbg_show_one(struct seq_file *s,
+                                    struct pinctrl_dev *pctldev,
+                                    struct gpio_chip *chip,
+                                    unsigned offset, unsigned gpio)
+{
+       const char *label = gpiochip_is_requested(chip, offset - 1);
+       u8 gpio_offset = offset - 1;
+       int mode = -1;
+       bool is_out;
+       bool pull;
+
+       const char *modes[] = {
+               [ABX500_DEFAULT]        = "default",
+               [ABX500_ALT_A]          = "altA",
+               [ABX500_ALT_B]          = "altB",
+               [ABX500_ALT_C]          = "altC",
+       };
+
+       abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG, gpio_offset, &is_out);
+       abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG, gpio_offset, &pull);
+
+       if (pctldev)
+               mode = abx500_get_mode(pctldev, chip, offset);
+
+       seq_printf(s, " gpio-%-3d (%-20.20s) %-3s %-9s %s",
+                  gpio, label ?: "(none)",
+                  is_out ? "out" : "in ",
+                  is_out ?
+                  (chip->get
+                  ? (chip->get(chip, offset) ? "hi" : "lo")
+                  : "?  ")
+                  : (pull ? "pull up" : "pull down"),
+                  (mode < 0) ? "unknown" : modes[mode]);
+}
+
+static void abx500_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
+{
+       unsigned i;
+       unsigned gpio = chip->base;
+       struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
+       struct pinctrl_dev *pctldev = pct->pctldev;
+
+       for (i = 0; i < chip->ngpio; i++, gpio++) {
+               /* On AB8500, there is no GPIO0, the first is the GPIO 1 */
+               abx500_gpio_dbg_show_one(s, pctldev, chip, i + 1, gpio);
+               seq_printf(s, "\n");
+       }
+}
+
+#else
+static inline void abx500_gpio_dbg_show_one(struct seq_file *s,
+                                           struct pinctrl_dev *pctldev,
+                                           struct gpio_chip *chip,
+                                           unsigned offset, unsigned gpio)
+{
+}
+#define abx500_gpio_dbg_show   NULL
+#endif
+
+int abx500_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+       int gpio = chip->base + offset;
+
+       return pinctrl_request_gpio(gpio);
+}
+
+void abx500_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+       int gpio = chip->base + offset;
+
+       pinctrl_free_gpio(gpio);
+}
+
+static struct gpio_chip abx500gpio_chip = {
+       .label                  = "abx500-gpio",
+       .owner                  = THIS_MODULE,
+       .request                = abx500_gpio_request,
+       .free                   = abx500_gpio_free,
+       .direction_input        = abx500_gpio_direction_input,
+       .get                    = abx500_gpio_get,
+       .direction_output       = abx500_gpio_direction_output,
+       .set                    = abx500_gpio_set,
+       .to_irq                 = abx500_gpio_to_irq,
+       .dbg_show               = abx500_gpio_dbg_show,
+};
+
+static int abx500_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
+{
+       struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
+
+       return pct->soc->nfunctions;
+}
+
+static const char *abx500_pmx_get_func_name(struct pinctrl_dev *pctldev,
+                                        unsigned function)
+{
+       struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
+
+       return pct->soc->functions[function].name;
+}
+
+static int abx500_pmx_get_func_groups(struct pinctrl_dev *pctldev,
+                                     unsigned function,
+                                     const char * const **groups,
+                                     unsigned * const num_groups)
+{
+       struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
+
+       *groups = pct->soc->functions[function].groups;
+       *num_groups = pct->soc->functions[function].ngroups;
+
+       return 0;
+}
+
+static int abx500_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
+                            unsigned group)
+{
+       struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
+       struct gpio_chip *chip = &pct->chip;
+       const struct abx500_pingroup *g;
+       int i;
+       int ret = 0;
+
+       g = &pct->soc->groups[group];
+       if (g->altsetting < 0)
+               return -EINVAL;
+
+       dev_dbg(pct->dev, "enable group %s, %u pins\n", g->name, g->npins);
+
+       for (i = 0; i < g->npins; i++) {
+               dev_dbg(pct->dev, "setting pin %d to altsetting %d\n",
+                       g->pins[i], g->altsetting);
+
+               ret = abx500_set_mode(pctldev, chip, g->pins[i], g->altsetting);
+       }
+
+       return ret;
+}
+
+static void abx500_pmx_disable(struct pinctrl_dev *pctldev,
+                              unsigned function, unsigned group)
+{
+       struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
+       const struct abx500_pingroup *g;
+
+       g = &pct->soc->groups[group];
+       if (g->altsetting < 0)
+               return;
+
+       /* FIXME: poke out the mux, set the pin to some default state? */
+       dev_dbg(pct->dev, "disable group %s, %u pins\n", g->name, g->npins);
+}
+
+int abx500_gpio_request_enable(struct pinctrl_dev *pctldev,
+                              struct pinctrl_gpio_range *range,
+                              unsigned offset)
+{
+       struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
+       const struct abx500_pinrange *p;
+       int ret;
+       int i;
+
+       /*
+        * Different ranges have different ways to enable GPIO function on a
+        * pin, so refer back to our local range type, where we handily define
+        * what altfunc enables GPIO for a certain pin.
+        */
+       for (i = 0; i < pct->soc->gpio_num_ranges; i++) {
+               p = &pct->soc->gpio_ranges[i];
+               if ((offset >= p->offset) &&
+                   (offset < (p->offset + p->npins)))
+                 break;
+       }
+
+       if (i == pct->soc->gpio_num_ranges) {
+               dev_err(pct->dev, "%s failed to locate range\n", __func__);
+               return -ENODEV;
+       }
+
+       dev_dbg(pct->dev, "enable GPIO by altfunc %d at gpio %d\n",
+               p->altfunc, offset);
+
+       ret = abx500_set_mode(pct->pctldev, &pct->chip,
+                             offset, p->altfunc);
+       if (ret < 0) {
+               dev_err(pct->dev, "%s setting altfunc failed\n", __func__);
+               return ret;
+       }
+
+       return ret;
+}
+
+static void abx500_gpio_disable_free(struct pinctrl_dev *pctldev,
+                                    struct pinctrl_gpio_range *range,
+                                    unsigned offset)
+{
+}
+
+static struct pinmux_ops abx500_pinmux_ops = {
+       .get_functions_count = abx500_pmx_get_funcs_cnt,
+       .get_function_name = abx500_pmx_get_func_name,
+       .get_function_groups = abx500_pmx_get_func_groups,
+       .enable = abx500_pmx_enable,
+       .disable = abx500_pmx_disable,
+       .gpio_request_enable = abx500_gpio_request_enable,
+       .gpio_disable_free = abx500_gpio_disable_free,
+};
+
+static int abx500_get_groups_cnt(struct pinctrl_dev *pctldev)
+{
+       struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
+
+       return pct->soc->ngroups;
+}
+
+static const char *abx500_get_group_name(struct pinctrl_dev *pctldev,
+                                        unsigned selector)
+{
+       struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
+
+       return pct->soc->groups[selector].name;
+}
+
+static int abx500_get_group_pins(struct pinctrl_dev *pctldev,
+                                unsigned selector,
+                                const unsigned **pins,
+                                unsigned *num_pins)
+{
+       struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
+
+       *pins = pct->soc->groups[selector].pins;
+       *num_pins = pct->soc->groups[selector].npins;
+
+       return 0;
+}
+
+static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev,
+                               struct seq_file *s, unsigned offset)
+{
+       struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
+       struct gpio_chip *chip = &pct->chip;
+
+       abx500_gpio_dbg_show_one(s, pctldev, chip, offset,
+                                chip->base + offset - 1);
+}
+
+static struct pinctrl_ops abx500_pinctrl_ops = {
+       .get_groups_count = abx500_get_groups_cnt,
+       .get_group_name = abx500_get_group_name,
+       .get_group_pins = abx500_get_group_pins,
+       .pin_dbg_show = abx500_pin_dbg_show,
+};
+
+int abx500_pin_config_get(struct pinctrl_dev *pctldev,
+                         unsigned pin,
+                         unsigned long *config)
+{
+       return -ENOSYS;
+}
+
+int abx500_pin_config_set(struct pinctrl_dev *pctldev,
+                         unsigned pin,
+                         unsigned long config)
+{
+       struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
+       struct pullud *pullud = pct->soc->pullud;
+       struct gpio_chip *chip = &pct->chip;
+       unsigned offset;
+       int ret;
+       enum pin_config_param param = pinconf_to_config_param(config);
+       enum pin_config_param argument = pinconf_to_config_argument(config);
+
+       dev_dbg(chip->dev, "pin %d [%#lx]: %s %s\n",
+               pin, config, (param == PIN_CONFIG_OUTPUT) ? "output " : "input",
+               (param == PIN_CONFIG_OUTPUT) ? (argument ? "high" : "low") :
+               (argument ? "pull up" : "pull down"));
+
+       /* on ABx500, there is no GPIO0, so adjust the offset */
+       offset = pin - 1;
+
+       switch (param) {
+       case PIN_CONFIG_BIAS_PULL_DOWN:
+               /*
+                * if argument = 1 set the pull down
+                * else clear the pull down
+                */
+               ret = abx500_gpio_direction_input(chip, offset);
+               /*
+                * Some chips only support pull down, while some actually
+                * support both pull up and pull down. Such chips have
+                * a "pullud" range specified for the pins that support
+                * both features. If the pin is not within that range, we
+                * fall back to the old bit set that only support pull down.
+                */
+               if (pullud &&
+                   pin >= pullud->first_pin &&
+                   pin <= pullud->last_pin)
+                       ret = abx500_config_pull_updown(pct,
+                               pin,
+                               argument ? ABX500_GPIO_PULL_DOWN : ABX500_GPIO_PULL_NONE);
+               else
+                       /* Chip only supports pull down */
+                       ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG,
+                               offset, argument ? 0 : 1);
+               break;
+
+       case PIN_CONFIG_OUTPUT:
+               ret = abx500_gpio_direction_output(chip, offset, argument);
+
+               break;
+
+       default:
+               dev_err(chip->dev, "illegal configuration requested\n");
+
+               return -EINVAL;
+       }
+
+       return ret;
+}
+
+static struct pinconf_ops abx500_pinconf_ops = {
+       .pin_config_get = abx500_pin_config_get,
+       .pin_config_set = abx500_pin_config_set,
+};
+
+static struct pinctrl_desc abx500_pinctrl_desc = {
+       .name = "pinctrl-abx500",
+       .pctlops = &abx500_pinctrl_ops,
+       .pmxops = &abx500_pinmux_ops,
+       .confops = &abx500_pinconf_ops,
+       .owner = THIS_MODULE,
+};
+
+static int abx500_get_gpio_num(struct abx500_pinctrl_soc_data *soc)
+{
+       unsigned int lowest = 0;
+       unsigned int highest = 0;
+       unsigned int npins = 0;
+       int i;
+
+       /*
+        * Compute number of GPIOs from the last SoC gpio range descriptors
+        * These ranges may include "holes" but the GPIO number space shall
+        * still be homogeneous, so we need to detect and account for any
+        * such holes so that these are included in the number of GPIO pins.
+        */
+       for (i = 0; i < soc->gpio_num_ranges; i++) {
+               unsigned gstart;
+               unsigned gend;
+               const struct abx500_pinrange *p;
+
+               p = &soc->gpio_ranges[i];
+               gstart = p->offset;
+               gend = p->offset + p->npins - 1;
+
+               if (i == 0) {
+                       /* First iteration, set start values */
+                       lowest = gstart;
+                       highest = gend;
+               } else {
+                       if (gstart < lowest)
+                               lowest = gstart;
+                       if (gend > highest)
+                               highest = gend;
+               }
+       }
+       /* this gives the absolute number of pins */
+       npins = highest - lowest + 1;
+       return npins;
+}
+
+static const struct of_device_id abx500_gpio_match[] = {
+       { .compatible = "stericsson,ab8500-gpio", .data = (void *)PINCTRL_AB8500, },
+       { .compatible = "stericsson,ab8505-gpio", .data = (void *)PINCTRL_AB8505, },
+       { .compatible = "stericsson,ab8540-gpio", .data = (void *)PINCTRL_AB8540, },
+       { .compatible = "stericsson,ab9540-gpio", .data = (void *)PINCTRL_AB9540, },
+};
+
+static int abx500_gpio_probe(struct platform_device *pdev)
+{
+       struct ab8500_platform_data *abx500_pdata =
+                               dev_get_platdata(pdev->dev.parent);
+       struct abx500_gpio_platform_data *pdata = NULL;
+       struct device_node *np = pdev->dev.of_node;
+       struct abx500_pinctrl *pct;
+       const struct platform_device_id *platid = platform_get_device_id(pdev);
+       unsigned int id = -1;
+       int ret, err;
+       int i;
+
+       if (abx500_pdata)
+               pdata = abx500_pdata->gpio;
+       if (!pdata) {
+               if (np) {
+                       const struct of_device_id *match;
+
+                       match = of_match_device(abx500_gpio_match, &pdev->dev);
+                       if (!match)
+                               return -ENODEV;
+                       id = (unsigned long)match->data;
+               } else {
+                       dev_err(&pdev->dev, "gpio dt and platform data missing\n");
+                       return -ENODEV;
+               }
+       }
+
+       if (platid)
+               id = platid->driver_data;
+
+       pct = devm_kzalloc(&pdev->dev, sizeof(struct abx500_pinctrl),
+                                  GFP_KERNEL);
+       if (pct == NULL) {
+               dev_err(&pdev->dev,
+                       "failed to allocate memory for pct\n");
+               return -ENOMEM;
+       }
+
+       pct->dev = &pdev->dev;
+       pct->parent = dev_get_drvdata(pdev->dev.parent);
+       pct->chip = abx500gpio_chip;
+       pct->chip.dev = &pdev->dev;
+       pct->chip.base = pdata->gpio_base;
+       pct->chip.base = (np) ? -1 : pdata->gpio_base;
+
+       /* initialize the lock */
+       mutex_init(&pct->lock);
+
+       /* Poke in other ASIC variants here */
+       switch (id) {
+       case PINCTRL_AB8500:
+               abx500_pinctrl_ab8500_init(&pct->soc);
+               break;
+       case PINCTRL_AB8540:
+               abx500_pinctrl_ab8540_init(&pct->soc);
+               break;
+       case PINCTRL_AB9540:
+               abx500_pinctrl_ab9540_init(&pct->soc);
+               break;
+       case PINCTRL_AB8505:
+               abx500_pinctrl_ab8505_init(&pct->soc);
+               break;
+       default:
+               dev_err(&pdev->dev, "Unsupported pinctrl sub driver (%d)\n",
+                               (int) platid->driver_data);
+               mutex_destroy(&pct->lock);
+               return -EINVAL;
+       }
+
+       if (!pct->soc) {
+               dev_err(&pdev->dev, "Invalid SOC data\n");
+               mutex_destroy(&pct->lock);
+               return -EINVAL;
+       }
+
+       pct->chip.ngpio = abx500_get_gpio_num(pct->soc);
+       pct->irq_cluster = pct->soc->gpio_irq_cluster;
+       pct->irq_cluster_size = pct->soc->ngpio_irq_cluster;
+
+       ret = gpiochip_add(&pct->chip);
+       if (ret) {
+               dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
+               mutex_destroy(&pct->lock);
+               return ret;
+       }
+       dev_info(&pdev->dev, "added gpiochip\n");
+
+       abx500_pinctrl_desc.pins = pct->soc->pins;
+       abx500_pinctrl_desc.npins = pct->soc->npins;
+       pct->pctldev = pinctrl_register(&abx500_pinctrl_desc, &pdev->dev, pct);
+       if (!pct->pctldev) {
+               dev_err(&pdev->dev,
+                       "could not register abx500 pinctrl driver\n");
+               ret = -EINVAL;
+               goto out_rem_chip;
+       }
+       dev_info(&pdev->dev, "registered pin controller\n");
+
+       /* We will handle a range of GPIO pins */
+       for (i = 0; i < pct->soc->gpio_num_ranges; i++) {
+               const struct abx500_pinrange *p = &pct->soc->gpio_ranges[i];
+
+               ret = gpiochip_add_pin_range(&pct->chip,
+                                       dev_name(&pdev->dev),
+                                       p->offset - 1, p->offset, p->npins);
+               if (ret < 0)
+                       goto out_rem_chip;
+       }
+
+       platform_set_drvdata(pdev, pct);
+       dev_info(&pdev->dev, "initialized abx500 pinctrl driver\n");
+
+       return 0;
+
+out_rem_chip:
+       err = gpiochip_remove(&pct->chip);
+       if (err)
+               dev_info(&pdev->dev, "failed to remove gpiochip\n");
+
+       mutex_destroy(&pct->lock);
+       return ret;
+}
+
+/**
+ * abx500_gpio_remove() - remove Ab8500-gpio driver
+ * @pdev:      Platform device registered
+ */
+static int abx500_gpio_remove(struct platform_device *pdev)
+{
+       struct abx500_pinctrl *pct = platform_get_drvdata(pdev);
+       int ret;
+
+       ret = gpiochip_remove(&pct->chip);
+       if (ret < 0) {
+               dev_err(pct->dev, "unable to remove gpiochip: %d\n",
+                       ret);
+               return ret;
+       }
+
+       mutex_destroy(&pct->lock);
+
+       return 0;
+}
+
+static const struct platform_device_id abx500_pinctrl_id[] = {
+       { "pinctrl-ab8500", PINCTRL_AB8500 },
+       { "pinctrl-ab8540", PINCTRL_AB8540 },
+       { "pinctrl-ab9540", PINCTRL_AB9540 },
+       { "pinctrl-ab8505", PINCTRL_AB8505 },
+       { },
+};
+
+static struct platform_driver abx500_gpio_driver = {
+       .driver = {
+               .name = "abx500-gpio",
+               .owner = THIS_MODULE,
+               .of_match_table = abx500_gpio_match,
+       },
+       .probe = abx500_gpio_probe,
+       .remove = abx500_gpio_remove,
+       .id_table = abx500_pinctrl_id,
+};
+
+static int __init abx500_gpio_init(void)
+{
+       return platform_driver_register(&abx500_gpio_driver);
+}
+core_initcall(abx500_gpio_init);
+
+MODULE_AUTHOR("Patrice Chotard <patrice.chotard@st.com>");
+MODULE_DESCRIPTION("Driver allows to use AxB5xx unused pins to be used as GPIO");
+MODULE_ALIAS("platform:abx500-gpio");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-abx500.h b/drivers/pinctrl/pinctrl-abx500.h
new file mode 100644 (file)
index 0000000..eeca8f9
--- /dev/null
@@ -0,0 +1,234 @@
+#ifndef PINCTRL_PINCTRL_ABx5O0_H
+#define PINCTRL_PINCTRL_ABx500_H
+
+/* Package definitions */
+#define PINCTRL_AB8500 0
+#define PINCTRL_AB8540 1
+#define PINCTRL_AB9540 2
+#define PINCTRL_AB8505 3
+
+/* pins alternate function */
+enum abx500_pin_func {
+       ABX500_DEFAULT,
+       ABX500_ALT_A,
+       ABX500_ALT_B,
+       ABX500_ALT_C,
+};
+
+/**
+ * struct abx500_function - ABx500 pinctrl mux function
+ * @name: The name of the function, exported to pinctrl core.
+ * @groups: An array of pin groups that may select this function.
+ * @ngroups: The number of entries in @groups.
+ */
+struct abx500_function {
+       const char *name;
+       const char * const *groups;
+       unsigned ngroups;
+};
+
+/**
+ * struct abx500_pingroup - describes a ABx500 pin group
+ * @name: the name of this specific pin group
+ * @pins: an array of discrete physical pins used in this group, taken
+ *     from the driver-local pin enumeration space
+ * @num_pins: the number of pins in this group array, i.e. the number of
+ *     elements in .pins so we can iterate over that array
+ * @altsetting: the altsetting to apply to all pins in this group to
+ *     configure them to be used by a function
+ */
+struct abx500_pingroup {
+       const char *name;
+       const unsigned int *pins;
+       const unsigned npins;
+       int altsetting;
+};
+
+#define ALTERNATE_FUNCTIONS(pin, sel_bit, alt1, alt2, alta, altb, altc)        \
+{                                                                      \
+       .pin_number = pin,                                              \
+       .gpiosel_bit = sel_bit,                                         \
+       .alt_bit1 = alt1,                                               \
+       .alt_bit2 = alt2,                                               \
+       .alta_val = alta,                                               \
+       .altb_val = altb,                                               \
+       .altc_val = altc,                                               \
+}
+
+#define UNUSED -1
+/**
+ * struct alternate_functions
+ * @pin_number:                The pin number
+ * @gpiosel_bit:       Control bit in GPIOSEL register,
+ * @alt_bit1:          First AlternateFunction bit used to select the
+ *                     alternate function
+ * @alt_bit2:          Second AlternateFunction bit used to select the
+ *                     alternate function
+ *
+ *                     these 3 following fields are necessary due to none
+ *                     coherency on how to select the altA, altB and altC
+ *                     function between the ABx500 SOC family when using
+ *                     alternatfunc register.
+ * @alta_val:          value to write in alternatfunc to select altA function
+ * @altb_val:          value to write in alternatfunc to select altB function
+ * @altc_val:          value to write in alternatfunc to select altC function
+ */
+struct alternate_functions {
+       unsigned pin_number;
+       s8 gpiosel_bit;
+       s8 alt_bit1;
+       s8 alt_bit2;
+       u8 alta_val;
+       u8 altb_val;
+       u8 altc_val;
+};
+
+/**
+ * struct pullud - specific pull up/down feature
+ * @first_pin:         The pin number of the first pins which support
+ *                     specific pull up/down
+ * @last_pin:          The pin number of the last pins
+ */
+struct pullud {
+       unsigned first_pin;
+       unsigned last_pin;
+};
+
+#define GPIO_IRQ_CLUSTER(a, b, c)      \
+{                                      \
+       .start = a,                     \
+       .end = b,                       \
+       .to_irq = c,                    \
+}
+
+/**
+ * struct abx500_gpio_irq_cluster - indicates GPIOs which are interrupt
+ *                     capable
+ * @start:             The pin number of the first pin interrupt capable
+ * @end:               The pin number of the last pin interrupt capable
+ * @to_irq:            The ABx500 GPIO's associated IRQs are clustered
+ *                      together throughout the interrupt numbers at irregular
+ *                      intervals. To solve this quandary, we will place the
+ *                      read-in values into the cluster information table
+ */
+
+struct abx500_gpio_irq_cluster {
+       int start;
+       int end;
+       int to_irq;
+};
+
+/**
+ * struct abx500_pinrange - map pin numbers to GPIO offsets
+ * @offset:            offset into the GPIO local numberspace, incidentally
+ *                     identical to the offset into the local pin numberspace
+ * @npins:             number of pins to map from both offsets
+ * @altfunc:           altfunc setting to be used to enable GPIO on a pin in
+ *                     this range (may vary)
+ */
+struct abx500_pinrange {
+       unsigned int offset;
+       unsigned int npins;
+       int altfunc;
+};
+
+#define ABX500_PINRANGE(a, b, c) { .offset = a, .npins = b, .altfunc = c }
+
+/**
+ * struct abx500_pinctrl_soc_data - ABx500 pin controller per-SoC configuration
+ * @gpio_ranges:       An array of GPIO ranges for this SoC
+ * @gpio_num_ranges:   The number of GPIO ranges for this SoC
+ * @pins:              An array describing all pins the pin controller affects.
+ *                     All pins which are also GPIOs must be listed first within the
+ *                     array, and be numbered identically to the GPIO controller's
+ *                     numbering.
+ * @npins:             The number of entries in @pins.
+ * @functions:         The functions supported on this SoC.
+ * @nfunction:         The number of entries in @functions.
+ * @groups:            An array describing all pin groups the pin SoC supports.
+ * @ngroups:           The number of entries in @groups.
+ * @alternate_functions: array describing pins which supports alternate and
+ *                     how to set it.
+ * @pullud:            array describing pins which supports pull up/down
+ *                     specific registers.
+ * @gpio_irq_cluster:  An array of GPIO interrupt capable for this SoC
+ * @ngpio_irq_cluster: The number of GPIO inetrrupt capable for this SoC
+ * @irq_gpio_rising_offset: Interrupt offset used as base to compute specific
+ *                     setting strategy of the rising interrupt line
+ * @irq_gpio_falling_offset: Interrupt offset used as base to compute specific
+ *                     setting strategy of the falling interrupt line
+ * @irq_gpio_factor:   Factor used to compute specific setting strategy of
+ *                     the interrupt line
+ */
+
+struct abx500_pinctrl_soc_data {
+       const struct abx500_pinrange *gpio_ranges;
+       unsigned gpio_num_ranges;
+       const struct pinctrl_pin_desc *pins;
+       unsigned npins;
+       const struct abx500_function *functions;
+       unsigned nfunctions;
+       const struct abx500_pingroup *groups;
+       unsigned ngroups;
+       struct alternate_functions *alternate_functions;
+       struct pullud *pullud;
+       struct abx500_gpio_irq_cluster *gpio_irq_cluster;
+       unsigned ngpio_irq_cluster;
+       int irq_gpio_rising_offset;
+       int irq_gpio_falling_offset;
+       int irq_gpio_factor;
+};
+
+#ifdef CONFIG_PINCTRL_AB8500
+
+void abx500_pinctrl_ab8500_init(struct abx500_pinctrl_soc_data **soc);
+
+#else
+
+static inline void
+abx500_pinctrl_ab8500_init(struct abx500_pinctrl_soc_data **soc)
+{
+}
+
+#endif
+
+#ifdef CONFIG_PINCTRL_AB8540
+
+void abx500_pinctrl_ab8540_init(struct abx500_pinctrl_soc_data **soc);
+
+#else
+
+static inline void
+abx500_pinctrl_ab8540_init(struct abx500_pinctrl_soc_data **soc)
+{
+}
+
+#endif
+
+#ifdef CONFIG_PINCTRL_AB9540
+
+void abx500_pinctrl_ab9540_init(struct abx500_pinctrl_soc_data **soc);
+
+#else
+
+static inline void
+abx500_pinctrl_ab9540_init(struct abx500_pinctrl_soc_data **soc)
+{
+}
+
+#endif
+
+#ifdef CONFIG_PINCTRL_AB8505
+
+void abx500_pinctrl_ab8505_init(struct abx500_pinctrl_soc_data **soc);
+
+#else
+
+static inline void
+abx500_pinctrl_ab8505_init(struct abx500_pinctrl_soc_data **soc)
+{
+}
+
+#endif
+
+#endif /* PINCTRL_PINCTRL_ABx500_H */
index 8ed20e84cb0274f486264c8d00e1d5ff5c86edee..4a0d54a08890c866986cc72505e96202b526ab82 100644 (file)
@@ -170,7 +170,7 @@ static const unsigned pins_ntr[] = {GPIO4};
 static const unsigned pins_ntr8k[] = {GPIO5};
 static const unsigned pins_hrst[] = {GPIO6};
 static const unsigned pins_mdio[] = {GPIO7, GPIO8};
-static const unsigned pins_bled[] = {GPIO7, GPIO10, GPIO11,
+static const unsigned pins_bled[] = {GPIO9, GPIO10, GPIO11,
                                        GPIO12, GPIO13, GPIO14};
 static const unsigned pins_asc0[] = {GPIO32, GPIO33};
 static const unsigned pins_spi[] = {GPIO34, GPIO35, GPIO36};
@@ -315,6 +315,37 @@ static int falcon_pinconf_set(struct pinctrl_dev *pctrldev,
 static void falcon_pinconf_dbg_show(struct pinctrl_dev *pctrldev,
                        struct seq_file *s, unsigned offset)
 {
+       unsigned long config;
+       struct pin_desc *desc;
+
+       struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
+       int port = PORT(offset);
+
+       seq_printf(s, " (port %d) mux %d -- ", port,
+               pad_r32(info->membase[port], LTQ_PADC_MUX(PORT_PIN(offset))));
+
+       config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_PULL, 0);
+       if (!falcon_pinconf_get(pctrldev, offset, &config))
+               seq_printf(s, "pull %d ",
+                       (int)LTQ_PINCONF_UNPACK_ARG(config));
+
+       config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_DRIVE_CURRENT, 0);
+       if (!falcon_pinconf_get(pctrldev, offset, &config))
+               seq_printf(s, "drive-current %d ",
+                       (int)LTQ_PINCONF_UNPACK_ARG(config));
+
+       config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_SLEW_RATE, 0);
+       if (!falcon_pinconf_get(pctrldev, offset, &config))
+               seq_printf(s, "slew-rate %d ",
+                       (int)LTQ_PINCONF_UNPACK_ARG(config));
+
+       desc = pin_desc_get(pctrldev, offset);
+       if (desc) {
+               if (desc->gpio_owner)
+                       seq_printf(s, " owner: %s", desc->gpio_owner);
+       } else {
+               seq_printf(s, " not registered");
+       }
 }
 
 static void falcon_pinconf_group_dbg_show(struct pinctrl_dev *pctrldev,
@@ -360,6 +391,8 @@ static const struct ltq_cfg_param falcon_cfg_params[] = {
 static struct ltq_pinmux_info falcon_info = {
        .desc           = &falcon_pctrl_desc,
        .apply_mux      = falcon_mux_apply,
+       .params         = falcon_cfg_params,
+       .num_params     = ARRAY_SIZE(falcon_cfg_params),
 };
 
 
@@ -398,6 +431,9 @@ static int pinctrl_falcon_probe(struct platform_device *pdev)
                u32 avail;
                int pins;
 
+               if (!of_device_is_available(np))
+                       continue;
+
                if (!ppdev) {
                        dev_err(&pdev->dev, "failed to find pad pdev\n");
                        continue;
index 15f501d89026f2360cf59639c464e5200f5e03c8..a70384611351411a8396aa23288649aa044c283b 100644 (file)
@@ -64,11 +64,13 @@ static void ltq_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
        seq_printf(s, " %s", dev_name(pctldev->dev));
 }
 
-static int ltq_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
+static void ltq_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
                                struct device_node *np,
                                struct pinctrl_map **map)
 {
        struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
+       struct property *pins = of_find_property(np, "lantiq,pins", NULL);
+       struct property *groups = of_find_property(np, "lantiq,groups", NULL);
        unsigned long configs[3];
        unsigned num_configs = 0;
        struct property *prop;
@@ -76,8 +78,20 @@ static int ltq_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
        const char *function;
        int ret, i;
 
+       if (!pins && !groups) {
+               dev_err(pctldev->dev, "%s defines neither pins nor groups\n",
+                       np->name);
+               return;
+       }
+
+       if (pins && groups) {
+               dev_err(pctldev->dev, "%s defines both pins and groups\n",
+                       np->name);
+               return;
+       }
+
        ret = of_property_read_string(np, "lantiq,function", &function);
-       if (!ret) {
+       if (groups && !ret) {
                of_property_for_each_string(np, "lantiq,groups", prop, group) {
                        (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
                        (*map)->name = function;
@@ -85,11 +99,6 @@ static int ltq_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
                        (*map)->data.mux.function = function;
                        (*map)++;
                }
-               if (of_find_property(np, "lantiq,pins", NULL))
-                       dev_err(pctldev->dev,
-                               "%s mixes pins and groups settings\n",
-                               np->name);
-               return 0;
        }
 
        for (i = 0; i < info->num_params; i++) {
@@ -103,7 +112,7 @@ static int ltq_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
        }
 
        if (!num_configs)
-               return -EINVAL;
+               return;
 
        of_property_for_each_string(np, "lantiq,pins", prop, pin) {
                (*map)->data.configs.configs = kmemdup(configs,
@@ -115,7 +124,16 @@ static int ltq_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
                (*map)->data.configs.num_configs = num_configs;
                (*map)++;
        }
-       return 0;
+       of_property_for_each_string(np, "lantiq,groups", prop, group) {
+               (*map)->data.configs.configs = kmemdup(configs,
+                                       num_configs * sizeof(unsigned long),
+                                       GFP_KERNEL);
+               (*map)->type = PIN_MAP_TYPE_CONFIGS_GROUP;
+               (*map)->name = group;
+               (*map)->data.configs.group_or_pin = group;
+               (*map)->data.configs.num_configs = num_configs;
+               (*map)++;
+       }
 }
 
 static int ltq_pinctrl_dt_subnode_size(struct device_node *np)
@@ -135,23 +153,19 @@ static int ltq_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
 {
        struct pinctrl_map *tmp;
        struct device_node *np;
-       int ret;
+       int max_maps = 0;
 
-       *num_maps = 0;
        for_each_child_of_node(np_config, np)
-               *num_maps += ltq_pinctrl_dt_subnode_size(np);
-       *map = kzalloc(*num_maps * sizeof(struct pinctrl_map), GFP_KERNEL);
+               max_maps += ltq_pinctrl_dt_subnode_size(np);
+       *map = kzalloc(max_maps * sizeof(struct pinctrl_map) * 2, GFP_KERNEL);
        if (!*map)
                return -ENOMEM;
        tmp = *map;
 
-       for_each_child_of_node(np_config, np) {
-               ret = ltq_pinctrl_dt_subnode_to_map(pctldev, np, &tmp);
-               if (ret < 0) {
-                       ltq_pinctrl_dt_free_map(pctldev, *map, *num_maps);
-                       return ret;
-               }
-       }
+       for_each_child_of_node(np_config, np)
+               ltq_pinctrl_dt_subnode_to_map(pctldev, np, &tmp);
+       *num_maps = ((int)(tmp - *map));
+
        return 0;
 }
 
@@ -280,7 +294,7 @@ static int ltq_pmx_gpio_request_enable(struct pinctrl_dev *pctrldev,
                                unsigned pin)
 {
        struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
-       int mfp = match_mfp(info, pin + (range->id * 32));
+       int mfp = match_mfp(info, pin);
        int pin_func;
 
        if (mfp < 0) {
index 4419d32a0ade00acb70d2ad56da68ea108d969ab..6d07f0238532050c1c7ecd54cefd65bb8439ddaf 100644 (file)
@@ -34,6 +34,7 @@ enum ltq_pinconf_param {
        LTQ_PINCONF_PARAM_OPEN_DRAIN,
        LTQ_PINCONF_PARAM_DRIVE_CURRENT,
        LTQ_PINCONF_PARAM_SLEW_RATE,
+       LTQ_PINCONF_PARAM_OUTPUT,
 };
 
 struct ltq_cfg_param {
index 5767b18ebdff6d1639bd37c6007f9c93553a3f58..de9e8519b803570e4188bb58d5b0c77cf6ab004f 100644 (file)
@@ -25,6 +25,8 @@
 #include <linux/irqdomain.h>
 #include <linux/slab.h>
 #include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/pinmux.h>
 #include <linux/pinctrl/pinconf.h>
@@ -32,8 +34,8 @@
 #include <linux/pinctrl/consumer.h>
 #include <linux/platform_data/pinctrl-nomadik.h>
 #include <asm/mach/irq.h>
-#include <mach/irqs.h>
 #include "pinctrl-nomadik.h"
+#include "core.h"
 
 /*
  * The GPIO module in the Nomadik family of Systems-on-Chip is an
@@ -216,7 +218,7 @@ nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
        u32 falling = nmk_chip->fimsc & BIT(offset);
        u32 rising = nmk_chip->rimsc & BIT(offset);
        int gpio = nmk_chip->chip.base + offset;
-       int irq = NOMADIK_GPIO_TO_IRQ(gpio);
+       int irq = irq_find_mapping(nmk_chip->domain, offset);
        struct irq_data *d = irq_get_irq_data(irq);
 
        if (!rising && !falling)
@@ -1341,8 +1343,7 @@ static int nmk_gpio_probe(struct platform_device *dev)
 
                if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
                        dev_err(&dev->dev, "gpio-bank property not found\n");
-                       ret = -EINVAL;
-                       goto out;
+                       return -EINVAL;
                }
 
                pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP;
@@ -1350,41 +1351,29 @@ static int nmk_gpio_probe(struct platform_device *dev)
        }
 
        res = platform_get_resource(dev, IORESOURCE_MEM, 0);
-       if (!res) {
-               ret = -ENOENT;
-               goto out;
-       }
+       if (!res)
+               return -ENOENT;
 
        irq = platform_get_irq(dev, 0);
-       if (irq < 0) {
-               ret = irq;
-               goto out;
-       }
+       if (irq < 0)
+               return irq;
 
        secondary_irq = platform_get_irq(dev, 1);
-       if (secondary_irq >= 0 && !pdata->get_secondary_status) {
-               ret = -EINVAL;
-               goto out;
-       }
+       if (secondary_irq >= 0 && !pdata->get_secondary_status)
+               return -EINVAL;
 
        base = devm_request_and_ioremap(&dev->dev, res);
-       if (!base) {
-               ret = -ENOMEM;
-               goto out;
-       }
+       if (!base)
+               return -ENOMEM;
 
        clk = devm_clk_get(&dev->dev, NULL);
-       if (IS_ERR(clk)) {
-               ret = PTR_ERR(clk);
-               goto out;
-       }
+       if (IS_ERR(clk))
+               return PTR_ERR(clk);
        clk_prepare(clk);
 
        nmk_chip = devm_kzalloc(&dev->dev, sizeof(*nmk_chip), GFP_KERNEL);
-       if (!nmk_chip) {
-               ret = -ENOMEM;
-               goto out;
-       }
+       if (!nmk_chip)
+               return -ENOMEM;
 
        /*
         * The virt address in nmk_chip->addr is in the nomadik register space,
@@ -1418,7 +1407,7 @@ static int nmk_gpio_probe(struct platform_device *dev)
 
        ret = gpiochip_add(&nmk_chip->chip);
        if (ret)
-               goto out;
+               return ret;
 
        BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
 
@@ -1427,14 +1416,15 @@ static int nmk_gpio_probe(struct platform_device *dev)
        platform_set_drvdata(dev, nmk_chip);
 
        if (!np)
-               irq_start = NOMADIK_GPIO_TO_IRQ(pdata->first_gpio);
+               irq_start = pdata->first_irq;
        nmk_chip->domain = irq_domain_add_simple(np,
                                NMK_GPIO_PER_CHIP, irq_start,
                                &nmk_gpio_irq_simple_ops, nmk_chip);
        if (!nmk_chip->domain) {
                dev_err(&dev->dev, "failed to create irqdomain\n");
-               ret = -ENOSYS;
-               goto out;
+               /* Just do this, no matter if it fails */
+               ret = gpiochip_remove(&nmk_chip->chip);
+               return -ENOSYS;
        }
 
        nmk_gpio_init_irq(nmk_chip);
@@ -1442,12 +1432,6 @@ static int nmk_gpio_probe(struct platform_device *dev)
        dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);
 
        return 0;
-
-out:
-       dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret,
-                 pdata->first_gpio, pdata->first_gpio+31);
-
-       return ret;
 }
 
 static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
@@ -1508,11 +1492,285 @@ static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
        nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset);
 }
 
+static void nmk_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
+               struct pinctrl_map *map, unsigned num_maps)
+{
+       int i;
+
+       for (i = 0; i < num_maps; i++)
+               if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
+                       kfree(map[i].data.configs.configs);
+       kfree(map);
+}
+
+static int nmk_dt_reserve_map(struct pinctrl_map **map, unsigned *reserved_maps,
+               unsigned *num_maps, unsigned reserve)
+{
+       unsigned old_num = *reserved_maps;
+       unsigned new_num = *num_maps + reserve;
+       struct pinctrl_map *new_map;
+
+       if (old_num >= new_num)
+               return 0;
+
+       new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
+       if (!new_map)
+               return -ENOMEM;
+
+       memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
+
+       *map = new_map;
+       *reserved_maps = new_num;
+
+       return 0;
+}
+
+static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
+               unsigned *num_maps, const char *group,
+               const char *function)
+{
+       if (*num_maps == *reserved_maps)
+               return -ENOSPC;
+
+       (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
+       (*map)[*num_maps].data.mux.group = group;
+       (*map)[*num_maps].data.mux.function = function;
+       (*num_maps)++;
+
+       return 0;
+}
+
+static int nmk_dt_add_map_configs(struct pinctrl_map **map,
+               unsigned *reserved_maps,
+               unsigned *num_maps, const char *group,
+               unsigned long *configs, unsigned num_configs)
+{
+       unsigned long *dup_configs;
+
+       if (*num_maps == *reserved_maps)
+               return -ENOSPC;
+
+       dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
+                             GFP_KERNEL);
+       if (!dup_configs)
+               return -ENOMEM;
+
+       (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN;
+
+       (*map)[*num_maps].data.configs.group_or_pin = group;
+       (*map)[*num_maps].data.configs.configs = dup_configs;
+       (*map)[*num_maps].data.configs.num_configs = num_configs;
+       (*num_maps)++;
+
+       return 0;
+}
+
+#define NMK_CONFIG_PIN(x,y) { .property = x, .config = y, }
+#define NMK_CONFIG_PIN_ARRAY(x,y) { .property = x, .choice = y, \
+       .size = ARRAY_SIZE(y), }
+
+static const unsigned long nmk_pin_input_modes[] = {
+       PIN_INPUT_NOPULL,
+       PIN_INPUT_PULLUP,
+       PIN_INPUT_PULLDOWN,
+};
+
+static const unsigned long nmk_pin_output_modes[] = {
+       PIN_OUTPUT_LOW,
+       PIN_OUTPUT_HIGH,
+       PIN_DIR_OUTPUT,
+};
+
+static const unsigned long nmk_pin_sleep_modes[] = {
+       PIN_SLEEPMODE_DISABLED,
+       PIN_SLEEPMODE_ENABLED,
+};
+
+static const unsigned long nmk_pin_sleep_input_modes[] = {
+       PIN_SLPM_INPUT_NOPULL,
+       PIN_SLPM_INPUT_PULLUP,
+       PIN_SLPM_INPUT_PULLDOWN,
+       PIN_SLPM_DIR_INPUT,
+};
+
+static const unsigned long nmk_pin_sleep_output_modes[] = {
+       PIN_SLPM_OUTPUT_LOW,
+       PIN_SLPM_OUTPUT_HIGH,
+       PIN_SLPM_DIR_OUTPUT,
+};
+
+static const unsigned long nmk_pin_sleep_wakeup_modes[] = {
+       PIN_SLPM_WAKEUP_DISABLE,
+       PIN_SLPM_WAKEUP_ENABLE,
+};
+
+static const unsigned long nmk_pin_gpio_modes[] = {
+       PIN_GPIOMODE_DISABLED,
+       PIN_GPIOMODE_ENABLED,
+};
+
+static const unsigned long nmk_pin_sleep_pdis_modes[] = {
+       PIN_SLPM_PDIS_DISABLED,
+       PIN_SLPM_PDIS_ENABLED,
+};
+
+struct nmk_cfg_param {
+       const char *property;
+       unsigned long config;
+       const unsigned long *choice;
+       int size;
+};
+
+static const struct nmk_cfg_param nmk_cfg_params[] = {
+       NMK_CONFIG_PIN_ARRAY("ste,input",               nmk_pin_input_modes),
+       NMK_CONFIG_PIN_ARRAY("ste,output",              nmk_pin_output_modes),
+       NMK_CONFIG_PIN_ARRAY("ste,sleep",               nmk_pin_sleep_modes),
+       NMK_CONFIG_PIN_ARRAY("ste,sleep-input",         nmk_pin_sleep_input_modes),
+       NMK_CONFIG_PIN_ARRAY("ste,sleep-output",        nmk_pin_sleep_output_modes),
+       NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup",        nmk_pin_sleep_wakeup_modes),
+       NMK_CONFIG_PIN_ARRAY("ste,gpio",                nmk_pin_gpio_modes),
+       NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable",  nmk_pin_sleep_pdis_modes),
+};
+
+static int nmk_dt_pin_config(int index, int val, unsigned long *config)
+{
+       int ret = 0;
+
+       if (nmk_cfg_params[index].choice == NULL)
+               *config = nmk_cfg_params[index].config;
+       else {
+               /* test if out of range */
+               if  (val < nmk_cfg_params[index].size) {
+                       *config = nmk_cfg_params[index].config |
+                               nmk_cfg_params[index].choice[val];
+               }
+       }
+       return ret;
+}
+
+static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name)
+{
+       int i, pin_number;
+       struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
+
+       if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1)
+               for (i = 0; i < npct->soc->npins; i++)
+                       if (npct->soc->pins[i].number == pin_number)
+                               return npct->soc->pins[i].name;
+       return NULL;
+}
+
+static bool nmk_pinctrl_dt_get_config(struct device_node *np,
+               unsigned long *configs)
+{
+       bool has_config = 0;
+       unsigned long cfg = 0;
+       int i, val, ret;
+
+       for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) {
+               ret = of_property_read_u32(np,
+                               nmk_cfg_params[i].property, &val);
+               if (ret != -EINVAL) {
+                       if (nmk_dt_pin_config(i, val, &cfg) == 0) {
+                               *configs |= cfg;
+                               has_config = 1;
+                       }
+               }
+       }
+
+       return has_config;
+}
+
+int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
+               struct device_node *np,
+               struct pinctrl_map **map,
+               unsigned *reserved_maps,
+               unsigned *num_maps)
+{
+       int ret;
+       const char *function = NULL;
+       unsigned long configs = 0;
+       bool has_config = 0;
+       unsigned reserve = 0;
+       struct property *prop;
+       const char *group, *gpio_name;
+       struct device_node *np_config;
+
+       ret = of_property_read_string(np, "ste,function", &function);
+       if (ret >= 0)
+               reserve = 1;
+
+       has_config = nmk_pinctrl_dt_get_config(np, &configs);
+
+       np_config = of_parse_phandle(np, "ste,config", 0);
+       if (np_config)
+               has_config |= nmk_pinctrl_dt_get_config(np_config, &configs);
+
+       ret = of_property_count_strings(np, "ste,pins");
+       if (ret < 0)
+               goto exit;
+
+       if (has_config)
+               reserve++;
+
+       reserve *= ret;
+
+       ret = nmk_dt_reserve_map(map, reserved_maps, num_maps, reserve);
+       if (ret < 0)
+               goto exit;
+
+       of_property_for_each_string(np, "ste,pins", prop, group) {
+               if (function) {
+                       ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps,
+                                         group, function);
+                       if (ret < 0)
+                               goto exit;
+               }
+               if (has_config) {
+                       gpio_name = nmk_find_pin_name(pctldev, group);
+
+                       ret = nmk_dt_add_map_configs(map, reserved_maps, num_maps,
+                                             gpio_name, &configs, 1);
+                       if (ret < 0)
+                               goto exit;
+               }
+
+       }
+exit:
+       return ret;
+}
+
+int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
+                                struct device_node *np_config,
+                                struct pinctrl_map **map, unsigned *num_maps)
+{
+       unsigned reserved_maps;
+       struct device_node *np;
+       int ret;
+
+       reserved_maps = 0;
+       *map = NULL;
+       *num_maps = 0;
+
+       for_each_child_of_node(np_config, np) {
+               ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map,
+                               &reserved_maps, num_maps);
+               if (ret < 0) {
+                       nmk_pinctrl_dt_free_map(pctldev, *map, *num_maps);
+                       return ret;
+               }
+       }
+
+       return 0;
+}
+
 static struct pinctrl_ops nmk_pinctrl_ops = {
        .get_groups_count = nmk_get_groups_cnt,
        .get_group_name = nmk_get_group_name,
        .get_group_pins = nmk_get_group_pins,
        .pin_dbg_show = nmk_pin_dbg_show,
+       .dt_node_to_map = nmk_pinctrl_dt_node_to_map,
+       .dt_free_map = nmk_pinctrl_dt_free_map,
 };
 
 static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
@@ -1846,16 +2104,39 @@ static struct pinctrl_desc nmk_pinctrl_desc = {
 
 static const struct of_device_id nmk_pinctrl_match[] = {
        {
-               .compatible = "stericsson,nmk_pinctrl",
+               .compatible = "stericsson,nmk-pinctrl",
                .data = (void *)PINCTRL_NMK_DB8500,
        },
        {},
 };
 
+static int nmk_pinctrl_suspend(struct platform_device *pdev, pm_message_t state)
+{
+       struct nmk_pinctrl *npct;
+
+       npct = platform_get_drvdata(pdev);
+       if (!npct)
+               return -EINVAL;
+
+       return pinctrl_force_sleep(npct->pctl);
+}
+
+static int nmk_pinctrl_resume(struct platform_device *pdev)
+{
+       struct nmk_pinctrl *npct;
+
+       npct = platform_get_drvdata(pdev);
+       if (!npct)
+               return -EINVAL;
+
+       return pinctrl_force_default(npct->pctl);
+}
+
 static int nmk_pinctrl_probe(struct platform_device *pdev)
 {
        const struct platform_device_id *platid = platform_get_device_id(pdev);
        struct device_node *np = pdev->dev.of_node;
+       struct device_node *prcm_np;
        struct nmk_pinctrl *npct;
        struct resource *res;
        unsigned int version = 0;
@@ -1884,21 +2165,26 @@ static int nmk_pinctrl_probe(struct platform_device *pdev)
        if (version == PINCTRL_NMK_DB8540)
                nmk_pinctrl_db8540_init(&npct->soc);
 
+       if (np) {
+               prcm_np = of_parse_phandle(np, "prcm", 0);
+               if (prcm_np)
+                       npct->prcm_base = of_iomap(prcm_np, 0);
+       }
+
+       /* Allow platform passed information to over-write DT. */
        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-       if (res) {
+       if (res)
                npct->prcm_base = devm_ioremap(&pdev->dev, res->start,
                                               resource_size(res));
-               if (!npct->prcm_base) {
-                       dev_err(&pdev->dev,
-                               "failed to ioremap PRCM registers\n");
-                       return -ENOMEM;
+       if (!npct->prcm_base) {
+               if (version == PINCTRL_NMK_STN8815) {
+                       dev_info(&pdev->dev,
+                                "No PRCM base, "
+                                "assuming no ALT-Cx control is available\n");
+               } else {
+                       dev_err(&pdev->dev, "missing PRCM base address\n");
+                       return -EINVAL;
                }
-       } else if (version == PINCTRL_NMK_STN8815) {
-               dev_info(&pdev->dev,
-                        "No PRCM base, assume no ALT-Cx control is available\n");
-       } else {
-               dev_err(&pdev->dev, "missing PRCM base address\n");
-               return -EINVAL;
        }
 
        /*
@@ -1963,6 +2249,10 @@ static struct platform_driver nmk_pinctrl_driver = {
        },
        .probe = nmk_pinctrl_probe,
        .id_table = nmk_pinctrl_id,
+#ifdef CONFIG_PM
+       .suspend = nmk_pinctrl_suspend,
+       .resume = nmk_pinctrl_resume,
+#endif
 };
 
 static int __init nmk_gpio_init(void)
index fd7b24cd89084d923dd2cc1cc2a581695a040deb..5c20ed056054035eecf80d3ed3718bf5729127a5 100644 (file)
@@ -716,7 +716,6 @@ static int samsung_pinctrl_register(struct platform_device *pdev,
        }
        ctrldesc->pins = pindesc;
        ctrldesc->npins = drvdata->ctrl->nr_pins;
-       ctrldesc->npins = drvdata->ctrl->nr_pins;
 
        /* dynamically populate the pin number and pin name for pindesc */
        for (pin = 0, pdesc = pindesc; pin < ctrldesc->npins; pin++, pdesc++)
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
new file mode 100644 (file)
index 0000000..80b11e3
--- /dev/null
@@ -0,0 +1,1505 @@
+/*
+ * Allwinner A1X SoCs pinctrl driver.
+ *
+ * Copyright (C) 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "core.h"
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin sun4i_a10_pins[] = {
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out"),
+               SUNXI_FUNCTION(0x4, "uart1")),          /* TX */
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out"),
+               SUNXI_FUNCTION(0x4, "uart1")),          /* RX */
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out"),
+               SUNXI_FUNCTION(0x4, "uart1")),          /* RTS */
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out"),
+               SUNXI_FUNCTION(0x4, "uart1")),          /* CTS */
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out"),
+               SUNXI_FUNCTION(0x4, "uart1")),          /* DTR */
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out"),
+               SUNXI_FUNCTION(0x4, "uart1")),          /* DSR */
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out"),
+               SUNXI_FUNCTION(0x4, "uart1")),          /* DCD */
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out"),
+               SUNXI_FUNCTION(0x4, "uart1")),          /* RING */
+       /* Hole */
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB21,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB22,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out"),
+               SUNXI_FUNCTION(0x2, "uart0")),          /* TX */
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB23,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out"),
+               SUNXI_FUNCTION(0x2, "uart0")),          /* RX */
+       /* Hole */
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       /* Hole */
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       /* Hole */
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       /* Hole */
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out"),
+               SUNXI_FUNCTION(0x4, "uart0")),          /* TX */
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out"),
+               SUNXI_FUNCTION(0x4, "uart0")),          /* RX */
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       /* Hole */
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       /* Hole */
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       /* Hole */
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI0,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI1,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI2,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI3,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI4,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI5,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI6,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI7,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI8,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI9,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI10,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI21,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+};
+
+static const struct sunxi_desc_pin sun5i_a13_pins[] = {
+       /* Hole */
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       /* Hole */
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       /* Hole */
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       /* Hole */
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       /* Hole */
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       /* Hole */
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       /* Hole */
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       /* Hole */
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       /* Hole */
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out"),
+               SUNXI_FUNCTION(0x4, "uart1")),          /* TX */
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out"),
+               SUNXI_FUNCTION(0x4, "uart1")),          /* RX */
+       /* Hole */
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       /* Hole */
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out"),
+               SUNXI_FUNCTION(0x4, "uart1")),          /* TX */
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out"),
+               SUNXI_FUNCTION(0x4, "uart1")),          /* RX */
+       /* Hole */
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12,
+               SUNXI_FUNCTION(0x0, "gpio_in"),
+               SUNXI_FUNCTION(0x1, "gpio_out")),
+};
+
+static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = {
+       .pins = sun4i_a10_pins,
+       .npins = ARRAY_SIZE(sun4i_a10_pins),
+};
+
+static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = {
+       .pins = sun5i_a13_pins,
+       .npins = ARRAY_SIZE(sun5i_a13_pins),
+};
+
+static struct sunxi_pinctrl_group *
+sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
+{
+       int i;
+
+       for (i = 0; i < pctl->ngroups; i++) {
+               struct sunxi_pinctrl_group *grp = pctl->groups + i;
+
+               if (!strcmp(grp->name, group))
+                       return grp;
+       }
+
+       return NULL;
+}
+
+static struct sunxi_pinctrl_function *
+sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
+                                   const char *name)
+{
+       struct sunxi_pinctrl_function *func = pctl->functions;
+       int i;
+
+       for (i = 0; i < pctl->nfunctions; i++) {
+               if (!func[i].name)
+                       break;
+
+               if (!strcmp(func[i].name, name))
+                       return func + i;
+       }
+
+       return NULL;
+}
+
+static struct sunxi_desc_function *
+sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
+                                        const char *pin_name,
+                                        const char *func_name)
+{
+       int i;
+
+       for (i = 0; i < pctl->desc->npins; i++) {
+               const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
+
+               if (!strcmp(pin->pin.name, pin_name)) {
+                       struct sunxi_desc_function *func = pin->functions;
+
+                       while (func->name) {
+                               if (!strcmp(func->name, func_name))
+                                       return func;
+
+                               func++;
+                       }
+               }
+       }
+
+       return NULL;
+}
+
+static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
+{
+       struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+       return pctl->ngroups;
+}
+
+static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,
+                                             unsigned group)
+{
+       struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+       return pctl->groups[group].name;
+}
+
+static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
+                                     unsigned group,
+                                     const unsigned **pins,
+                                     unsigned *num_pins)
+{
+       struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+       *pins = (unsigned *)&pctl->groups[group].pin;
+       *num_pins = 1;
+
+       return 0;
+}
+
+static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
+                                     struct device_node *node,
+                                     struct pinctrl_map **map,
+                                     unsigned *num_maps)
+{
+       struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+       unsigned long *pinconfig;
+       struct property *prop;
+       const char *function;
+       const char *group;
+       int ret, nmaps, i = 0;
+       u32 val;
+
+       *map = NULL;
+       *num_maps = 0;
+
+       ret = of_property_read_string(node, "allwinner,function", &function);
+       if (ret) {
+               dev_err(pctl->dev,
+                       "missing allwinner,function property in node %s\n",
+                       node->name);
+               return -EINVAL;
+       }
+
+       nmaps = of_property_count_strings(node, "allwinner,pins") * 2;
+       if (nmaps < 0) {
+               dev_err(pctl->dev,
+                       "missing allwinner,pins property in node %s\n",
+                       node->name);
+               return -EINVAL;
+       }
+
+       *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL);
+       if (!map)
+               return -ENOMEM;
+
+       of_property_for_each_string(node, "allwinner,pins", prop, group) {
+               struct sunxi_pinctrl_group *grp =
+                       sunxi_pinctrl_find_group_by_name(pctl, group);
+               int j = 0, configlen = 0;
+
+               if (!grp) {
+                       dev_err(pctl->dev, "unknown pin %s", group);
+                       continue;
+               }
+
+               if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
+                                                             grp->name,
+                                                             function)) {
+                       dev_err(pctl->dev, "unsupported function %s on pin %s",
+                               function, group);
+                       continue;
+               }
+
+               (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
+               (*map)[i].data.mux.group = group;
+               (*map)[i].data.mux.function = function;
+
+               i++;
+
+               (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
+               (*map)[i].data.configs.group_or_pin = group;
+
+               if (of_find_property(node, "allwinner,drive", NULL))
+                       configlen++;
+               if (of_find_property(node, "allwinner,pull", NULL))
+                       configlen++;
+
+               pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL);
+
+               if (!of_property_read_u32(node, "allwinner,drive", &val)) {
+                       u16 strength = (val + 1) * 10;
+                       pinconfig[j++] =
+                               pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
+                                                        strength);
+               }
+
+               if (!of_property_read_u32(node, "allwinner,pull", &val)) {
+                       enum pin_config_param pull = PIN_CONFIG_END;
+                       if (val == 1)
+                               pull = PIN_CONFIG_BIAS_PULL_UP;
+                       else if (val == 2)
+                               pull = PIN_CONFIG_BIAS_PULL_DOWN;
+                       pinconfig[j++] = pinconf_to_config_packed(pull, 0);
+               }
+
+               (*map)[i].data.configs.configs = pinconfig;
+               (*map)[i].data.configs.num_configs = configlen;
+
+               i++;
+       }
+
+       *num_maps = nmaps;
+
+       return 0;
+}
+
+static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
+                                   struct pinctrl_map *map,
+                                   unsigned num_maps)
+{
+       int i;
+
+       for (i = 0; i < num_maps; i++) {
+               if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
+                       kfree(map[i].data.configs.configs);
+       }
+
+       kfree(map);
+}
+
+static struct pinctrl_ops sunxi_pctrl_ops = {
+       .dt_node_to_map         = sunxi_pctrl_dt_node_to_map,
+       .dt_free_map            = sunxi_pctrl_dt_free_map,
+       .get_groups_count       = sunxi_pctrl_get_groups_count,
+       .get_group_name         = sunxi_pctrl_get_group_name,
+       .get_group_pins         = sunxi_pctrl_get_group_pins,
+};
+
+static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
+                                unsigned group,
+                                unsigned long *config)
+{
+       struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+       *config = pctl->groups[group].config;
+
+       return 0;
+}
+
+static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
+                                unsigned group,
+                                unsigned long config)
+{
+       struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+       struct sunxi_pinctrl_group *g = &pctl->groups[group];
+       u32 val, mask;
+       u16 strength;
+       u8 dlevel;
+
+       switch (pinconf_to_config_param(config)) {
+       case PIN_CONFIG_DRIVE_STRENGTH:
+               strength = pinconf_to_config_argument(config);
+               if (strength > 40)
+                       return -EINVAL;
+               /*
+                * We convert from mA to what the register expects:
+                *   0: 10mA
+                *   1: 20mA
+                *   2: 30mA
+                *   3: 40mA
+                */
+               dlevel = strength / 10 - 1;
+               val = readl(pctl->membase + sunxi_dlevel_reg(g->pin));
+               mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(g->pin);
+               writel((val & ~mask) | dlevel << sunxi_dlevel_offset(g->pin),
+                       pctl->membase + sunxi_dlevel_reg(g->pin));
+               break;
+       case PIN_CONFIG_BIAS_PULL_UP:
+               val = readl(pctl->membase + sunxi_pull_reg(g->pin));
+               mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
+               writel((val & ~mask) | 1 << sunxi_pull_offset(g->pin),
+                       pctl->membase + sunxi_pull_reg(g->pin));
+               break;
+       case PIN_CONFIG_BIAS_PULL_DOWN:
+               val = readl(pctl->membase + sunxi_pull_reg(g->pin));
+               mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
+               writel((val & ~mask) | 2 << sunxi_pull_offset(g->pin),
+                       pctl->membase + sunxi_pull_reg(g->pin));
+               break;
+       default:
+               break;
+       }
+
+       /* cache the config value */
+       g->config = config;
+
+       return 0;
+}
+
+static struct pinconf_ops sunxi_pconf_ops = {
+       .pin_config_group_get   = sunxi_pconf_group_get,
+       .pin_config_group_set   = sunxi_pconf_group_set,
+};
+
+static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
+{
+       struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+       return pctl->nfunctions;
+}
+
+static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,
+                                          unsigned function)
+{
+       struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+       return pctl->functions[function].name;
+}
+
+static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,
+                                    unsigned function,
+                                    const char * const **groups,
+                                    unsigned * const num_groups)
+{
+       struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+       *groups = pctl->functions[function].groups;
+       *num_groups = pctl->functions[function].ngroups;
+
+       return 0;
+}
+
+static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
+                                unsigned pin,
+                                u8 config)
+{
+       struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+       u32 val = readl(pctl->membase + sunxi_mux_reg(pin));
+       u32 mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
+       writel((val & ~mask) | config << sunxi_mux_offset(pin),
+               pctl->membase + sunxi_mux_reg(pin));
+}
+
+static int sunxi_pmx_enable(struct pinctrl_dev *pctldev,
+                           unsigned function,
+                           unsigned group)
+{
+       struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+       struct sunxi_pinctrl_group *g = pctl->groups + group;
+       struct sunxi_pinctrl_function *func = pctl->functions + function;
+       struct sunxi_desc_function *desc =
+               sunxi_pinctrl_desc_find_function_by_name(pctl,
+                                                        g->name,
+                                                        func->name);
+
+       if (!desc)
+               return -EINVAL;
+
+       sunxi_pmx_set(pctldev, g->pin, desc->muxval);
+
+       return 0;
+}
+
+static int
+sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
+                       struct pinctrl_gpio_range *range,
+                       unsigned offset,
+                       bool input)
+{
+       struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+       struct sunxi_desc_function *desc;
+       char pin_name[SUNXI_PIN_NAME_MAX_LEN];
+       const char *func;
+       u8 bank, pin;
+       int ret;
+
+       bank = (offset) / PINS_PER_BANK;
+       pin = (offset) % PINS_PER_BANK;
+
+       ret = sprintf(pin_name, "P%c%d", 'A' + bank, pin);
+       if (!ret)
+               goto error;
+
+       if (input)
+               func = "gpio_in";
+       else
+               func = "gpio_out";
+
+       desc = sunxi_pinctrl_desc_find_function_by_name(pctl,
+                                                       pin_name,
+                                                       func);
+       if (!desc) {
+               ret = -EINVAL;
+               goto error;
+       }
+
+       sunxi_pmx_set(pctldev, offset, desc->muxval);
+
+       ret = 0;
+
+error:
+       return ret;
+}
+
+static struct pinmux_ops sunxi_pmx_ops = {
+       .get_functions_count    = sunxi_pmx_get_funcs_cnt,
+       .get_function_name      = sunxi_pmx_get_func_name,
+       .get_function_groups    = sunxi_pmx_get_func_groups,
+       .enable                 = sunxi_pmx_enable,
+       .gpio_set_direction     = sunxi_pmx_gpio_set_direction,
+};
+
+static struct pinctrl_desc sunxi_pctrl_desc = {
+       .confops        = &sunxi_pconf_ops,
+       .pctlops        = &sunxi_pctrl_ops,
+       .pmxops         = &sunxi_pmx_ops,
+};
+
+static int sunxi_pinctrl_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+       return pinctrl_request_gpio(chip->base + offset);
+}
+
+static void sunxi_pinctrl_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+       pinctrl_free_gpio(chip->base + offset);
+}
+
+static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
+                                       unsigned offset)
+{
+       return pinctrl_gpio_direction_input(chip->base + offset);
+}
+
+static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+       struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
+
+       u32 reg = sunxi_data_reg(offset);
+       u8 index = sunxi_data_offset(offset);
+       u32 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
+
+       return val;
+}
+
+static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
+                                       unsigned offset, int value)
+{
+       return pinctrl_gpio_direction_output(chip->base + offset);
+}
+
+static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
+                               unsigned offset, int value)
+{
+       struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
+       u32 reg = sunxi_data_reg(offset);
+       u8 index = sunxi_data_offset(offset);
+
+       writel((value & DATA_PINS_MASK) << index, pctl->membase + reg);
+}
+
+static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
+                               const struct of_phandle_args *gpiospec,
+                               u32 *flags)
+{
+       int pin, base;
+
+       base = PINS_PER_BANK * gpiospec->args[0];
+       pin = base + gpiospec->args[1];
+
+       if (pin > (gc->base + gc->ngpio))
+               return -EINVAL;
+
+       if (flags)
+               *flags = gpiospec->args[2];
+
+       return pin;
+}
+
+static struct gpio_chip sunxi_pinctrl_gpio_chip = {
+       .owner                  = THIS_MODULE,
+       .request                = sunxi_pinctrl_gpio_request,
+       .free                   = sunxi_pinctrl_gpio_free,
+       .direction_input        = sunxi_pinctrl_gpio_direction_input,
+       .direction_output       = sunxi_pinctrl_gpio_direction_output,
+       .get                    = sunxi_pinctrl_gpio_get,
+       .set                    = sunxi_pinctrl_gpio_set,
+       .of_xlate               = sunxi_pinctrl_gpio_of_xlate,
+       .of_gpio_n_cells        = 3,
+       .can_sleep              = 0,
+};
+
+static struct of_device_id sunxi_pinctrl_match[] = {
+       { .compatible = "allwinner,sun4i-a10-pinctrl", .data = (void *)&sun4i_a10_pinctrl_data },
+       { .compatible = "allwinner,sun5i-a13-pinctrl", .data = (void *)&sun5i_a13_pinctrl_data },
+       {}
+};
+MODULE_DEVICE_TABLE(of, sunxi_pinctrl_match);
+
+static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
+                                       const char *name)
+{
+       struct sunxi_pinctrl_function *func = pctl->functions;
+
+       while (func->name) {
+               /* function already there */
+               if (strcmp(func->name, name) == 0) {
+                       func->ngroups++;
+                       return -EEXIST;
+               }
+               func++;
+       }
+
+       func->name = name;
+       func->ngroups = 1;
+
+       pctl->nfunctions++;
+
+       return 0;
+}
+
+static int sunxi_pinctrl_build_state(struct platform_device *pdev)
+{
+       struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
+       int i;
+
+       pctl->ngroups = pctl->desc->npins;
+
+       /* Allocate groups */
+       pctl->groups = devm_kzalloc(&pdev->dev,
+                                   pctl->ngroups * sizeof(*pctl->groups),
+                                   GFP_KERNEL);
+       if (!pctl->groups)
+               return -ENOMEM;
+
+       for (i = 0; i < pctl->desc->npins; i++) {
+               const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
+               struct sunxi_pinctrl_group *group = pctl->groups + i;
+
+               group->name = pin->pin.name;
+               group->pin = pin->pin.number;
+       }
+
+       /*
+        * We suppose that we won't have any more functions than pins,
+        * we'll reallocate that later anyway
+        */
+       pctl->functions = devm_kzalloc(&pdev->dev,
+                               pctl->desc->npins * sizeof(*pctl->functions),
+                               GFP_KERNEL);
+       if (!pctl->functions)
+               return -ENOMEM;
+
+       /* Count functions and their associated groups */
+       for (i = 0; i < pctl->desc->npins; i++) {
+               const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
+               struct sunxi_desc_function *func = pin->functions;
+
+               while (func->name) {
+                       sunxi_pinctrl_add_function(pctl, func->name);
+                       func++;
+               }
+       }
+
+       pctl->functions = krealloc(pctl->functions,
+                               pctl->nfunctions * sizeof(*pctl->functions),
+                               GFP_KERNEL);
+
+       for (i = 0; i < pctl->desc->npins; i++) {
+               const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
+               struct sunxi_desc_function *func = pin->functions;
+
+               while (func->name) {
+                       struct sunxi_pinctrl_function *func_item;
+                       const char **func_grp;
+
+                       func_item = sunxi_pinctrl_find_function_by_name(pctl,
+                                                                       func->name);
+                       if (!func_item)
+                               return -EINVAL;
+
+                       if (!func_item->groups) {
+                               func_item->groups =
+                                       devm_kzalloc(&pdev->dev,
+                                                    func_item->ngroups * sizeof(*func_item->groups),
+                                                    GFP_KERNEL);
+                               if (!func_item->groups)
+                                       return -ENOMEM;
+                       }
+
+                       func_grp = func_item->groups;
+                       while (*func_grp)
+                               func_grp++;
+
+                       *func_grp = pin->pin.name;
+                       func++;
+               }
+       }
+
+       return 0;
+}
+
+static int sunxi_pinctrl_probe(struct platform_device *pdev)
+{
+       struct device_node *node = pdev->dev.of_node;
+       const struct of_device_id *device;
+       struct pinctrl_pin_desc *pins;
+       struct sunxi_pinctrl *pctl;
+       int i, ret, last_pin;
+
+       pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
+       if (!pctl)
+               return -ENOMEM;
+       platform_set_drvdata(pdev, pctl);
+
+       pctl->membase = of_iomap(node, 0);
+       if (!pctl->membase)
+               return -ENOMEM;
+
+       device = of_match_device(sunxi_pinctrl_match, &pdev->dev);
+       if (!device)
+               return -ENODEV;
+
+       pctl->desc = (struct sunxi_pinctrl_desc *)device->data;
+
+       ret = sunxi_pinctrl_build_state(pdev);
+       if (ret) {
+               dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
+               return ret;
+       }
+
+       pins = devm_kzalloc(&pdev->dev,
+                           pctl->desc->npins * sizeof(*pins),
+                           GFP_KERNEL);
+       if (!pins)
+               return -ENOMEM;
+
+       for (i = 0; i < pctl->desc->npins; i++)
+               pins[i] = pctl->desc->pins[i].pin;
+
+       sunxi_pctrl_desc.name = dev_name(&pdev->dev);
+       sunxi_pctrl_desc.owner = THIS_MODULE;
+       sunxi_pctrl_desc.pins = pins;
+       sunxi_pctrl_desc.npins = pctl->desc->npins;
+       pctl->dev = &pdev->dev;
+       pctl->pctl_dev = pinctrl_register(&sunxi_pctrl_desc,
+                                         &pdev->dev, pctl);
+       if (!pctl->pctl_dev) {
+               dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
+               return -EINVAL;
+       }
+
+       pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
+       if (!pctl->chip) {
+               ret = -ENOMEM;
+               goto pinctrl_error;
+       }
+
+       last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
+       pctl->chip = &sunxi_pinctrl_gpio_chip;
+       pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK);
+       pctl->chip->label = dev_name(&pdev->dev);
+       pctl->chip->dev = &pdev->dev;
+       pctl->chip->base = 0;
+
+       ret = gpiochip_add(pctl->chip);
+       if (ret)
+               goto pinctrl_error;
+
+       for (i = 0; i < pctl->desc->npins; i++) {
+               const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
+
+               ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
+                                            pin->pin.number,
+                                            pin->pin.number, 1);
+               if (ret)
+                       goto gpiochip_error;
+       }
+
+       dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
+
+       return 0;
+
+gpiochip_error:
+       ret = gpiochip_remove(pctl->chip);
+pinctrl_error:
+       pinctrl_unregister(pctl->pctl_dev);
+       return ret;
+}
+
+static struct platform_driver sunxi_pinctrl_driver = {
+       .probe = sunxi_pinctrl_probe,
+       .driver = {
+               .name = "sunxi-pinctrl",
+               .owner = THIS_MODULE,
+               .of_match_table = sunxi_pinctrl_match,
+       },
+};
+module_platform_driver(sunxi_pinctrl_driver);
+
+MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
+MODULE_DESCRIPTION("Allwinner A1X pinctrl driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/pinctrl-sunxi.h b/drivers/pinctrl/pinctrl-sunxi.h
new file mode 100644 (file)
index 0000000..e921621
--- /dev/null
@@ -0,0 +1,478 @@
+/*
+ * Allwinner A1X SoCs pinctrl driver.
+ *
+ * Copyright (C) 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PINCTRL_SUNXI_H
+#define __PINCTRL_SUNXI_H
+
+#include <linux/kernel.h>
+
+#define PA_BASE        0
+#define PB_BASE        32
+#define PC_BASE        64
+#define PD_BASE        96
+#define PE_BASE        128
+#define PF_BASE        160
+#define PG_BASE        192
+#define PH_BASE        224
+#define PI_BASE        256
+
+#define SUNXI_PINCTRL_PIN_PA0  PINCTRL_PIN(PA_BASE + 0, "PA0")
+#define SUNXI_PINCTRL_PIN_PA1  PINCTRL_PIN(PA_BASE + 1, "PA1")
+#define SUNXI_PINCTRL_PIN_PA2  PINCTRL_PIN(PA_BASE + 2, "PA2")
+#define SUNXI_PINCTRL_PIN_PA3  PINCTRL_PIN(PA_BASE + 3, "PA3")
+#define SUNXI_PINCTRL_PIN_PA4  PINCTRL_PIN(PA_BASE + 4, "PA4")
+#define SUNXI_PINCTRL_PIN_PA5  PINCTRL_PIN(PA_BASE + 5, "PA5")
+#define SUNXI_PINCTRL_PIN_PA6  PINCTRL_PIN(PA_BASE + 6, "PA6")
+#define SUNXI_PINCTRL_PIN_PA7  PINCTRL_PIN(PA_BASE + 7, "PA7")
+#define SUNXI_PINCTRL_PIN_PA8  PINCTRL_PIN(PA_BASE + 8, "PA8")
+#define SUNXI_PINCTRL_PIN_PA9  PINCTRL_PIN(PA_BASE + 9, "PA9")
+#define SUNXI_PINCTRL_PIN_PA10 PINCTRL_PIN(PA_BASE + 10, "PA10")
+#define SUNXI_PINCTRL_PIN_PA11 PINCTRL_PIN(PA_BASE + 11, "PA11")
+#define SUNXI_PINCTRL_PIN_PA12 PINCTRL_PIN(PA_BASE + 12, "PA12")
+#define SUNXI_PINCTRL_PIN_PA13 PINCTRL_PIN(PA_BASE + 13, "PA13")
+#define SUNXI_PINCTRL_PIN_PA14 PINCTRL_PIN(PA_BASE + 14, "PA14")
+#define SUNXI_PINCTRL_PIN_PA15 PINCTRL_PIN(PA_BASE + 15, "PA15")
+#define SUNXI_PINCTRL_PIN_PA16 PINCTRL_PIN(PA_BASE + 16, "PA16")
+#define SUNXI_PINCTRL_PIN_PA17 PINCTRL_PIN(PA_BASE + 17, "PA17")
+#define SUNXI_PINCTRL_PIN_PA18 PINCTRL_PIN(PA_BASE + 18, "PA18")
+#define SUNXI_PINCTRL_PIN_PA19 PINCTRL_PIN(PA_BASE + 19, "PA19")
+#define SUNXI_PINCTRL_PIN_PA20 PINCTRL_PIN(PA_BASE + 20, "PA20")
+#define SUNXI_PINCTRL_PIN_PA21 PINCTRL_PIN(PA_BASE + 21, "PA21")
+#define SUNXI_PINCTRL_PIN_PA22 PINCTRL_PIN(PA_BASE + 22, "PA22")
+#define SUNXI_PINCTRL_PIN_PA23 PINCTRL_PIN(PA_BASE + 23, "PA23")
+#define SUNXI_PINCTRL_PIN_PA24 PINCTRL_PIN(PA_BASE + 24, "PA24")
+#define SUNXI_PINCTRL_PIN_PA25 PINCTRL_PIN(PA_BASE + 25, "PA25")
+#define SUNXI_PINCTRL_PIN_PA26 PINCTRL_PIN(PA_BASE + 26, "PA26")
+#define SUNXI_PINCTRL_PIN_PA27 PINCTRL_PIN(PA_BASE + 27, "PA27")
+#define SUNXI_PINCTRL_PIN_PA28 PINCTRL_PIN(PA_BASE + 28, "PA28")
+#define SUNXI_PINCTRL_PIN_PA29 PINCTRL_PIN(PA_BASE + 29, "PA29")
+#define SUNXI_PINCTRL_PIN_PA30 PINCTRL_PIN(PA_BASE + 30, "PA30")
+#define SUNXI_PINCTRL_PIN_PA31 PINCTRL_PIN(PA_BASE + 31, "PA31")
+
+#define SUNXI_PINCTRL_PIN_PB0  PINCTRL_PIN(PB_BASE + 0, "PB0")
+#define SUNXI_PINCTRL_PIN_PB1  PINCTRL_PIN(PB_BASE + 1, "PB1")
+#define SUNXI_PINCTRL_PIN_PB2  PINCTRL_PIN(PB_BASE + 2, "PB2")
+#define SUNXI_PINCTRL_PIN_PB3  PINCTRL_PIN(PB_BASE + 3, "PB3")
+#define SUNXI_PINCTRL_PIN_PB4  PINCTRL_PIN(PB_BASE + 4, "PB4")
+#define SUNXI_PINCTRL_PIN_PB5  PINCTRL_PIN(PB_BASE + 5, "PB5")
+#define SUNXI_PINCTRL_PIN_PB6  PINCTRL_PIN(PB_BASE + 6, "PB6")
+#define SUNXI_PINCTRL_PIN_PB7  PINCTRL_PIN(PB_BASE + 7, "PB7")
+#define SUNXI_PINCTRL_PIN_PB8  PINCTRL_PIN(PB_BASE + 8, "PB8")
+#define SUNXI_PINCTRL_PIN_PB9  PINCTRL_PIN(PB_BASE + 9, "PB9")
+#define SUNXI_PINCTRL_PIN_PB10 PINCTRL_PIN(PB_BASE + 10, "PB10")
+#define SUNXI_PINCTRL_PIN_PB11 PINCTRL_PIN(PB_BASE + 11, "PB11")
+#define SUNXI_PINCTRL_PIN_PB12 PINCTRL_PIN(PB_BASE + 12, "PB12")
+#define SUNXI_PINCTRL_PIN_PB13 PINCTRL_PIN(PB_BASE + 13, "PB13")
+#define SUNXI_PINCTRL_PIN_PB14 PINCTRL_PIN(PB_BASE + 14, "PB14")
+#define SUNXI_PINCTRL_PIN_PB15 PINCTRL_PIN(PB_BASE + 15, "PB15")
+#define SUNXI_PINCTRL_PIN_PB16 PINCTRL_PIN(PB_BASE + 16, "PB16")
+#define SUNXI_PINCTRL_PIN_PB17 PINCTRL_PIN(PB_BASE + 17, "PB17")
+#define SUNXI_PINCTRL_PIN_PB18 PINCTRL_PIN(PB_BASE + 18, "PB18")
+#define SUNXI_PINCTRL_PIN_PB19 PINCTRL_PIN(PB_BASE + 19, "PB19")
+#define SUNXI_PINCTRL_PIN_PB20 PINCTRL_PIN(PB_BASE + 20, "PB20")
+#define SUNXI_PINCTRL_PIN_PB21 PINCTRL_PIN(PB_BASE + 21, "PB21")
+#define SUNXI_PINCTRL_PIN_PB22 PINCTRL_PIN(PB_BASE + 22, "PB22")
+#define SUNXI_PINCTRL_PIN_PB23 PINCTRL_PIN(PB_BASE + 23, "PB23")
+#define SUNXI_PINCTRL_PIN_PB24 PINCTRL_PIN(PB_BASE + 24, "PB24")
+#define SUNXI_PINCTRL_PIN_PB25 PINCTRL_PIN(PB_BASE + 25, "PB25")
+#define SUNXI_PINCTRL_PIN_PB26 PINCTRL_PIN(PB_BASE + 26, "PB26")
+#define SUNXI_PINCTRL_PIN_PB27 PINCTRL_PIN(PB_BASE + 27, "PB27")
+#define SUNXI_PINCTRL_PIN_PB28 PINCTRL_PIN(PB_BASE + 28, "PB28")
+#define SUNXI_PINCTRL_PIN_PB29 PINCTRL_PIN(PB_BASE + 29, "PB29")
+#define SUNXI_PINCTRL_PIN_PB30 PINCTRL_PIN(PB_BASE + 30, "PB30")
+#define SUNXI_PINCTRL_PIN_PB31 PINCTRL_PIN(PB_BASE + 31, "PB31")
+
+#define SUNXI_PINCTRL_PIN_PC0  PINCTRL_PIN(PC_BASE + 0, "PC0")
+#define SUNXI_PINCTRL_PIN_PC1  PINCTRL_PIN(PC_BASE + 1, "PC1")
+#define SUNXI_PINCTRL_PIN_PC2  PINCTRL_PIN(PC_BASE + 2, "PC2")
+#define SUNXI_PINCTRL_PIN_PC3  PINCTRL_PIN(PC_BASE + 3, "PC3")
+#define SUNXI_PINCTRL_PIN_PC4  PINCTRL_PIN(PC_BASE + 4, "PC4")
+#define SUNXI_PINCTRL_PIN_PC5  PINCTRL_PIN(PC_BASE + 5, "PC5")
+#define SUNXI_PINCTRL_PIN_PC6  PINCTRL_PIN(PC_BASE + 6, "PC6")
+#define SUNXI_PINCTRL_PIN_PC7  PINCTRL_PIN(PC_BASE + 7, "PC7")
+#define SUNXI_PINCTRL_PIN_PC8  PINCTRL_PIN(PC_BASE + 8, "PC8")
+#define SUNXI_PINCTRL_PIN_PC9  PINCTRL_PIN(PC_BASE + 9, "PC9")
+#define SUNXI_PINCTRL_PIN_PC10 PINCTRL_PIN(PC_BASE + 10, "PC10")
+#define SUNXI_PINCTRL_PIN_PC11 PINCTRL_PIN(PC_BASE + 11, "PC11")
+#define SUNXI_PINCTRL_PIN_PC12 PINCTRL_PIN(PC_BASE + 12, "PC12")
+#define SUNXI_PINCTRL_PIN_PC13 PINCTRL_PIN(PC_BASE + 13, "PC13")
+#define SUNXI_PINCTRL_PIN_PC14 PINCTRL_PIN(PC_BASE + 14, "PC14")
+#define SUNXI_PINCTRL_PIN_PC15 PINCTRL_PIN(PC_BASE + 15, "PC15")
+#define SUNXI_PINCTRL_PIN_PC16 PINCTRL_PIN(PC_BASE + 16, "PC16")
+#define SUNXI_PINCTRL_PIN_PC17 PINCTRL_PIN(PC_BASE + 17, "PC17")
+#define SUNXI_PINCTRL_PIN_PC18 PINCTRL_PIN(PC_BASE + 18, "PC18")
+#define SUNXI_PINCTRL_PIN_PC19 PINCTRL_PIN(PC_BASE + 19, "PC19")
+#define SUNXI_PINCTRL_PIN_PC20 PINCTRL_PIN(PC_BASE + 20, "PC20")
+#define SUNXI_PINCTRL_PIN_PC21 PINCTRL_PIN(PC_BASE + 21, "PC21")
+#define SUNXI_PINCTRL_PIN_PC22 PINCTRL_PIN(PC_BASE + 22, "PC22")
+#define SUNXI_PINCTRL_PIN_PC23 PINCTRL_PIN(PC_BASE + 23, "PC23")
+#define SUNXI_PINCTRL_PIN_PC24 PINCTRL_PIN(PC_BASE + 24, "PC24")
+#define SUNXI_PINCTRL_PIN_PC25 PINCTRL_PIN(PC_BASE + 25, "PC25")
+#define SUNXI_PINCTRL_PIN_PC26 PINCTRL_PIN(PC_BASE + 26, "PC26")
+#define SUNXI_PINCTRL_PIN_PC27 PINCTRL_PIN(PC_BASE + 27, "PC27")
+#define SUNXI_PINCTRL_PIN_PC28 PINCTRL_PIN(PC_BASE + 28, "PC28")
+#define SUNXI_PINCTRL_PIN_PC29 PINCTRL_PIN(PC_BASE + 29, "PC29")
+#define SUNXI_PINCTRL_PIN_PC30 PINCTRL_PIN(PC_BASE + 30, "PC30")
+#define SUNXI_PINCTRL_PIN_PC31 PINCTRL_PIN(PC_BASE + 31, "PC31")
+
+#define SUNXI_PINCTRL_PIN_PD0  PINCTRL_PIN(PD_BASE + 0, "PD0")
+#define SUNXI_PINCTRL_PIN_PD1  PINCTRL_PIN(PD_BASE + 1, "PD1")
+#define SUNXI_PINCTRL_PIN_PD2  PINCTRL_PIN(PD_BASE + 2, "PD2")
+#define SUNXI_PINCTRL_PIN_PD3  PINCTRL_PIN(PD_BASE + 3, "PD3")
+#define SUNXI_PINCTRL_PIN_PD4  PINCTRL_PIN(PD_BASE + 4, "PD4")
+#define SUNXI_PINCTRL_PIN_PD5  PINCTRL_PIN(PD_BASE + 5, "PD5")
+#define SUNXI_PINCTRL_PIN_PD6  PINCTRL_PIN(PD_BASE + 6, "PD6")
+#define SUNXI_PINCTRL_PIN_PD7  PINCTRL_PIN(PD_BASE + 7, "PD7")
+#define SUNXI_PINCTRL_PIN_PD8  PINCTRL_PIN(PD_BASE + 8, "PD8")
+#define SUNXI_PINCTRL_PIN_PD9  PINCTRL_PIN(PD_BASE + 9, "PD9")
+#define SUNXI_PINCTRL_PIN_PD10 PINCTRL_PIN(PD_BASE + 10, "PD10")
+#define SUNXI_PINCTRL_PIN_PD11 PINCTRL_PIN(PD_BASE + 11, "PD11")
+#define SUNXI_PINCTRL_PIN_PD12 PINCTRL_PIN(PD_BASE + 12, "PD12")
+#define SUNXI_PINCTRL_PIN_PD13 PINCTRL_PIN(PD_BASE + 13, "PD13")
+#define SUNXI_PINCTRL_PIN_PD14 PINCTRL_PIN(PD_BASE + 14, "PD14")
+#define SUNXI_PINCTRL_PIN_PD15 PINCTRL_PIN(PD_BASE + 15, "PD15")
+#define SUNXI_PINCTRL_PIN_PD16 PINCTRL_PIN(PD_BASE + 16, "PD16")
+#define SUNXI_PINCTRL_PIN_PD17 PINCTRL_PIN(PD_BASE + 17, "PD17")
+#define SUNXI_PINCTRL_PIN_PD18 PINCTRL_PIN(PD_BASE + 18, "PD18")
+#define SUNXI_PINCTRL_PIN_PD19 PINCTRL_PIN(PD_BASE + 19, "PD19")
+#define SUNXI_PINCTRL_PIN_PD20 PINCTRL_PIN(PD_BASE + 20, "PD20")
+#define SUNXI_PINCTRL_PIN_PD21 PINCTRL_PIN(PD_BASE + 21, "PD21")
+#define SUNXI_PINCTRL_PIN_PD22 PINCTRL_PIN(PD_BASE + 22, "PD22")
+#define SUNXI_PINCTRL_PIN_PD23 PINCTRL_PIN(PD_BASE + 23, "PD23")
+#define SUNXI_PINCTRL_PIN_PD24 PINCTRL_PIN(PD_BASE + 24, "PD24")
+#define SUNXI_PINCTRL_PIN_PD25 PINCTRL_PIN(PD_BASE + 25, "PD25")
+#define SUNXI_PINCTRL_PIN_PD26 PINCTRL_PIN(PD_BASE + 26, "PD26")
+#define SUNXI_PINCTRL_PIN_PD27 PINCTRL_PIN(PD_BASE + 27, "PD27")
+#define SUNXI_PINCTRL_PIN_PD28 PINCTRL_PIN(PD_BASE + 28, "PD28")
+#define SUNXI_PINCTRL_PIN_PD29 PINCTRL_PIN(PD_BASE + 29, "PD29")
+#define SUNXI_PINCTRL_PIN_PD30 PINCTRL_PIN(PD_BASE + 30, "PD30")
+#define SUNXI_PINCTRL_PIN_PD31 PINCTRL_PIN(PD_BASE + 31, "PD31")
+
+#define SUNXI_PINCTRL_PIN_PE0  PINCTRL_PIN(PE_BASE + 0, "PE0")
+#define SUNXI_PINCTRL_PIN_PE1  PINCTRL_PIN(PE_BASE + 1, "PE1")
+#define SUNXI_PINCTRL_PIN_PE2  PINCTRL_PIN(PE_BASE + 2, "PE2")
+#define SUNXI_PINCTRL_PIN_PE3  PINCTRL_PIN(PE_BASE + 3, "PE3")
+#define SUNXI_PINCTRL_PIN_PE4  PINCTRL_PIN(PE_BASE + 4, "PE4")
+#define SUNXI_PINCTRL_PIN_PE5  PINCTRL_PIN(PE_BASE + 5, "PE5")
+#define SUNXI_PINCTRL_PIN_PE6  PINCTRL_PIN(PE_BASE + 6, "PE6")
+#define SUNXI_PINCTRL_PIN_PE7  PINCTRL_PIN(PE_BASE + 7, "PE7")
+#define SUNXI_PINCTRL_PIN_PE8  PINCTRL_PIN(PE_BASE + 8, "PE8")
+#define SUNXI_PINCTRL_PIN_PE9  PINCTRL_PIN(PE_BASE + 9, "PE9")
+#define SUNXI_PINCTRL_PIN_PE10 PINCTRL_PIN(PE_BASE + 10, "PE10")
+#define SUNXI_PINCTRL_PIN_PE11 PINCTRL_PIN(PE_BASE + 11, "PE11")
+#define SUNXI_PINCTRL_PIN_PE12 PINCTRL_PIN(PE_BASE + 12, "PE12")
+#define SUNXI_PINCTRL_PIN_PE13 PINCTRL_PIN(PE_BASE + 13, "PE13")
+#define SUNXI_PINCTRL_PIN_PE14 PINCTRL_PIN(PE_BASE + 14, "PE14")
+#define SUNXI_PINCTRL_PIN_PE15 PINCTRL_PIN(PE_BASE + 15, "PE15")
+#define SUNXI_PINCTRL_PIN_PE16 PINCTRL_PIN(PE_BASE + 16, "PE16")
+#define SUNXI_PINCTRL_PIN_PE17 PINCTRL_PIN(PE_BASE + 17, "PE17")
+#define SUNXI_PINCTRL_PIN_PE18 PINCTRL_PIN(PE_BASE + 18, "PE18")
+#define SUNXI_PINCTRL_PIN_PE19 PINCTRL_PIN(PE_BASE + 19, "PE19")
+#define SUNXI_PINCTRL_PIN_PE20 PINCTRL_PIN(PE_BASE + 20, "PE20")
+#define SUNXI_PINCTRL_PIN_PE21 PINCTRL_PIN(PE_BASE + 21, "PE21")
+#define SUNXI_PINCTRL_PIN_PE22 PINCTRL_PIN(PE_BASE + 22, "PE22")
+#define SUNXI_PINCTRL_PIN_PE23 PINCTRL_PIN(PE_BASE + 23, "PE23")
+#define SUNXI_PINCTRL_PIN_PE24 PINCTRL_PIN(PE_BASE + 24, "PE24")
+#define SUNXI_PINCTRL_PIN_PE25 PINCTRL_PIN(PE_BASE + 25, "PE25")
+#define SUNXI_PINCTRL_PIN_PE26 PINCTRL_PIN(PE_BASE + 26, "PE26")
+#define SUNXI_PINCTRL_PIN_PE27 PINCTRL_PIN(PE_BASE + 27, "PE27")
+#define SUNXI_PINCTRL_PIN_PE28 PINCTRL_PIN(PE_BASE + 28, "PE28")
+#define SUNXI_PINCTRL_PIN_PE29 PINCTRL_PIN(PE_BASE + 29, "PE29")
+#define SUNXI_PINCTRL_PIN_PE30 PINCTRL_PIN(PE_BASE + 30, "PE30")
+#define SUNXI_PINCTRL_PIN_PE31 PINCTRL_PIN(PE_BASE + 31, "PE31")
+
+#define SUNXI_PINCTRL_PIN_PF0  PINCTRL_PIN(PF_BASE + 0, "PF0")
+#define SUNXI_PINCTRL_PIN_PF1  PINCTRL_PIN(PF_BASE + 1, "PF1")
+#define SUNXI_PINCTRL_PIN_PF2  PINCTRL_PIN(PF_BASE + 2, "PF2")
+#define SUNXI_PINCTRL_PIN_PF3  PINCTRL_PIN(PF_BASE + 3, "PF3")
+#define SUNXI_PINCTRL_PIN_PF4  PINCTRL_PIN(PF_BASE + 4, "PF4")
+#define SUNXI_PINCTRL_PIN_PF5  PINCTRL_PIN(PF_BASE + 5, "PF5")
+#define SUNXI_PINCTRL_PIN_PF6  PINCTRL_PIN(PF_BASE + 6, "PF6")
+#define SUNXI_PINCTRL_PIN_PF7  PINCTRL_PIN(PF_BASE + 7, "PF7")
+#define SUNXI_PINCTRL_PIN_PF8  PINCTRL_PIN(PF_BASE + 8, "PF8")
+#define SUNXI_PINCTRL_PIN_PF9  PINCTRL_PIN(PF_BASE + 9, "PF9")
+#define SUNXI_PINCTRL_PIN_PF10 PINCTRL_PIN(PF_BASE + 10, "PF10")
+#define SUNXI_PINCTRL_PIN_PF11 PINCTRL_PIN(PF_BASE + 11, "PF11")
+#define SUNXI_PINCTRL_PIN_PF12 PINCTRL_PIN(PF_BASE + 12, "PF12")
+#define SUNXI_PINCTRL_PIN_PF13 PINCTRL_PIN(PF_BASE + 13, "PF13")
+#define SUNXI_PINCTRL_PIN_PF14 PINCTRL_PIN(PF_BASE + 14, "PF14")
+#define SUNXI_PINCTRL_PIN_PF15 PINCTRL_PIN(PF_BASE + 15, "PF15")
+#define SUNXI_PINCTRL_PIN_PF16 PINCTRL_PIN(PF_BASE + 16, "PF16")
+#define SUNXI_PINCTRL_PIN_PF17 PINCTRL_PIN(PF_BASE + 17, "PF17")
+#define SUNXI_PINCTRL_PIN_PF18 PINCTRL_PIN(PF_BASE + 18, "PF18")
+#define SUNXI_PINCTRL_PIN_PF19 PINCTRL_PIN(PF_BASE + 19, "PF19")
+#define SUNXI_PINCTRL_PIN_PF20 PINCTRL_PIN(PF_BASE + 20, "PF20")
+#define SUNXI_PINCTRL_PIN_PF21 PINCTRL_PIN(PF_BASE + 21, "PF21")
+#define SUNXI_PINCTRL_PIN_PF22 PINCTRL_PIN(PF_BASE + 22, "PF22")
+#define SUNXI_PINCTRL_PIN_PF23 PINCTRL_PIN(PF_BASE + 23, "PF23")
+#define SUNXI_PINCTRL_PIN_PF24 PINCTRL_PIN(PF_BASE + 24, "PF24")
+#define SUNXI_PINCTRL_PIN_PF25 PINCTRL_PIN(PF_BASE + 25, "PF25")
+#define SUNXI_PINCTRL_PIN_PF26 PINCTRL_PIN(PF_BASE + 26, "PF26")
+#define SUNXI_PINCTRL_PIN_PF27 PINCTRL_PIN(PF_BASE + 27, "PF27")
+#define SUNXI_PINCTRL_PIN_PF28 PINCTRL_PIN(PF_BASE + 28, "PF28")
+#define SUNXI_PINCTRL_PIN_PF29 PINCTRL_PIN(PF_BASE + 29, "PF29")
+#define SUNXI_PINCTRL_PIN_PF30 PINCTRL_PIN(PF_BASE + 30, "PF30")
+#define SUNXI_PINCTRL_PIN_PF31 PINCTRL_PIN(PF_BASE + 31, "PF31")
+
+#define SUNXI_PINCTRL_PIN_PG0  PINCTRL_PIN(PG_BASE + 0, "PG0")
+#define SUNXI_PINCTRL_PIN_PG1  PINCTRL_PIN(PG_BASE + 1, "PG1")
+#define SUNXI_PINCTRL_PIN_PG2  PINCTRL_PIN(PG_BASE + 2, "PG2")
+#define SUNXI_PINCTRL_PIN_PG3  PINCTRL_PIN(PG_BASE + 3, "PG3")
+#define SUNXI_PINCTRL_PIN_PG4  PINCTRL_PIN(PG_BASE + 4, "PG4")
+#define SUNXI_PINCTRL_PIN_PG5  PINCTRL_PIN(PG_BASE + 5, "PG5")
+#define SUNXI_PINCTRL_PIN_PG6  PINCTRL_PIN(PG_BASE + 6, "PG6")
+#define SUNXI_PINCTRL_PIN_PG7  PINCTRL_PIN(PG_BASE + 7, "PG7")
+#define SUNXI_PINCTRL_PIN_PG8  PINCTRL_PIN(PG_BASE + 8, "PG8")
+#define SUNXI_PINCTRL_PIN_PG9  PINCTRL_PIN(PG_BASE + 9, "PG9")
+#define SUNXI_PINCTRL_PIN_PG10 PINCTRL_PIN(PG_BASE + 10, "PG10")
+#define SUNXI_PINCTRL_PIN_PG11 PINCTRL_PIN(PG_BASE + 11, "PG11")
+#define SUNXI_PINCTRL_PIN_PG12 PINCTRL_PIN(PG_BASE + 12, "PG12")
+#define SUNXI_PINCTRL_PIN_PG13 PINCTRL_PIN(PG_BASE + 13, "PG13")
+#define SUNXI_PINCTRL_PIN_PG14 PINCTRL_PIN(PG_BASE + 14, "PG14")
+#define SUNXI_PINCTRL_PIN_PG15 PINCTRL_PIN(PG_BASE + 15, "PG15")
+#define SUNXI_PINCTRL_PIN_PG16 PINCTRL_PIN(PG_BASE + 16, "PG16")
+#define SUNXI_PINCTRL_PIN_PG17 PINCTRL_PIN(PG_BASE + 17, "PG17")
+#define SUNXI_PINCTRL_PIN_PG18 PINCTRL_PIN(PG_BASE + 18, "PG18")
+#define SUNXI_PINCTRL_PIN_PG19 PINCTRL_PIN(PG_BASE + 19, "PG19")
+#define SUNXI_PINCTRL_PIN_PG20 PINCTRL_PIN(PG_BASE + 20, "PG20")
+#define SUNXI_PINCTRL_PIN_PG21 PINCTRL_PIN(PG_BASE + 21, "PG21")
+#define SUNXI_PINCTRL_PIN_PG22 PINCTRL_PIN(PG_BASE + 22, "PG22")
+#define SUNXI_PINCTRL_PIN_PG23 PINCTRL_PIN(PG_BASE + 23, "PG23")
+#define SUNXI_PINCTRL_PIN_PG24 PINCTRL_PIN(PG_BASE + 24, "PG24")
+#define SUNXI_PINCTRL_PIN_PG25 PINCTRL_PIN(PG_BASE + 25, "PG25")
+#define SUNXI_PINCTRL_PIN_PG26 PINCTRL_PIN(PG_BASE + 26, "PG26")
+#define SUNXI_PINCTRL_PIN_PG27 PINCTRL_PIN(PG_BASE + 27, "PG27")
+#define SUNXI_PINCTRL_PIN_PG28 PINCTRL_PIN(PG_BASE + 28, "PG28")
+#define SUNXI_PINCTRL_PIN_PG29 PINCTRL_PIN(PG_BASE + 29, "PG29")
+#define SUNXI_PINCTRL_PIN_PG30 PINCTRL_PIN(PG_BASE + 30, "PG30")
+#define SUNXI_PINCTRL_PIN_PG31 PINCTRL_PIN(PG_BASE + 31, "PG31")
+
+#define SUNXI_PINCTRL_PIN_PH0  PINCTRL_PIN(PH_BASE + 0, "PH0")
+#define SUNXI_PINCTRL_PIN_PH1  PINCTRL_PIN(PH_BASE + 1, "PH1")
+#define SUNXI_PINCTRL_PIN_PH2  PINCTRL_PIN(PH_BASE + 2, "PH2")
+#define SUNXI_PINCTRL_PIN_PH3  PINCTRL_PIN(PH_BASE + 3, "PH3")
+#define SUNXI_PINCTRL_PIN_PH4  PINCTRL_PIN(PH_BASE + 4, "PH4")
+#define SUNXI_PINCTRL_PIN_PH5  PINCTRL_PIN(PH_BASE + 5, "PH5")
+#define SUNXI_PINCTRL_PIN_PH6  PINCTRL_PIN(PH_BASE + 6, "PH6")
+#define SUNXI_PINCTRL_PIN_PH7  PINCTRL_PIN(PH_BASE + 7, "PH7")
+#define SUNXI_PINCTRL_PIN_PH8  PINCTRL_PIN(PH_BASE + 8, "PH8")
+#define SUNXI_PINCTRL_PIN_PH9  PINCTRL_PIN(PH_BASE + 9, "PH9")
+#define SUNXI_PINCTRL_PIN_PH10 PINCTRL_PIN(PH_BASE + 10, "PH10")
+#define SUNXI_PINCTRL_PIN_PH11 PINCTRL_PIN(PH_BASE + 11, "PH11")
+#define SUNXI_PINCTRL_PIN_PH12 PINCTRL_PIN(PH_BASE + 12, "PH12")
+#define SUNXI_PINCTRL_PIN_PH13 PINCTRL_PIN(PH_BASE + 13, "PH13")
+#define SUNXI_PINCTRL_PIN_PH14 PINCTRL_PIN(PH_BASE + 14, "PH14")
+#define SUNXI_PINCTRL_PIN_PH15 PINCTRL_PIN(PH_BASE + 15, "PH15")
+#define SUNXI_PINCTRL_PIN_PH16 PINCTRL_PIN(PH_BASE + 16, "PH16")
+#define SUNXI_PINCTRL_PIN_PH17 PINCTRL_PIN(PH_BASE + 17, "PH17")
+#define SUNXI_PINCTRL_PIN_PH18 PINCTRL_PIN(PH_BASE + 18, "PH18")
+#define SUNXI_PINCTRL_PIN_PH19 PINCTRL_PIN(PH_BASE + 19, "PH19")
+#define SUNXI_PINCTRL_PIN_PH20 PINCTRL_PIN(PH_BASE + 20, "PH20")
+#define SUNXI_PINCTRL_PIN_PH21 PINCTRL_PIN(PH_BASE + 21, "PH21")
+#define SUNXI_PINCTRL_PIN_PH22 PINCTRL_PIN(PH_BASE + 22, "PH22")
+#define SUNXI_PINCTRL_PIN_PH23 PINCTRL_PIN(PH_BASE + 23, "PH23")
+#define SUNXI_PINCTRL_PIN_PH24 PINCTRL_PIN(PH_BASE + 24, "PH24")
+#define SUNXI_PINCTRL_PIN_PH25 PINCTRL_PIN(PH_BASE + 25, "PH25")
+#define SUNXI_PINCTRL_PIN_PH26 PINCTRL_PIN(PH_BASE + 26, "PH26")
+#define SUNXI_PINCTRL_PIN_PH27 PINCTRL_PIN(PH_BASE + 27, "PH27")
+#define SUNXI_PINCTRL_PIN_PH28 PINCTRL_PIN(PH_BASE + 28, "PH28")
+#define SUNXI_PINCTRL_PIN_PH29 PINCTRL_PIN(PH_BASE + 29, "PH29")
+#define SUNXI_PINCTRL_PIN_PH30 PINCTRL_PIN(PH_BASE + 30, "PH30")
+#define SUNXI_PINCTRL_PIN_PH31 PINCTRL_PIN(PH_BASE + 31, "PH31")
+
+#define SUNXI_PINCTRL_PIN_PI0  PINCTRL_PIN(PI_BASE + 0, "PI0")
+#define SUNXI_PINCTRL_PIN_PI1  PINCTRL_PIN(PI_BASE + 1, "PI1")
+#define SUNXI_PINCTRL_PIN_PI2  PINCTRL_PIN(PI_BASE + 2, "PI2")
+#define SUNXI_PINCTRL_PIN_PI3  PINCTRL_PIN(PI_BASE + 3, "PI3")
+#define SUNXI_PINCTRL_PIN_PI4  PINCTRL_PIN(PI_BASE + 4, "PI4")
+#define SUNXI_PINCTRL_PIN_PI5  PINCTRL_PIN(PI_BASE + 5, "PI5")
+#define SUNXI_PINCTRL_PIN_PI6  PINCTRL_PIN(PI_BASE + 6, "PI6")
+#define SUNXI_PINCTRL_PIN_PI7  PINCTRL_PIN(PI_BASE + 7, "PI7")
+#define SUNXI_PINCTRL_PIN_PI8  PINCTRL_PIN(PI_BASE + 8, "PI8")
+#define SUNXI_PINCTRL_PIN_PI9  PINCTRL_PIN(PI_BASE + 9, "PI9")
+#define SUNXI_PINCTRL_PIN_PI10 PINCTRL_PIN(PI_BASE + 10, "PI10")
+#define SUNXI_PINCTRL_PIN_PI11 PINCTRL_PIN(PI_BASE + 11, "PI11")
+#define SUNXI_PINCTRL_PIN_PI12 PINCTRL_PIN(PI_BASE + 12, "PI12")
+#define SUNXI_PINCTRL_PIN_PI13 PINCTRL_PIN(PI_BASE + 13, "PI13")
+#define SUNXI_PINCTRL_PIN_PI14 PINCTRL_PIN(PI_BASE + 14, "PI14")
+#define SUNXI_PINCTRL_PIN_PI15 PINCTRL_PIN(PI_BASE + 15, "PI15")
+#define SUNXI_PINCTRL_PIN_PI16 PINCTRL_PIN(PI_BASE + 16, "PI16")
+#define SUNXI_PINCTRL_PIN_PI17 PINCTRL_PIN(PI_BASE + 17, "PI17")
+#define SUNXI_PINCTRL_PIN_PI18 PINCTRL_PIN(PI_BASE + 18, "PI18")
+#define SUNXI_PINCTRL_PIN_PI19 PINCTRL_PIN(PI_BASE + 19, "PI19")
+#define SUNXI_PINCTRL_PIN_PI20 PINCTRL_PIN(PI_BASE + 20, "PI20")
+#define SUNXI_PINCTRL_PIN_PI21 PINCTRL_PIN(PI_BASE + 21, "PI21")
+#define SUNXI_PINCTRL_PIN_PI22 PINCTRL_PIN(PI_BASE + 22, "PI22")
+#define SUNXI_PINCTRL_PIN_PI23 PINCTRL_PIN(PI_BASE + 23, "PI23")
+#define SUNXI_PINCTRL_PIN_PI24 PINCTRL_PIN(PI_BASE + 24, "PI24")
+#define SUNXI_PINCTRL_PIN_PI25 PINCTRL_PIN(PI_BASE + 25, "PI25")
+#define SUNXI_PINCTRL_PIN_PI26 PINCTRL_PIN(PI_BASE + 26, "PI26")
+#define SUNXI_PINCTRL_PIN_PI27 PINCTRL_PIN(PI_BASE + 27, "PI27")
+#define SUNXI_PINCTRL_PIN_PI28 PINCTRL_PIN(PI_BASE + 28, "PI28")
+#define SUNXI_PINCTRL_PIN_PI29 PINCTRL_PIN(PI_BASE + 29, "PI29")
+#define SUNXI_PINCTRL_PIN_PI30 PINCTRL_PIN(PI_BASE + 30, "PI30")
+#define SUNXI_PINCTRL_PIN_PI31 PINCTRL_PIN(PI_BASE + 31, "PI31")
+
+#define SUNXI_PIN_NAME_MAX_LEN 5
+
+#define BANK_MEM_SIZE          0x24
+#define MUX_REGS_OFFSET                0x0
+#define DATA_REGS_OFFSET       0x10
+#define DLEVEL_REGS_OFFSET     0x14
+#define PULL_REGS_OFFSET       0x1c
+
+#define PINS_PER_BANK          32
+#define MUX_PINS_PER_REG       8
+#define MUX_PINS_BITS          4
+#define MUX_PINS_MASK          0x0f
+#define DATA_PINS_PER_REG      32
+#define DATA_PINS_BITS         1
+#define DATA_PINS_MASK         0x01
+#define DLEVEL_PINS_PER_REG    16
+#define DLEVEL_PINS_BITS       2
+#define DLEVEL_PINS_MASK       0x03
+#define PULL_PINS_PER_REG      16
+#define PULL_PINS_BITS         2
+#define PULL_PINS_MASK         0x03
+
+struct sunxi_desc_function {
+       const char      *name;
+       u8              muxval;
+};
+
+struct sunxi_desc_pin {
+       struct pinctrl_pin_desc         pin;
+       struct sunxi_desc_function      *functions;
+};
+
+struct sunxi_pinctrl_desc {
+       const struct sunxi_desc_pin     *pins;
+       int                             npins;
+       struct pinctrl_gpio_range       *ranges;
+       int                             nranges;
+};
+
+struct sunxi_pinctrl_function {
+       const char      *name;
+       const char      **groups;
+       unsigned        ngroups;
+};
+
+struct sunxi_pinctrl_group {