Merge branch 'hwmon-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jdelv...
authorLinus Torvalds <torvalds@linux-foundation.org>
Thu, 20 Dec 2012 15:07:18 +0000 (07:07 -0800)
committerLinus Torvalds <torvalds@linux-foundation.org>
Thu, 20 Dec 2012 15:07:18 +0000 (07:07 -0800)
Pull hwmon subsystem update from Jean Delvare:
 "There are many improvements to the it87 driver, as well as suspend
  support for the Winbond Super-I/O chips, and a few other fixes."

* 'hwmon-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jdelvare/staging:
  hwmon-vid: Add support for AMD family 11h to 15h processors
  hwmon: (it87) Support PECI for additional chips
  hwmon: (it87) Report thermal sensor type as Intel PECI if appropriate
  hwmon: (it87) Manage device specific features with table
  hwmon: (it87) Replace pwm group macro with direct attribute definitions
  hwmon: (it87) Avoid quoted string splits across lines
  hwmon: (it87) Save fan registers in 2-dimensional array
  hwmon: (it87) Introduce support for tempX_offset sysfs attribute
  hwmon: (it87) Replace macro defining tempX_type sensors with direct definitions
  hwmon: (it87) Save voltage register values in 2-dimensional array
  hwmon: (it87) Save temperature registers in 2-dimensional array
  hwmon: (w83627ehf) Get rid of smatch warnings
  hwmon: (w83627hf) Don't touch nonexistent I2C address registers
  hwmon: (w83627ehf) Add support for suspend
  hwmon: (w83627hf) Add support for suspend
  hwmon: Fix PCI device reference leak in quirk

351 files changed:
Documentation/ABI/testing/ima_policy
Documentation/devicetree/bindings/arm/davinci/nand.txt
Documentation/devicetree/bindings/mtd/denali-nand.txt [new file with mode: 0644]
Documentation/devicetree/bindings/mtd/flctl-nand.txt [new file with mode: 0644]
Documentation/devicetree/bindings/mtd/fsmc-nand.txt
Documentation/devicetree/bindings/mtd/m25p80.txt [new file with mode: 0644]
Documentation/devicetree/bindings/mtd/mtd-physmap.txt
Documentation/devicetree/bindings/pwm/pwm-tiecap.txt [new file with mode: 0644]
Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt [new file with mode: 0644]
Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt [new file with mode: 0644]
Documentation/devicetree/bindings/pwm/pwm.txt
Documentation/devicetree/bindings/pwm/spear-pwm.txt [new file with mode: 0644]
Documentation/devicetree/bindings/pwm/ti,twl-pwm.txt [new file with mode: 0644]
Documentation/devicetree/bindings/pwm/ti,twl-pwmled.txt [new file with mode: 0644]
Documentation/devicetree/bindings/pwm/vt8500-pwm.txt [new file with mode: 0644]
Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
Documentation/devicetree/bindings/spi/spi_atmel.txt [new file with mode: 0644]
Documentation/x86/boot.txt
Documentation/xtensa/atomctl.txt [new file with mode: 0644]
Makefile
arch/Kconfig
arch/arm/boot/dts/spear13xx.dtsi
arch/arm/boot/dts/spear300.dtsi
arch/arm/boot/dts/spear310.dtsi
arch/arm/boot/dts/spear320.dtsi
arch/arm/boot/dts/spear600.dtsi
arch/arm/configs/nhk8815_defconfig
arch/arm/include/uapi/asm/unistd.h
arch/arm/kernel/calls.S
arch/arm/mach-nomadik/board-nhk8815.c
arch/arm/mach-nomadik/include/mach/fsmc.h [deleted file]
arch/arm/mach-omap2/board-rx51-peripherals.c
arch/arm/mach-u300/core.c
arch/cris/kernel/module.c
arch/parisc/kernel/module.c
arch/powerpc/include/asm/systbl.h
arch/powerpc/include/asm/unistd.h
arch/powerpc/include/uapi/asm/unistd.h
arch/sparc/crypto/aes_asm.S
arch/sparc/crypto/aes_glue.c
arch/sparc/crypto/camellia_glue.c
arch/sparc/crypto/des_asm.S
arch/sparc/crypto/des_glue.c
arch/sparc/include/asm/hugetlb.h
arch/sparc/include/asm/pgtable_64.h
arch/sparc/kernel/module.c
arch/tile/kernel/module.c
arch/unicore32/kernel/module.c
arch/x86/kernel/cpu/proc.c
arch/x86/kernel/irqinit.c
arch/x86/kernel/traps.c
arch/x86/syscalls/syscall_32.tbl
arch/x86/syscalls/syscall_64.tbl
arch/xtensa/Kconfig
arch/xtensa/Kconfig.debug
arch/xtensa/Makefile
arch/xtensa/boot/Makefile
arch/xtensa/boot/boot-elf/Makefile
arch/xtensa/boot/boot-redboot/Makefile
arch/xtensa/boot/boot-uboot/Makefile [new file with mode: 0644]
arch/xtensa/boot/dts/lx60.dts [new file with mode: 0644]
arch/xtensa/boot/dts/ml605.dts [new file with mode: 0644]
arch/xtensa/boot/dts/xtfpga-flash-16m.dtsi [new file with mode: 0644]
arch/xtensa/boot/dts/xtfpga-flash-4m.dtsi [new file with mode: 0644]
arch/xtensa/boot/dts/xtfpga.dtsi [new file with mode: 0644]
arch/xtensa/include/asm/atomic.h
arch/xtensa/include/asm/barrier.h
arch/xtensa/include/asm/bitops.h
arch/xtensa/include/asm/bootparam.h
arch/xtensa/include/asm/cacheasm.h
arch/xtensa/include/asm/cacheflush.h
arch/xtensa/include/asm/checksum.h
arch/xtensa/include/asm/cmpxchg.h
arch/xtensa/include/asm/current.h
arch/xtensa/include/asm/delay.h
arch/xtensa/include/asm/dma-mapping.h
arch/xtensa/include/asm/elf.h
arch/xtensa/include/asm/highmem.h
arch/xtensa/include/asm/initialize_mmu.h [new file with mode: 0644]
arch/xtensa/include/asm/mmu_context.h
arch/xtensa/include/asm/nommu_context.h
arch/xtensa/include/asm/page.h
arch/xtensa/include/asm/pci-bridge.h
arch/xtensa/include/asm/pci.h
arch/xtensa/include/asm/pgalloc.h
arch/xtensa/include/asm/pgtable.h
arch/xtensa/include/asm/platform.h
arch/xtensa/include/asm/processor.h
arch/xtensa/include/asm/prom.h [new file with mode: 0644]
arch/xtensa/include/asm/ptrace.h
arch/xtensa/include/asm/regs.h
arch/xtensa/include/asm/spinlock.h
arch/xtensa/include/asm/syscall.h
arch/xtensa/include/asm/traps.h [new file with mode: 0644]
arch/xtensa/include/asm/uaccess.h
arch/xtensa/kernel/Makefile
arch/xtensa/kernel/align.S
arch/xtensa/kernel/asm-offsets.c
arch/xtensa/kernel/coprocessor.S
arch/xtensa/kernel/entry.S
arch/xtensa/kernel/head.S
arch/xtensa/kernel/irq.c
arch/xtensa/kernel/module.c
arch/xtensa/kernel/platform.c
arch/xtensa/kernel/process.c
arch/xtensa/kernel/ptrace.c
arch/xtensa/kernel/setup.c
arch/xtensa/kernel/signal.c
arch/xtensa/kernel/syscall.c
arch/xtensa/kernel/time.c
arch/xtensa/kernel/traps.c
arch/xtensa/kernel/vectors.S
arch/xtensa/lib/checksum.S
arch/xtensa/lib/memcopy.S
arch/xtensa/lib/pci-auto.c
arch/xtensa/lib/strncpy_user.S
arch/xtensa/lib/strnlen_user.S
arch/xtensa/lib/usercopy.S
arch/xtensa/mm/cache.c
arch/xtensa/mm/fault.c
arch/xtensa/mm/init.c
arch/xtensa/mm/misc.S
arch/xtensa/mm/mmu.c
arch/xtensa/mm/tlb.c
arch/xtensa/platforms/iss/include/platform/serial.h
arch/xtensa/platforms/iss/include/platform/simcall.h
arch/xtensa/platforms/xtfpga/Makefile [new file with mode: 0644]
arch/xtensa/platforms/xtfpga/include/platform/hardware.h [new file with mode: 0644]
arch/xtensa/platforms/xtfpga/include/platform/lcd.h [new file with mode: 0644]
arch/xtensa/platforms/xtfpga/include/platform/serial.h [new file with mode: 0644]
arch/xtensa/platforms/xtfpga/lcd.c [new file with mode: 0644]
arch/xtensa/platforms/xtfpga/setup.c [new file with mode: 0644]
arch/xtensa/variants/s6000/gpio.c
drivers/atm/solos-pci.c
drivers/bcma/driver_chipcommon_pmu.c
drivers/char/random.c
drivers/clk/clk-nomadik.c
drivers/gpio/Kconfig
drivers/gpio/gpio-ich.c
drivers/gpio/gpio-mvebu.c
drivers/gpu/drm/ttm/ttm_bo.c
drivers/input/serio/i8042-x86ia64io.h
drivers/isdn/mISDN/dsp_core.c
drivers/mtd/ar7part.c
drivers/mtd/bcm63xxpart.c
drivers/mtd/chips/cfi_cmdset_0002.c
drivers/mtd/cmdlinepart.c
drivers/mtd/devices/bcm47xxsflash.c
drivers/mtd/devices/block2mtd.c
drivers/mtd/devices/docg3.c
drivers/mtd/devices/docprobe.c
drivers/mtd/devices/m25p80.c
drivers/mtd/devices/mtd_dataflash.c
drivers/mtd/devices/spear_smi.c
drivers/mtd/devices/sst25l.c
drivers/mtd/maps/Kconfig
drivers/mtd/maps/Makefile
drivers/mtd/maps/amd76xrom.c
drivers/mtd/maps/autcpu12-nvram.c
drivers/mtd/maps/bfin-async-flash.c
drivers/mtd/maps/ck804xrom.c
drivers/mtd/maps/esb2rom.c
drivers/mtd/maps/fortunet.c [deleted file]
drivers/mtd/maps/gpio-addr-flash.c
drivers/mtd/maps/ichxrom.c
drivers/mtd/maps/intel_vr_nor.c
drivers/mtd/maps/lantiq-flash.c
drivers/mtd/maps/latch-addr-flash.c
drivers/mtd/maps/pci.c
drivers/mtd/maps/physmap_of.c
drivers/mtd/maps/pismo.c
drivers/mtd/maps/pxa2xx-flash.c
drivers/mtd/maps/sa1100-flash.c
drivers/mtd/maps/scb2_flash.c
drivers/mtd/maps/sun_uflash.c
drivers/mtd/maps/vmu-flash.c
drivers/mtd/mtd_blkdevs.c
drivers/mtd/mtdoops.c
drivers/mtd/nand/Kconfig
drivers/mtd/nand/Makefile
drivers/mtd/nand/ams-delta.c
drivers/mtd/nand/atmel_nand.c
drivers/mtd/nand/au1550nd.c
drivers/mtd/nand/bcm47xxnflash/Makefile [new file with mode: 0644]
drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h [new file with mode: 0644]
drivers/mtd/nand/bcm47xxnflash/main.c [new file with mode: 0644]
drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c [new file with mode: 0644]
drivers/mtd/nand/bf5xx_nand.c
drivers/mtd/nand/cafe_nand.c
drivers/mtd/nand/cs553x_nand.c
drivers/mtd/nand/davinci_nand.c
drivers/mtd/nand/denali.c
drivers/mtd/nand/denali.h
drivers/mtd/nand/denali_dt.c [new file with mode: 0644]
drivers/mtd/nand/denali_pci.c [new file with mode: 0644]
drivers/mtd/nand/diskonchip.c
drivers/mtd/nand/docg4.c
drivers/mtd/nand/fsl_elbc_nand.c
drivers/mtd/nand/fsl_ifc_nand.c
drivers/mtd/nand/fsl_upm.c
drivers/mtd/nand/fsmc_nand.c
drivers/mtd/nand/gpio.c
drivers/mtd/nand/gpmi-nand/gpmi-lib.c
drivers/mtd/nand/gpmi-nand/gpmi-nand.c
drivers/mtd/nand/gpmi-nand/gpmi-nand.h
drivers/mtd/nand/jz4740_nand.c
drivers/mtd/nand/lpc32xx_mlc.c
drivers/mtd/nand/lpc32xx_slc.c
drivers/mtd/nand/mpc5121_nfc.c
drivers/mtd/nand/mxc_nand.c
drivers/mtd/nand/nand_base.c
drivers/mtd/nand/nandsim.c
drivers/mtd/nand/ndfc.c
drivers/mtd/nand/nomadik_nand.c [deleted file]
drivers/mtd/nand/nuc900_nand.c
drivers/mtd/nand/omap2.c
drivers/mtd/nand/orion_nand.c
drivers/mtd/nand/pasemi_nand.c
drivers/mtd/nand/plat_nand.c
drivers/mtd/nand/s3c2410.c
drivers/mtd/nand/sh_flctl.c
drivers/mtd/nand/sharpsl.c
drivers/mtd/nand/socrates_nand.c
drivers/mtd/ofpart.c
drivers/mtd/onenand/generic.c
drivers/mtd/onenand/omap2.c
drivers/mtd/onenand/samsung.c
drivers/mtd/tests/mtd_nandbiterrs.c
drivers/mtd/tests/mtd_nandecctest.c
drivers/mtd/tests/mtd_oobtest.c
drivers/mtd/tests/mtd_pagetest.c
drivers/mtd/tests/mtd_readtest.c
drivers/mtd/tests/mtd_speedtest.c
drivers/mtd/tests/mtd_stresstest.c
drivers/mtd/tests/mtd_subpagetest.c
drivers/mtd/tests/mtd_torturetest.c
drivers/net/bonding/bond_main.c
drivers/net/can/sja1000/sja1000_of_platform.c
drivers/net/ethernet/emulex/benet/be.h
drivers/net/ethernet/emulex/benet/be_cmds.c
drivers/net/ethernet/emulex/benet/be_main.c
drivers/net/ethernet/freescale/Kconfig
drivers/net/ethernet/micrel/ksz884x.c
drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c
drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c
drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c
drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c
drivers/net/ethernet/realtek/8139cp.c
drivers/net/ethernet/smsc/smc91x.c
drivers/net/ethernet/smsc/smsc911x.c
drivers/net/ethernet/stmicro/stmmac/stmmac.h
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
drivers/net/ethernet/ti/cpts.c
drivers/net/tun.c
drivers/net/usb/cdc_ether.c
drivers/net/usb/cdc_ncm.c
drivers/net/usb/qmi_wwan.c
drivers/net/usb/usbnet.c
drivers/net/wimax/i2400m/i2400m-usb.h
drivers/net/wimax/i2400m/usb.c
drivers/net/wireless/Makefile
drivers/net/wireless/rt2x00/rt2x00dev.c
drivers/of/base.c
drivers/power/charger-manager.c
drivers/pwm/Kconfig
drivers/pwm/Makefile
drivers/pwm/core.c
drivers/pwm/pwm-imx.c
drivers/pwm/pwm-lpc32xx.c
drivers/pwm/pwm-samsung.c
drivers/pwm/pwm-spear.c [new file with mode: 0644]
drivers/pwm/pwm-tiecap.c
drivers/pwm/pwm-tiehrpwm.c
drivers/pwm/pwm-tipwmss.c [new file with mode: 0644]
drivers/pwm/pwm-tipwmss.h [new file with mode: 0644]
drivers/pwm/pwm-twl-led.c [new file with mode: 0644]
drivers/pwm/pwm-twl.c [new file with mode: 0644]
drivers/pwm/pwm-twl6030.c [deleted file]
drivers/pwm/pwm-vt8500.c
drivers/spi/spi-atmel.c
drivers/spi/spi-s3c64xx.c
drivers/spi/spi-sh-hspi.c
drivers/spi/spi.c
fs/jffs2/nodemgmt.c
include/linux/asn1.h
include/linux/bcma/bcma.h
include/linux/blkdev.h
include/linux/compiler-gcc4.h
include/linux/compiler-intel.h
include/linux/compiler.h
include/linux/ima.h
include/linux/moduleparam.h
include/linux/mtd/blktrans.h
include/linux/mtd/doc2000.h
include/linux/mtd/fsmc.h
include/linux/mtd/gpmi-nand.h [deleted file]
include/linux/mtd/map.h
include/linux/mtd/mtd.h
include/linux/mtd/nand.h
include/linux/mtd/sh_flctl.h
include/linux/of_platform.h
include/linux/platform_data/mtd-nomadik-nand.h [deleted file]
include/linux/pwm.h
include/linux/security.h
include/linux/syscalls.h
include/linux/usb/usbnet.h
include/net/inet_connection_sock.h
include/net/ndisc.h
include/uapi/asm-generic/unistd.h
include/uapi/linux/if_bridge.h
include/uapi/linux/module.h [new file with mode: 0644]
include/uapi/linux/swab.h
kernel/Makefile
kernel/modsign_certificate.S [new file with mode: 0644]
kernel/modsign_pubkey.c
kernel/module.c
kernel/posix-cpu-timers.c
kernel/sched/fair.c
kernel/sys_ni.c
kernel/watchdog.c
lib/asn1_decoder.c
mm/ksm.c
mm/vmscan.c
net/atm/atm_sysfs.c
net/bridge/br_mdb.c
net/bridge/br_multicast.c
net/bridge/br_netlink.c
net/bridge/br_private.h
net/dccp/ipv4.c
net/dccp/ipv6.c
net/ipv4/inet_connection_sock.c
net/ipv4/tcp_ipv4.c
net/ipv6/Makefile
net/ipv6/addrconf.c
net/ipv6/ndisc.c
net/ipv6/tcp_ipv6.c
net/mac802154/ieee802154_dev.c
net/netlink/af_netlink.c
net/sctp/Kconfig
net/sctp/probe.c
net/sctp/protocol.c
scripts/Makefile.modsign [new file with mode: 0644]
security/capability.c
security/integrity/ima/ima.h
security/integrity/ima/ima_api.c
security/integrity/ima/ima_main.c
security/integrity/ima/ima_policy.c
security/security.c
security/selinux/nlmsgtab.c

index 986946613542b4bc1852aaf671e62059d3295cea..ec0a38ef3145e30a90ace37c391d0eba33c81bc7 100644 (file)
@@ -23,7 +23,7 @@ Description:
                        lsm:    [[subj_user=] [subj_role=] [subj_type=]
                                 [obj_user=] [obj_role=] [obj_type=]]
 
-               base:   func:= [BPRM_CHECK][FILE_MMAP][FILE_CHECK]
+               base:   func:= [BPRM_CHECK][FILE_MMAP][FILE_CHECK][MODULE_CHECK]
                        mask:= [MAY_READ] [MAY_WRITE] [MAY_APPEND] [MAY_EXEC]
                        fsmagic:= hex value
                        uid:= decimal value
@@ -53,6 +53,7 @@ Description:
                        measure func=BPRM_CHECK
                        measure func=FILE_MMAP mask=MAY_EXEC
                        measure func=FILE_CHECK mask=MAY_READ uid=0
+                       measure func=MODULE_CHECK uid=0
                        appraise fowner=0
 
                The default policy measures all executables in bprm_check,
index 49fc7ada929a4aec87a615031b948d65c251f0d2..3545ea704b50cbabaff63ff35bcf12048ac9e7c7 100644 (file)
@@ -23,6 +23,9 @@ Recommended properties :
 - ti,davinci-nand-buswidth: buswidth 8 or 16
 - ti,davinci-nand-use-bbt: use flash based bad block table support.
 
+nand device bindings may contain additional sub-nodes describing
+partitions of the address space. See partition.txt for more detail.
+
 Example(da850 EVM ):
 nand_cs3@62000000 {
        compatible = "ti,davinci-nand";
@@ -35,4 +38,9 @@ nand_cs3@62000000 {
        ti,davinci-ecc-mode = "hw";
        ti,davinci-ecc-bits = <4>;
        ti,davinci-nand-use-bbt;
+
+       partition@180000 {
+               label = "ubifs";
+               reg = <0x180000 0x7e80000>;
+       };
 };
diff --git a/Documentation/devicetree/bindings/mtd/denali-nand.txt b/Documentation/devicetree/bindings/mtd/denali-nand.txt
new file mode 100644 (file)
index 0000000..b04d03a
--- /dev/null
@@ -0,0 +1,23 @@
+* Denali NAND controller
+
+Required properties:
+  - compatible : should be "denali,denali-nand-dt"
+  - reg : should contain registers location and length for data and reg.
+  - reg-names: Should contain the reg names "nand_data" and "denali_reg"
+  - interrupts : The interrupt number.
+  - dm-mask : DMA bit mask
+
+The device tree may optionally contain sub-nodes describing partitions of the
+address space. See partition.txt for more detail.
+
+Examples:
+
+nand: nand@ff900000 {
+       #address-cells = <1>;
+       #size-cells = <1>;
+       compatible = "denali,denali-nand-dt";
+       reg = <0xff900000 0x100000>, <0xffb80000 0x10000>;
+       reg-names = "nand_data", "denali_reg";
+       interrupts = <0 144 4>;
+       dma-mask = <0xffffffff>;
+};
diff --git a/Documentation/devicetree/bindings/mtd/flctl-nand.txt b/Documentation/devicetree/bindings/mtd/flctl-nand.txt
new file mode 100644 (file)
index 0000000..427f46d
--- /dev/null
@@ -0,0 +1,49 @@
+FLCTL NAND controller
+
+Required properties:
+- compatible : "renesas,shmobile-flctl-sh7372"
+- reg : Address range of the FLCTL
+- interrupts : flste IRQ number
+- nand-bus-width : bus width to NAND chip
+
+Optional properties:
+- dmas: DMA specifier(s)
+- dma-names: name for each DMA specifier. Valid names are
+            "data_tx", "data_rx", "ecc_tx", "ecc_rx"
+
+The DMA fields are not used yet in the driver but are listed here for
+completing the bindings.
+
+The device tree may optionally contain sub-nodes describing partitions of the
+address space. See partition.txt for more detail.
+
+Example:
+
+       flctl@e6a30000 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "renesas,shmobile-flctl-sh7372";
+               reg = <0xe6a30000 0x100>;
+               interrupts = <0x0d80>;
+
+               nand-bus-width = <16>;
+
+               dmas = <&dmac 1 /* data_tx */
+                       &dmac 2;> /* data_rx */
+               dma-names = "data_tx", "data_rx";
+
+               system@0 {
+                       label = "system";
+                       reg = <0x0 0x8000000>;
+               };
+
+               userdata@8000000 {
+                       label = "userdata";
+                       reg = <0x8000000 0x10000000>;
+               };
+
+               cache@18000000 {
+                       label = "cache";
+                       reg = <0x18000000 0x8000000>;
+               };
+       };
index e2c663b354d2ae2f241e5739d9cf2b6e67b23e37..e3ea32e7de3e763bae2aa515375ee8ea8ccd5efd 100644 (file)
@@ -3,9 +3,7 @@
 Required properties:
 - compatible : "st,spear600-fsmc-nand"
 - reg : Address range of the mtd chip
-- reg-names: Should contain the reg names "fsmc_regs" and "nand_data"
-- st,ale-off : Chip specific offset to ALE
-- st,cle-off : Chip specific offset to CLE
+- reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd"
 
 Optional properties:
 - bank-width : Width (in bytes) of the device.  If not present, the width
@@ -19,10 +17,10 @@ Example:
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0xd1800000 0x1000        /* FSMC Register */
-                      0xd2000000 0x4000>;      /* NAND Base */
-               reg-names = "fsmc_regs", "nand_data";
-               st,ale-off = <0x20000>;
-               st,cle-off = <0x10000>;
+                      0xd2000000 0x0010        /* NAND Base DATA */
+                      0xd2020000 0x0010        /* NAND Base ADDR */
+                      0xd2010000 0x0010>;      /* NAND Base CMD */
+               reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
 
                bank-width = <1>;
                nand-skip-bbtscan;
diff --git a/Documentation/devicetree/bindings/mtd/m25p80.txt b/Documentation/devicetree/bindings/mtd/m25p80.txt
new file mode 100644 (file)
index 0000000..6d3d576
--- /dev/null
@@ -0,0 +1,29 @@
+* MTD SPI driver for ST M25Pxx (and similar) serial flash chips
+
+Required properties:
+- #address-cells, #size-cells : Must be present if the device has sub-nodes
+  representing partitions.
+- compatible : Should be the manufacturer and the name of the chip. Bear in mind
+               the DT binding is not Linux-only, but in case of Linux, see the
+               "m25p_ids" table in drivers/mtd/devices/m25p80.c for the list of
+               supported chips.
+- reg : Chip-Select number
+- spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at
+
+Optional properties:
+- m25p,fast-read : Use the "fast read" opcode to read data from the chip instead
+                   of the usual "read" opcode. This opcode is not supported by
+                   all chips and support for it can not be detected at runtime.
+                   Refer to your chips' datasheet to check if this is supported
+                   by your chip.
+
+Example:
+
+       flash: m25p80@0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "spansion,m25p80";
+               reg = <0>;
+               spi-max-frequency = <40000000>;
+               m25p,fast-read;
+       };
index 94de19b8f16bcd548e2e1163704b9fc3ae2ce31f..dab7847fc800accd94916d42ea58b57d907343bc 100644 (file)
@@ -23,6 +23,9 @@ file systems on embedded devices.
    unaligned accesses as implemented in the JFFS2 code via memcpy().
    By defining "no-unaligned-direct-access", the flash will not be
    exposed directly to the MTD users (e.g. JFFS2) any more.
+ - linux,mtd-name: allow to specify the mtd name for retro capability with
+   physmap-flash drivers as boot loader pass the mtd partition via the old
+   device name physmap-flash.
 
 For JEDEC compatible devices, the following additional properties
 are defined:
diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt
new file mode 100644 (file)
index 0000000..131e8c1
--- /dev/null
@@ -0,0 +1,23 @@
+TI SOC ECAP based APWM controller
+
+Required properties:
+- compatible: Must be "ti,am33xx-ecap"
+- #pwm-cells: Should be 3. Number of cells being used to specify PWM property.
+  First cell specifies the per-chip index of the PWM to use, the second
+  cell is the period in nanoseconds and bit 0 in the third cell is used to
+  encode the polarity of PWM output. Set bit 0 of the third in PWM specifier
+  to 1 for inverse polarity & set to 0 for normal polarity.
+- reg: physical base address and size of the registers map.
+
+Optional properties:
+- ti,hwmods: Name of the hwmod associated to the ECAP:
+  "ecap<x>", <x> being the 0-based instance number from the HW spec
+
+Example:
+
+ecap0: ecap@0 {
+       compatible = "ti,am33xx-ecap";
+       #pwm-cells = <3>;
+       reg = <0x48300100 0x80>;
+       ti,hwmods = "ecap0";
+};
diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt
new file mode 100644 (file)
index 0000000..4fc7079
--- /dev/null
@@ -0,0 +1,23 @@
+TI SOC EHRPWM based PWM controller
+
+Required properties:
+- compatible : Must be "ti,am33xx-ehrpwm"
+- #pwm-cells: Should be 3. Number of cells being used to specify PWM property.
+  First cell specifies the per-chip index of the PWM to use, the second
+  cell is the period in nanoseconds and bit 0 in the third cell is used to
+  encode the polarity of PWM output. Set bit 0 of the third in PWM specifier
+  to 1 for inverse polarity & set to 0 for normal polarity.
+- reg: physical base address and size of the registers map.
+
+Optional properties:
+- ti,hwmods: Name of the hwmod associated to the EHRPWM:
+  "ehrpwm<x>", <x> being the 0-based instance number from the HW spec
+
+Example:
+
+ehrpwm0: ehrpwm@0 {
+       compatible = "ti,am33xx-ehrpwm";
+       #pwm-cells = <3>;
+       reg = <0x48300200 0x100>;
+       ti,hwmods = "ehrpwm0";
+};
diff --git a/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt b/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt
new file mode 100644 (file)
index 0000000..f7eae77
--- /dev/null
@@ -0,0 +1,31 @@
+TI SOC based PWM Subsystem
+
+Required properties:
+- compatible: Must be "ti,am33xx-pwmss";
+- reg: physical base address and size of the registers map.
+- address-cells: Specify the number of u32 entries needed in child nodes.
+                 Should set to 1.
+- size-cells: specify number of u32 entries needed to specify child nodes size
+               in reg property. Should set to 1.
+- ranges: describes the address mapping of a memory-mapped bus. Should set to
+          physical address map of child's base address, physical address within
+          parent's address  space and length of the address map. For am33xx,
+          3 set of child register maps present, ECAP register space, EQEP
+          register space, EHRPWM register space.
+
+Also child nodes should also populated under PWMSS DT node.
+
+Example:
+pwmss0: pwmss@48300000 {
+       compatible = "ti,am33xx-pwmss";
+       reg = <0x48300000 0x10>;
+       ti,hwmods = "epwmss0";
+       #address-cells = <1>;
+       #size-cells = <1>;
+       status = "disabled";
+       ranges = <0x48300100 0x48300100 0x80   /* ECAP */
+                 0x48300180 0x48300180 0x80   /* EQEP */
+                 0x48300200 0x48300200 0x80>; /* EHRPWM */
+
+       /* child nodes go here */
+};
index 73ec962bfe8cfb4911c00b296bd741b74ccd6ffa..06e67247859aa7eef3bc253d11cf6f18ca810680 100644 (file)
@@ -37,10 +37,21 @@ device:
                pwm-names = "backlight";
        };
 
+Note that in the example above, specifying the "pwm-names" is redundant
+because the name "backlight" would be used as fallback anyway.
+
 pwm-specifier typically encodes the chip-relative PWM number and the PWM
-period in nanoseconds. Note that in the example above, specifying the
-"pwm-names" is redundant because the name "backlight" would be used as
-fallback anyway.
+period in nanoseconds.
+
+Optionally, the pwm-specifier can encode a number of flags in a third cell:
+- bit 0: PWM signal polarity (0: normal polarity, 1: inverse polarity)
+
+Example with optional PWM specifier for inverse polarity
+
+       bl: backlight {
+               pwms = <&pwm 0 5000000 1>;
+               pwm-names = "backlight";
+       };
 
 2) PWM controller nodes
 -----------------------
diff --git a/Documentation/devicetree/bindings/pwm/spear-pwm.txt b/Documentation/devicetree/bindings/pwm/spear-pwm.txt
new file mode 100644 (file)
index 0000000..3ac779d
--- /dev/null
@@ -0,0 +1,18 @@
+== ST SPEAr SoC PWM controller ==
+
+Required properties:
+- compatible: should be one of:
+  - "st,spear320-pwm"
+  - "st,spear1340-pwm"
+- reg: physical base address and length of the controller's registers
+- #pwm-cells: number of cells used to specify PWM which is fixed to 2 on
+  SPEAr. The first cell specifies the per-chip index of the PWM to use and
+  the second cell is the period in nanoseconds.
+
+Example:
+
+        pwm: pwm@a8000000 {
+            compatible ="st,spear320-pwm";
+            reg = <0xa8000000 0x1000>;
+            #pwm-cells = <2>;
+        };
diff --git a/Documentation/devicetree/bindings/pwm/ti,twl-pwm.txt b/Documentation/devicetree/bindings/pwm/ti,twl-pwm.txt
new file mode 100644 (file)
index 0000000..2943ee5
--- /dev/null
@@ -0,0 +1,17 @@
+Texas Instruments TWL series PWM drivers
+
+Supported PWMs:
+On TWL4030 series: PWM1 and PWM2
+On TWL6030 series: PWM0 and PWM1
+
+Required properties:
+- compatible: "ti,twl4030-pwm" or "ti,twl6030-pwm"
+- #pwm-cells: should be 2.  The first cell specifies the per-chip index
+  of the PWM to use and the second cell is the period in nanoseconds.
+
+Example:
+
+twl_pwm: pwm {
+       compatible = "ti,twl6030-pwm";
+       #pwm-cells = <2>;
+};
diff --git a/Documentation/devicetree/bindings/pwm/ti,twl-pwmled.txt b/Documentation/devicetree/bindings/pwm/ti,twl-pwmled.txt
new file mode 100644 (file)
index 0000000..cb64f3a
--- /dev/null
@@ -0,0 +1,17 @@
+Texas Instruments TWL series PWM drivers connected to LED terminals
+
+Supported PWMs:
+On TWL4030 series: PWMA and PWMB (connected to LEDA and LEDB terminals)
+On TWL6030 series: LED PWM (mainly used as charging indicator LED)
+
+Required properties:
+- compatible: "ti,twl4030-pwmled" or "ti,twl6030-pwmled"
+- #pwm-cells: should be 2.  The first cell specifies the per-chip index
+  of the PWM to use and the second cell is the period in nanoseconds.
+
+Example:
+
+twl_pwmled: pwmled {
+       compatible = "ti,twl6030-pwmled";
+       #pwm-cells = <2>;
+};
diff --git a/Documentation/devicetree/bindings/pwm/vt8500-pwm.txt b/Documentation/devicetree/bindings/pwm/vt8500-pwm.txt
new file mode 100644 (file)
index 0000000..bcc6367
--- /dev/null
@@ -0,0 +1,17 @@
+VIA/Wondermedia VT8500/WM8xxx series SoC PWM controller
+
+Required properties:
+- compatible: should be "via,vt8500-pwm"
+- reg: physical base address and length of the controller's registers
+- #pwm-cells: should be 2.  The first cell specifies the per-chip index
+  of the PWM to use and the second cell is the period in nanoseconds.
+- clocks: phandle to the PWM source clock
+
+Example:
+
+pwm1: pwm@d8220000 {
+       #pwm-cells = <2>;
+       compatible = "via,vt8500-pwm";
+       reg = <0xd8220000 0x1000>;
+       clocks = <&clkpwm>;
+};
index 8cf24f6f0a99938a2c13e62e1131beb38de9101d..7b53da5cb75b9d24e11652f15bd15d11e67d6ada 100644 (file)
@@ -13,7 +13,7 @@ Recommended properties:
 
 Example:
 
-spi@7000d600 {
+spi@7000c380 {
        compatible = "nvidia,tegra20-sflash";
        reg = <0x7000c380 0x80>;
        interrupts = <0 39 0x04>;
index f5b1ad1a1ec31a859f9a14bfe3e654649fced676..eefe15e3d95e8f3cc9a8ff2885ec494563d488cd 100644 (file)
@@ -13,7 +13,7 @@ Recommended properties:
 
 Example:
 
-slink@7000d600 {
+spi@7000d600 {
        compatible = "nvidia,tegra20-slink";
        reg = <0x7000d600 0x200>;
        interrupts = <0 82 0x04>;
diff --git a/Documentation/devicetree/bindings/spi/spi_atmel.txt b/Documentation/devicetree/bindings/spi/spi_atmel.txt
new file mode 100644 (file)
index 0000000..07e04cd
--- /dev/null
@@ -0,0 +1,26 @@
+Atmel SPI device
+
+Required properties:
+- compatible : should be "atmel,at91rm9200-spi".
+- reg: Address and length of the register set for the device
+- interrupts: Should contain spi interrupt
+- cs-gpios: chipselects
+
+Example:
+
+spi1: spi@fffcc000 {
+       compatible = "atmel,at91rm9200-spi";
+       reg = <0xfffcc000 0x4000>;
+       interrupts = <13 4 5>;
+       #address-cells = <1>;
+       #size-cells = <0>;
+       cs-gpios = <&pioB 3 0>;
+       status = "okay";
+
+       mmc-slot@0 {
+               compatible = "mmc-spi-slot";
+               reg = <0>;
+               gpios = <&pioC 4 0>;    /* CD */
+               spi-max-frequency = <25000000>;
+       };
+};
index f15cb74c4f783263bba9917ec3f73755f23e09e4..406d82d5d2bb1e08a8cb9e4c548ce937f448b376 100644 (file)
@@ -373,7 +373,7 @@ Protocol:   2.00+
        1  Loadlin
        2  bootsect-loader      (0x20, all other values reserved)
        3  Syslinux
-       4  Etherboot/gPXE
+       4  Etherboot/gPXE/iPXE
        5  ELILO
        7  GRUB
        8  U-Boot
@@ -381,6 +381,7 @@ Protocol:   2.00+
        A  Gujin
        B  Qemu
        C  Arcturus Networks uCbootloader
+       D  kexec-tools
        E  Extended             (see ext_loader_type)
        F  Special              (0xFF = undefined)
        10  Reserved
diff --git a/Documentation/xtensa/atomctl.txt b/Documentation/xtensa/atomctl.txt
new file mode 100644 (file)
index 0000000..10a8d1f
--- /dev/null
@@ -0,0 +1,44 @@
+We Have Atomic Operation Control (ATOMCTL) Register.
+This register determines the effect of using a S32C1I instruction
+with various combinations of:
+
+     1. With and without an Coherent Cache Controller which
+        can do Atomic Transactions to the memory internally.
+
+     2. With and without An Intelligent Memory Controller which
+        can do Atomic Transactions itself.
+
+The Core comes up with a default value of for the three types of cache ops:
+
+      0x28: (WB: Internal, WT: Internal, BY:Exception)
+
+On the FPGA Cards we typically simulate an Intelligent Memory controller
+which can implement  RCW transactions. For FPGA cards with an External
+Memory controller we let it to the atomic operations internally while
+doing a Cached (WB) transaction and use the Memory RCW for un-cached
+operations.
+
+For systems without an coherent cache controller, non-MX, we always
+use the memory controllers RCW, thought non-MX controlers likely
+support the Internal Operation.
+
+CUSTOMER-WARNING:
+   Virtually all customers buy their memory controllers from vendors that
+   don't support atomic RCW memory transactions and will likely want to
+   configure this register to not use RCW.
+
+Developers might find using RCW in Bypass mode convenient when testing
+with the cache being bypassed; for example studying cache alias problems.
+
+See Section 4.3.12.4 of ISA; Bits:
+
+                             WB     WT      BY
+                           5   4 | 3   2 | 1   0
+  2 Bit
+  Field
+  Values     WB - Write Back         WT - Write Thru         BY - Bypass
+---------    ---------------         -----------------     ----------------
+    0        Exception               Exception               Exception
+    1        RCW Transaction         RCW Transaction         RCW Transaction
+    2        Internal Operation      Exception               Reserved
+    3        Reserved                Reserved                Reserved
index 540f7b240c77d7332f7c51746de660a709e6c431..6f07f4a28b479e01ef73371537794974e2ec4824 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -981,6 +981,12 @@ _modinst_post: _modinst_
        $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.fwinst obj=firmware __fw_modinst
        $(call cmd,depmod)
 
+ifeq ($(CONFIG_MODULE_SIG), y)
+PHONY += modules_sign
+modules_sign:
+       $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modsign
+endif
+
 else # CONFIG_MODULES
 
 # Modules not configured
index 54ffd0f9df21b7d9f28789104dd48e5bdcf5a965..8e9e3246b2b4e0f1a0b2218f5e49a8cacecb24d2 100644 (file)
@@ -113,6 +113,25 @@ config HAVE_EFFICIENT_UNALIGNED_ACCESS
          See Documentation/unaligned-memory-access.txt for more
          information on the topic of unaligned memory accesses.
 
+config ARCH_USE_BUILTIN_BSWAP
+       bool
+       help
+        Modern versions of GCC (since 4.4) have builtin functions
+        for handling byte-swapping. Using these, instead of the old
+        inline assembler that the architecture code provides in the
+        __arch_bswapXX() macros, allows the compiler to see what's
+        happening and offers more opportunity for optimisation. In
+        particular, the compiler will be able to combine the byteswap
+        with a nearby load or store and use load-and-swap or
+        store-and-swap instructions if the architecture has them. It
+        should almost *never* result in code which is worse than the
+        hand-coded assembler in <asm/swab.h>.  But just in case it
+        does, the use of the builtins is optional.
+
+        Any architecture with load-and-swap or store-and-swap
+        instructions should set this. And it shouldn't hurt to set it
+        on architectures that don't have such instructions.
+
 config HAVE_SYSCALL_WRAPPERS
        bool
 
index 009096d1d2c37694bbd30d82f90ee294bbe18b2c..b4ca60f4eb42dabf24adfb7f47e1da0471381fc9 100644 (file)
@@ -73,7 +73,7 @@
                                400000
                                500000
                                600000 >;
-               status = "disable";
+               status = "disabled";
        };
 
        ahb {
                        compatible = "st,spear600-fsmc-nand";
                        #address-cells = <1>;
                        #size-cells = <1>;
-                       reg = <0xb0000000 0x1000        /* FSMC Register */
-                              0xb0800000 0x0010>;      /* NAND Base */
-                       reg-names = "fsmc_regs", "nand_data";
+                       reg = <0xb0000000 0x1000        /* FSMC Register*/
+                              0xb0800000 0x0010        /* NAND Base DATA */
+                              0xb0820000 0x0010        /* NAND Base ADDR */
+                              0xb0810000 0x0010>;      /* NAND Base CMD */
+                       reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
                        interrupts = <0 20 0x4
                                      0 21 0x4
                                      0 22 0x4
                                      0 23 0x4>;
-                       st,ale-off = <0x20000>;
-                       st,cle-off = <0x10000>;
                        st,mode = <2>;
                        status = "disabled";
                };
                        compatible = "st,pcm-audio";
                        #address-cells = <0>;
                        #size-cells = <0>;
-                       status = "disable";
+                       status = "disabled";
                };
 
                smi: flash@ea000000 {
index 090adc65601504d4744f3d8156d3fdc464c60521..f79b3dfaabe6c2cc3f984148dde816e1674bc803 100644 (file)
                        #address-cells = <1>;
                        #size-cells = <1>;
                        reg = <0x94000000 0x1000        /* FSMC Register */
-                              0x80000000 0x0010>;      /* NAND Base */
-                       reg-names = "fsmc_regs", "nand_data";
-                       st,ale-off = <0x20000>;
-                       st,cle-off = <0x10000>;
+                              0x80000000 0x0010        /* NAND Base DATA */
+                              0x80020000 0x0010        /* NAND Base ADDR */
+                              0x80010000 0x0010>;      /* NAND Base CMD */
+                       reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
                        status = "disabled";
                };
 
index e814e5e9708318f968ca03224efae27d92242bb6..ab45b8c81982d17937052943370517bdfb6cb261 100644 (file)
                        #address-cells = <1>;
                        #size-cells = <1>;
                        reg = <0x44000000 0x1000        /* FSMC Register */
-                              0x40000000 0x0010>;      /* NAND Base */
-                       reg-names = "fsmc_regs", "nand_data";
-                       st,ale-off = <0x10000>;
-                       st,cle-off = <0x20000>;
+                              0x40000000 0x0010        /* NAND Base DATA */
+                              0x40020000 0x0010        /* NAND Base ADDR */
+                              0x40010000 0x0010>;      /* NAND Base CMD */
+                       reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
                        status = "disabled";
                };
 
index c056a84deabf90cfdf0ae937faaabf6fd5ff13ec..caa5520b1fd4e4e243f194c821d4b196833a1bee 100644 (file)
                        #address-cells = <1>;
                        #size-cells = <1>;
                        reg = <0x4c000000 0x1000        /* FSMC Register */
-                              0x50000000 0x0010>;      /* NAND Base */
-                       reg-names = "fsmc_regs", "nand_data";
-                       st,ale-off = <0x20000>;
-                       st,cle-off = <0x10000>;
+                              0x50000000 0x0010        /* NAND Base DATA */
+                              0x50020000 0x0010        /* NAND Base ADDR */
+                              0x50010000 0x0010>;      /* NAND Base CMD */
+                       reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
                        status = "disabled";
                };
 
index e051dde5181f31d56f3ad099e3df49c0d5e308a4..19f99dc4115e164c8903a3259ea873675be16ee2 100644 (file)
                        #address-cells = <1>;
                        #size-cells = <1>;
                        reg = <0xd1800000 0x1000        /* FSMC Register */
-                              0xd2000000 0x4000>;      /* NAND Base */
-                       reg-names = "fsmc_regs", "nand_data";
-                       st,ale-off = <0x20000>;
-                       st,cle-off = <0x10000>;
+                              0xd2000000 0x0010        /* NAND Base DATA */
+                              0xd2020000 0x0010        /* NAND Base ADDR */
+                              0xd2010000 0x0010>;      /* NAND Base CMD */
+                       reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
                        status = "disabled";
                };
 
index 240b25eea56559bb0588af7a048d720c15bb54ed..86cfd2959c47552bb2bcf40bbe630e6e36dce6db 100644 (file)
@@ -57,7 +57,7 @@ CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ECC_SMC=y
-CONFIG_MTD_NAND_NOMADIK=y
+CONFIG_MTD_NAND_FSMC=y
 CONFIG_MTD_ONENAND=y
 CONFIG_MTD_ONENAND_VERIFY_WRITE=y
 CONFIG_MTD_ONENAND_GENERIC=y
index ac03bdb4ae442a5e7b0a69cf0252ad84894c1b58..4da7cde70b5d3fac435bdbf13b3dcc9c298be4c7 100644 (file)
 #define __NR_process_vm_readv          (__NR_SYSCALL_BASE+376)
 #define __NR_process_vm_writev         (__NR_SYSCALL_BASE+377)
                                        /* 378 for kcmp */
+#define __NR_finit_module              (__NR_SYSCALL_BASE+379)
 
 /*
  * This may need to be greater than __NR_last_syscall+1 in order to
index 5935b6a02e6e2e0af99db6bda596574eadb35199..a4fda4e7a372f4428a00a0871d142b67f9458313 100644 (file)
                CALL(sys_process_vm_readv)
                CALL(sys_process_vm_writev)
                CALL(sys_ni_syscall)    /* reserved for sys_kcmp */
+               CALL(sys_finit_module)
 #ifndef syscalls_counted
 .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
 #define syscalls_counted
index 5ccdf53c5a9dcd0c3a6814d61b49d083e34a89eb..98167a4319f72d3735adf6ab4e277d68da8790b8 100644 (file)
@@ -19,6 +19,7 @@
 #include <linux/gpio.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
+#include <linux/mtd/fsmc.h>
 #include <linux/mtd/onenand.h>
 #include <linux/mtd/partitions.h>
 #include <linux/i2c.h>
@@ -33,7 +34,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 #include <asm/mach/time.h>
-#include <mach/fsmc.h>
 #include <mach/irqs.h>
 
 #include "cpu-8815.h"
 #define SRC_CR_INIT_MASK       0x00007fff
 #define SRC_CR_INIT_VAL                0x2aaa8000
 
+#define ALE_OFF 0x1000000
+#define CLE_OFF 0x800000
+
 /* These addresses span 16MB, so use three individual pages */
 static struct resource nhk8815_nand_resources[] = {
        {
+               .name = "nand_data",
+               .start = 0x40000000,
+               .end = 0x40000000 + SZ_16K - 1,
+               .flags = IORESOURCE_MEM,
+       }, {
                .name = "nand_addr",
-               .start = NAND_IO_ADDR,
-               .end = NAND_IO_ADDR + 0xfff,
+               .start = 0x40000000 + ALE_OFF,
+               .end = 0x40000000 +ALE_OFF + SZ_16K - 1,
                .flags = IORESOURCE_MEM,
        }, {
                .name = "nand_cmd",
-               .start = NAND_IO_CMD,
-               .end = NAND_IO_CMD + 0xfff,
+               .start = 0x40000000 + CLE_OFF,
+               .end = 0x40000000 + CLE_OFF + SZ_16K - 1,
                .flags = IORESOURCE_MEM,
        }, {
-               .name = "nand_data",
-               .start = NAND_IO_DATA,
-               .end = NAND_IO_DATA + 0xfff,
+               .name  = "fsmc_regs",
+               .start = NOMADIK_FSMC_BASE,
+               .end   = NOMADIK_FSMC_BASE + SZ_4K - 1,
                .flags = IORESOURCE_MEM,
-       }
+       },
 };
 
-static int nhk8815_nand_init(void)
-{
-       /* FSMC setup for nand chip select (8-bit nand in 8815NHK) */
-       writel(0x0000000E, FSMC_PCR(0));
-       writel(0x000D0A00, FSMC_PMEM(0));
-       writel(0x00100A00, FSMC_PATT(0));
-
-       /* enable access to the chip select area */
-       writel(readl(FSMC_PCR(0)) | 0x04, FSMC_PCR(0));
-
-       return 0;
-}
-
 /*
  * These partitions are the same as those used in the 2.6.20 release
  * shipped by the vendor; the first two partitions are mandated
@@ -108,20 +103,28 @@ static struct mtd_partition nhk8815_partitions[] = {
        }
 };
 
-static struct nomadik_nand_platform_data nhk8815_nand_data = {
-       .parts          = nhk8815_partitions,
-       .nparts         = ARRAY_SIZE(nhk8815_partitions),
-       .options        = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING,
-       .init           = nhk8815_nand_init,
+static struct fsmc_nand_timings nhk8815_nand_timings = {
+       .thiz   = 0,
+       .thold  = 0x10,
+       .twait  = 0x0A,
+       .tset   = 0,
+};
+
+static struct fsmc_nand_platform_data nhk8815_nand_platform_data = {
+       .nand_timings = &nhk8815_nand_timings,
+       .partitions = nhk8815_partitions,
+       .nr_partitions = ARRAY_SIZE(nhk8815_partitions),
+       .width = FSMC_NAND_BW8,
 };
 
 static struct platform_device nhk8815_nand_device = {
-       .name           = "nomadik_nand",
-       .dev            = {
-               .platform_data = &nhk8815_nand_data,
+       .name = "fsmc-nand",
+       .id = -1,
+       .resource = nhk8815_nand_resources,
+       .num_resources = ARRAY_SIZE(nhk8815_nand_resources),
+       .dev = {
+               .platform_data = &nhk8815_nand_platform_data,
        },
-       .resource       = nhk8815_nand_resources,
-       .num_resources  = ARRAY_SIZE(nhk8815_nand_resources),
 };
 
 /* These are the partitions for the OneNand device, different from above */
@@ -176,6 +179,10 @@ static struct platform_device nhk8815_onenand_device = {
        .num_resources  = ARRAY_SIZE(nhk8815_onenand_resource),
 };
 
+/* bus control reg. and bus timing reg. for CS0..CS3 */
+#define FSMC_BCR(x)    (NOMADIK_FSMC_VA + (x << 3))
+#define FSMC_BTR(x)    (NOMADIK_FSMC_VA + (x << 3) + 0x04)
+
 static void __init nhk8815_onenand_init(void)
 {
 #ifdef CONFIG_MTD_ONENAND
diff --git a/arch/arm/mach-nomadik/include/mach/fsmc.h b/arch/arm/mach-nomadik/include/mach/fsmc.h
deleted file mode 100644 (file)
index 8c2c051..0000000
+++ /dev/null
@@ -1,29 +0,0 @@
-
-/* Definitions for the Nomadik FSMC "Flexible Static Memory controller" */
-
-#ifndef __ASM_ARCH_FSMC_H
-#define __ASM_ARCH_FSMC_H
-
-#include <mach/hardware.h>
-/*
- * Register list
- */
-
-/* bus control reg. and bus timing reg. for CS0..CS3 */
-#define FSMC_BCR(x)     (NOMADIK_FSMC_VA + (x << 3))
-#define FSMC_BTR(x)     (NOMADIK_FSMC_VA + (x << 3) + 0x04)
-
-/* PC-card and NAND:
- * PCR = control register
- * PMEM = memory timing
- * PATT = attribute timing
- * PIO = I/O timing
- * PECCR = ECC result
- */
-#define FSMC_PCR(x)     (NOMADIK_FSMC_VA + ((2 + x) << 5) + 0x00)
-#define FSMC_PMEM(x)    (NOMADIK_FSMC_VA + ((2 + x) << 5) + 0x08)
-#define FSMC_PATT(x)    (NOMADIK_FSMC_VA + ((2 + x) << 5) + 0x0c)
-#define FSMC_PIO(x)     (NOMADIK_FSMC_VA + ((2 + x) << 5) + 0x10)
-#define FSMC_PECCR(x)   (NOMADIK_FSMC_VA + ((2 + x) << 5) + 0x14)
-
-#endif /* __ASM_ARCH_FSMC_H */
index 60529e0b3d67aea6a98da9c6774d81c4ca539e28..cf07e289b4eadb494f942ca966b4c78569102b82 100644 (file)
@@ -256,6 +256,11 @@ static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = {
        },
 };
 
+static struct platform_device rx51_battery_device = {
+       .name   = "rx51-battery",
+       .id     = -1,
+};
+
 static void rx51_charger_set_power(bool on)
 {
        gpio_set_value(RX51_USB_TRANSCEIVER_RST_GPIO, on);
@@ -277,6 +282,7 @@ static void __init rx51_charger_init(void)
        WARN_ON(gpio_request_one(RX51_USB_TRANSCEIVER_RST_GPIO,
                GPIOF_OUT_INIT_HIGH, "isp1704_reset"));
 
+       platform_device_register(&rx51_battery_device);
        platform_device_register(&rx51_charger_device);
 }
 
index 12f3994c43dbf5809f291972132a4db5763f73a7..8b204ae6900212524791908db1b215a82654bb09 100644 (file)
@@ -249,6 +249,18 @@ static struct resource rtc_resources[] = {
  * but these are not yet used by the driver.
  */
 static struct resource fsmc_resources[] = {
+       {
+               .name  = "nand_addr",
+               .start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE,
+               .end   = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE + SZ_16K - 1,
+               .flags = IORESOURCE_MEM,
+       },
+       {
+               .name  = "nand_cmd",
+               .start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE,
+               .end   = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE + SZ_16K - 1,
+               .flags = IORESOURCE_MEM,
+       },
        {
                .name  = "nand_data",
                .start = U300_NAND_CS0_PHYS_BASE,
@@ -1492,8 +1504,6 @@ static struct fsmc_nand_platform_data nand_platform_data = {
        .nr_partitions = ARRAY_SIZE(u300_partitions),
        .options = NAND_SKIP_BBTSCAN,
        .width = FSMC_NAND_BW8,
-       .ale_off = PLAT_NAND_ALE,
-       .cle_off = PLAT_NAND_CLE,
 };
 
 static struct platform_device nand_device = {
index 37400f5869e6137d780be5326ab49875d939f15c..51123f985eb5862a83bf7afcfc22e4bce2ecbda7 100644 (file)
@@ -32,8 +32,6 @@
 #ifdef CONFIG_ETRAX_KMALLOCED_MODULES
 void *module_alloc(unsigned long size)
 {
-       if (size == 0)
-               return NULL;
        return kmalloc(size, GFP_KERNEL);
 }
 
index 5e34ccf39a49eba54d9a0cbf74c2055ed439cb43..2a625fb063e1537bcdff9dd18cc10dde87ec535f 100644 (file)
@@ -214,8 +214,6 @@ static inline int reassemble_22(int as22)
 
 void *module_alloc(unsigned long size)
 {
-       if (size == 0)
-               return NULL;
        /* using RWX means less protection for modules, but it's
         * easier than trying to map the text, data, init_text and
         * init_data correctly */
index cec8aae5cbf8a85fc0f7db35734222e287e7cd48..97909d3b1d7b0b63f602dacbbcc97c681b35db67 100644 (file)
@@ -356,3 +356,4 @@ COMPAT_SYS_SPU(sendmmsg)
 SYSCALL_SPU(setns)
 COMPAT_SYS(process_vm_readv)
 COMPAT_SYS(process_vm_writev)
+SYSCALL(finit_module)
index bcbbe413c6069a885f8c755acee5baab38cf1220..29365e15ed7c1d3425a906459344fedd06ddb766 100644 (file)
@@ -12,7 +12,7 @@
 #include <uapi/asm/unistd.h>
 
 
-#define __NR_syscalls          353
+#define __NR_syscalls          354
 
 #define __NR__exit __NR_exit
 #define NR_syscalls    __NR_syscalls
index 380b5d37a9049fd1c2cb60d852d46e5e648c293d..8c478c6c6b1e41c7090b06a8b52815f7d537ff89 100644 (file)
 #define __NR_setns             350
 #define __NR_process_vm_readv  351
 #define __NR_process_vm_writev 352
+#define __NR_finit_module      353
 
 
 #endif /* _UAPI_ASM_POWERPC_UNISTD_H_ */
index 23f6cbb910d393a94cb3e6bd57aced5514f7766f..1cda8aa7cb852639cbb98fac2314abbdf9859afb 100644 (file)
@@ -1024,7 +1024,11 @@ ENTRY(aes_sparc64_ecb_encrypt_256)
         add            %o2, 0x20, %o2
        brlz,pt         %o3, 11f
         nop
-10:    ldx             [%o1 + 0x00], %g3
+10:    ldd             [%o0 + 0xd0], %f56
+       ldd             [%o0 + 0xd8], %f58
+       ldd             [%o0 + 0xe0], %f60
+       ldd             [%o0 + 0xe8], %f62
+       ldx             [%o1 + 0x00], %g3
        ldx             [%o1 + 0x08], %g7
        xor             %g1, %g3, %g3
        xor             %g2, %g7, %g7
@@ -1128,9 +1132,9 @@ ENTRY(aes_sparc64_ecb_decrypt_256)
        /* %o0=&key[key_len], %o1=input, %o2=output, %o3=len */
        ldx             [%o0 - 0x10], %g1
        subcc           %o3, 0x10, %o3
+       ldx             [%o0 - 0x08], %g2
        be              10f
-        ldx            [%o0 - 0x08], %g2
-       sub             %o0, 0xf0, %o0
+        sub            %o0, 0xf0, %o0
 1:     ldx             [%o1 + 0x00], %g3
        ldx             [%o1 + 0x08], %g7
        ldx             [%o1 + 0x10], %o4
@@ -1154,7 +1158,11 @@ ENTRY(aes_sparc64_ecb_decrypt_256)
         add            %o2, 0x20, %o2
        brlz,pt         %o3, 11f
         nop
-10:    ldx             [%o1 + 0x00], %g3
+10:    ldd             [%o0 + 0x18], %f56
+       ldd             [%o0 + 0x10], %f58
+       ldd             [%o0 + 0x08], %f60
+       ldd             [%o0 + 0x00], %f62
+       ldx             [%o1 + 0x00], %g3
        ldx             [%o1 + 0x08], %g7
        xor             %g1, %g3, %g3
        xor             %g2, %g7, %g7
@@ -1511,11 +1519,11 @@ ENTRY(aes_sparc64_ctr_crypt_256)
         add            %o2, 0x20, %o2
        brlz,pt         %o3, 11f
         nop
-       ldd             [%o0 + 0xd0], %f56
+10:    ldd             [%o0 + 0xd0], %f56
        ldd             [%o0 + 0xd8], %f58
        ldd             [%o0 + 0xe0], %f60
        ldd             [%o0 + 0xe8], %f62
-10:    xor             %g1, %g3, %o5
+       xor             %g1, %g3, %o5
        MOVXTOD_O5_F0
        xor             %g2, %g7, %o5
        MOVXTOD_O5_F2
index 3965d1d36dfaa84e4634a7918bfdb9626f4bfe1a..503e6d96ad4e49963727ef637f2d3fb985e25fb4 100644 (file)
@@ -222,6 +222,7 @@ static int ecb_encrypt(struct blkcipher_desc *desc,
 
        blkcipher_walk_init(&walk, dst, src, nbytes);
        err = blkcipher_walk_virt(desc, &walk);
+       desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
 
        ctx->ops->load_encrypt_keys(&ctx->key[0]);
        while ((nbytes = walk.nbytes)) {
@@ -251,6 +252,7 @@ static int ecb_decrypt(struct blkcipher_desc *desc,
 
        blkcipher_walk_init(&walk, dst, src, nbytes);
        err = blkcipher_walk_virt(desc, &walk);
+       desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
 
        ctx->ops->load_decrypt_keys(&ctx->key[0]);
        key_end = &ctx->key[ctx->expanded_key_length / sizeof(u64)];
@@ -280,6 +282,7 @@ static int cbc_encrypt(struct blkcipher_desc *desc,
 
        blkcipher_walk_init(&walk, dst, src, nbytes);
        err = blkcipher_walk_virt(desc, &walk);
+       desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
 
        ctx->ops->load_encrypt_keys(&ctx->key[0]);
        while ((nbytes = walk.nbytes)) {
@@ -309,6 +312,7 @@ static int cbc_decrypt(struct blkcipher_desc *desc,
 
        blkcipher_walk_init(&walk, dst, src, nbytes);
        err = blkcipher_walk_virt(desc, &walk);
+       desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
 
        ctx->ops->load_decrypt_keys(&ctx->key[0]);
        key_end = &ctx->key[ctx->expanded_key_length / sizeof(u64)];
@@ -329,6 +333,22 @@ static int cbc_decrypt(struct blkcipher_desc *desc,
        return err;
 }
 
+static void ctr_crypt_final(struct crypto_sparc64_aes_ctx *ctx,
+                           struct blkcipher_walk *walk)
+{
+       u8 *ctrblk = walk->iv;
+       u64 keystream[AES_BLOCK_SIZE / sizeof(u64)];
+       u8 *src = walk->src.virt.addr;
+       u8 *dst = walk->dst.virt.addr;
+       unsigned int nbytes = walk->nbytes;
+
+       ctx->ops->ecb_encrypt(&ctx->key[0], (const u64 *)ctrblk,
+                             keystream, AES_BLOCK_SIZE);
+       crypto_xor((u8 *) keystream, src, nbytes);
+       memcpy(dst, keystream, nbytes);
+       crypto_inc(ctrblk, AES_BLOCK_SIZE);
+}
+
 static int ctr_crypt(struct blkcipher_desc *desc,
                     struct scatterlist *dst, struct scatterlist *src,
                     unsigned int nbytes)
@@ -338,10 +358,11 @@ static int ctr_crypt(struct blkcipher_desc *desc,
        int err;
 
        blkcipher_walk_init(&walk, dst, src, nbytes);
-       err = blkcipher_walk_virt(desc, &walk);
+       err = blkcipher_walk_virt_block(desc, &walk, AES_BLOCK_SIZE);
+       desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
 
        ctx->ops->load_encrypt_keys(&ctx->key[0]);
-       while ((nbytes = walk.nbytes)) {
+       while ((nbytes = walk.nbytes) >= AES_BLOCK_SIZE) {
                unsigned int block_len = nbytes & AES_BLOCK_MASK;
 
                if (likely(block_len)) {
@@ -353,6 +374,10 @@ static int ctr_crypt(struct blkcipher_desc *desc,
                nbytes &= AES_BLOCK_SIZE - 1;
                err = blkcipher_walk_done(desc, &walk, nbytes);
        }
+       if (walk.nbytes) {
+               ctr_crypt_final(ctx, &walk);
+               err = blkcipher_walk_done(desc, &walk, 0);
+       }
        fprs_write(0);
        return err;
 }
@@ -418,7 +443,7 @@ static struct crypto_alg algs[] = { {
        .cra_driver_name        = "ctr-aes-sparc64",
        .cra_priority           = SPARC_CR_OPCODE_PRIORITY,
        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
-       .cra_blocksize          = AES_BLOCK_SIZE,
+       .cra_blocksize          = 1,
        .cra_ctxsize            = sizeof(struct crypto_sparc64_aes_ctx),
        .cra_alignmask          = 7,
        .cra_type               = &crypto_blkcipher_type,
index 62c89af3fd3fb3793a9dc0af63244fd94e7d808e..888f6260b4ec5169d36c23860a6f0bc70c5f5404 100644 (file)
@@ -98,6 +98,7 @@ static int __ecb_crypt(struct blkcipher_desc *desc,
 
        blkcipher_walk_init(&walk, dst, src, nbytes);
        err = blkcipher_walk_virt(desc, &walk);
+       desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
 
        if (encrypt)
                key = &ctx->encrypt_key[0];
@@ -160,6 +161,7 @@ static int cbc_encrypt(struct blkcipher_desc *desc,
 
        blkcipher_walk_init(&walk, dst, src, nbytes);
        err = blkcipher_walk_virt(desc, &walk);
+       desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
 
        key = &ctx->encrypt_key[0];
        camellia_sparc64_load_keys(key, ctx->key_len);
@@ -198,6 +200,7 @@ static int cbc_decrypt(struct blkcipher_desc *desc,
 
        blkcipher_walk_init(&walk, dst, src, nbytes);
        err = blkcipher_walk_virt(desc, &walk);
+       desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
 
        key = &ctx->decrypt_key[0];
        camellia_sparc64_load_keys(key, ctx->key_len);
index 30b6e90b28b2d793e1b18e5d342dabcfb515847b..b5c8fc269b5f3446964a6ee57a51d37eeb43e521 100644 (file)
@@ -376,6 +376,7 @@ ENTRY(des3_ede_sparc64_ecb_crypt)
 1:     ldd     [%o1 + 0x00], %f60
        DES3_LOOP_BODY(60)
        std     %f60, [%o2 + 0x00]
+       add     %o1, 0x08, %o1
        subcc   %o3, 0x08, %o3
        bne,pt  %icc, 1b
         add    %o2, 0x08, %o2
index 41524cebcc49e4dfb48e0628efd67b9aa50619ac..3065bc61f9d3bcf2ec96e78a2b3a15d96f981e14 100644 (file)
@@ -100,6 +100,7 @@ static int __ecb_crypt(struct blkcipher_desc *desc,
 
        blkcipher_walk_init(&walk, dst, src, nbytes);
        err = blkcipher_walk_virt(desc, &walk);
+       desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
 
        if (encrypt)
                des_sparc64_load_keys(&ctx->encrypt_expkey[0]);
@@ -147,6 +148,7 @@ static int cbc_encrypt(struct blkcipher_desc *desc,
 
        blkcipher_walk_init(&walk, dst, src, nbytes);
        err = blkcipher_walk_virt(desc, &walk);
+       desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
 
        des_sparc64_load_keys(&ctx->encrypt_expkey[0]);
        while ((nbytes = walk.nbytes)) {
@@ -177,6 +179,7 @@ static int cbc_decrypt(struct blkcipher_desc *desc,
 
        blkcipher_walk_init(&walk, dst, src, nbytes);
        err = blkcipher_walk_virt(desc, &walk);
+       desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
 
        des_sparc64_load_keys(&ctx->decrypt_expkey[0]);
        while ((nbytes = walk.nbytes)) {
@@ -266,6 +269,7 @@ static int __ecb3_crypt(struct blkcipher_desc *desc,
 
        blkcipher_walk_init(&walk, dst, src, nbytes);
        err = blkcipher_walk_virt(desc, &walk);
+       desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
 
        if (encrypt)
                K = &ctx->encrypt_expkey[0];
@@ -317,6 +321,7 @@ static int cbc3_encrypt(struct blkcipher_desc *desc,
 
        blkcipher_walk_init(&walk, dst, src, nbytes);
        err = blkcipher_walk_virt(desc, &walk);
+       desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
 
        K = &ctx->encrypt_expkey[0];
        des3_ede_sparc64_load_keys(K);
@@ -352,6 +357,7 @@ static int cbc3_decrypt(struct blkcipher_desc *desc,
 
        blkcipher_walk_init(&walk, dst, src, nbytes);
        err = blkcipher_walk_virt(desc, &walk);
+       desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
 
        K = &ctx->decrypt_expkey[0];
        des3_ede_sparc64_load_keys(K);
index 8c5eed6d267f5566512c30dbd93f8ff8abc43c2d..9661e9bc7bb6a21a957f8dae15cfc48354658233 100644 (file)
@@ -61,14 +61,20 @@ static inline pte_t huge_pte_wrprotect(pte_t pte)
 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
                                           unsigned long addr, pte_t *ptep)
 {
-       ptep_set_wrprotect(mm, addr, ptep);
+       pte_t old_pte = *ptep;
+       set_huge_pte_at(mm, addr, ptep, pte_wrprotect(old_pte));
 }
 
 static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
                                             unsigned long addr, pte_t *ptep,
                                             pte_t pte, int dirty)
 {
-       return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
+       int changed = !pte_same(*ptep, pte);
+       if (changed) {
+               set_huge_pte_at(vma->vm_mm, addr, ptep, pte);
+               flush_tlb_page(vma, addr);
+       }
+       return changed;
 }
 
 static inline pte_t huge_ptep_get(pte_t *ptep)
index 95515f1e7cef7006beb397c8f0e60026b2664290..7870be0f5adc4d922c21874f06af9bedacc2dfd2 100644 (file)
@@ -617,6 +617,12 @@ static inline unsigned long pte_present(pte_t pte)
        return val;
 }
 
+#define pte_accessible pte_accessible
+static inline unsigned long pte_accessible(pte_t a)
+{
+       return pte_val(a) & _PAGE_VALID;
+}
+
 static inline unsigned long pte_special(pte_t pte)
 {
        return pte_val(pte) & _PAGE_SPECIAL;
@@ -802,7 +808,7 @@ static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
         * SUN4V NOTE: _PAGE_VALID is the same value in both the SUN4U
         *             and SUN4V pte layout, so this inline test is fine.
         */
-       if (likely(mm != &init_mm) && (pte_val(orig) & _PAGE_VALID))
+       if (likely(mm != &init_mm) && pte_accessible(orig))
                tlb_batch_add(mm, addr, ptep, orig, fullmm);
 }
 
index f1ddc0d2367947d850e863aa4d0a897705074574..4435488ebe258580afd7177dc61579e2c3727044 100644 (file)
@@ -43,10 +43,6 @@ void *module_alloc(unsigned long size)
 {
        void *ret;
 
-       /* We handle the zero case fine, unlike vmalloc */
-       if (size == 0)
-               return NULL;
-
        ret = module_map(size);
        if (ret)
                memset(ret, 0, size);
index 243ffebe38d69a510f16e53083c49b46f3e6531b..4918d91bc3a660942a6aec8585be2bb41425d3df 100644 (file)
@@ -42,8 +42,6 @@ void *module_alloc(unsigned long size)
        int i = 0;
        int npages;
 
-       if (size == 0)
-               return NULL;
        npages = (size + PAGE_SIZE - 1) / PAGE_SIZE;
        pages = kmalloc(npages * sizeof(struct page *), GFP_KERNEL);
        if (pages == NULL)
index 8fbe8577f5e6902d07667ad426bdc6f2f5b8bfe9..16bd1495b9342472f86c3610fefbce27cce87000 100644 (file)
@@ -27,9 +27,6 @@ void *module_alloc(unsigned long size)
        struct vm_struct *area;
 
        size = PAGE_ALIGN(size);
-       if (!size)
-               return NULL;
-
        area = __get_vm_area(size, VM_ALLOC, MODULES_VADDR, MODULES_END);
        if (!area)
                return NULL;
index fbd895562292cdf54695a5aaa1433e7dfee61397..3286a92e662a13a4e146cbe73912c8f239427007 100644 (file)
@@ -26,11 +26,6 @@ static void show_cpuinfo_core(struct seq_file *m, struct cpuinfo_x86 *c,
 #ifdef CONFIG_X86_32
 static void show_cpuinfo_misc(struct seq_file *m, struct cpuinfo_x86 *c)
 {
-       /*
-        * We use exception 16 if we have hardware math and we've either seen
-        * it or the CPU claims it is internal
-        */
-       int fpu_exception = c->hard_math && (ignore_fpu_irq || cpu_has_fpu);
        seq_printf(m,
                   "fdiv_bug\t: %s\n"
                   "hlt_bug\t\t: %s\n"
@@ -45,7 +40,7 @@ static void show_cpuinfo_misc(struct seq_file *m, struct cpuinfo_x86 *c)
                   c->f00f_bug ? "yes" : "no",
                   c->coma_bug ? "yes" : "no",
                   c->hard_math ? "yes" : "no",
-                  fpu_exception ? "yes" : "no",
+                  c->hard_math ? "yes" : "no",
                   c->cpuid_level,
                   c->wp_works_ok ? "yes" : "no");
 }
index 6e03b0d6913817a312f72f016b027c46756197ff..7dc4e459c2b389c2126d679d1692856ea4caddb0 100644 (file)
  * (these are usually mapped into the 0x30-0xff vector range)
  */
 
-#ifdef CONFIG_X86_32
-/*
- * Note that on a 486, we don't want to do a SIGFPE on an irq13
- * as the irq is unreliable, and exception 16 works correctly
- * (ie as explained in the intel literature). On a 386, you
- * can't use exception 16 due to bad IBM design, so we have to
- * rely on the less exact irq13.
- *
- * Careful.. Not only is IRQ13 unreliable, but it is also
- * leads to races. IBM designers who came up with it should
- * be shot.
- */
-
-static irqreturn_t math_error_irq(int cpl, void *dev_id)
-{
-       outb(0, 0xF0);
-       if (ignore_fpu_irq || !boot_cpu_data.hard_math)
-               return IRQ_NONE;
-       math_error(get_irq_regs(), 0, X86_TRAP_MF);
-       return IRQ_HANDLED;
-}
-
-/*
- * New motherboards sometimes make IRQ 13 be a PCI interrupt,
- * so allow interrupt sharing.
- */
-static struct irqaction fpu_irq = {
-       .handler = math_error_irq,
-       .name = "fpu",
-       .flags = IRQF_NO_THREAD,
-};
-#endif
-
 /*
  * IRQ2 is cascade interrupt to second interrupt controller
  */
@@ -242,13 +209,6 @@ void __init native_init_IRQ(void)
                setup_irq(2, &irq2);
 
 #ifdef CONFIG_X86_32
-       /*
-        * External FPU? Set up irq13 if so, for
-        * original braindamaged IBM FERR coupling.
-        */
-       if (boot_cpu_data.hard_math && !cpu_has_fpu)
-               setup_irq(FPU_IRQ, &fpu_irq);
-
        irq_ctx_init(smp_processor_id());
 #endif
 }
index eb8586693e0b7ce3a49238f3c409d7adc4e0a751..ecffca11f4e92cb1df5bbf4bcedb0dcefb86bc8a 100644 (file)
@@ -69,9 +69,6 @@
 
 asmlinkage int system_call(void);
 
-/* Do we ignore FPU interrupts ? */
-char ignore_fpu_irq;
-
 /*
  * The IDT has to be page-aligned to simplify the Pentium
  * F0 0F bug workaround.
@@ -564,9 +561,6 @@ void math_error(struct pt_regs *regs, int error_code, int trapnr)
 
 dotraplinkage void do_coprocessor_error(struct pt_regs *regs, long error_code)
 {
-#ifdef CONFIG_X86_32
-       ignore_fpu_irq = 1;
-#endif
        exception_enter(regs);
        math_error(regs, error_code, X86_TRAP_MF);
        exception_exit(regs);
index ee3c220ee5009fec90afff372c3cff543d90c658..05f404f53f59ceeade47d9fad8694d20599ee88b 100644 (file)
 347    i386    process_vm_readv        sys_process_vm_readv            compat_sys_process_vm_readv
 348    i386    process_vm_writev       sys_process_vm_writev           compat_sys_process_vm_writev
 349    i386    kcmp                    sys_kcmp
+350    i386    finit_module            sys_finit_module
index a582bfed95bb05fd1ae4f62060f719856d49a405..7c58c84b7bc8dae578f7cee7dc2433ad46e69f03 100644 (file)
 310    64      process_vm_readv        sys_process_vm_readv
 311    64      process_vm_writev       sys_process_vm_writev
 312    common  kcmp                    sys_kcmp
+313    common  finit_module            sys_finit_module
 
 #
 # x32-specific system call numbers start at 512 to avoid cache impact
index 2481f267be298a9c9b2f0891d703a15b8d725def..73d34e77c39c136b0066236b7b8a2f43d8b9aa0c 100644 (file)
@@ -17,6 +17,7 @@ config XTENSA
        select GENERIC_KERNEL_EXECVE
        select ARCH_WANT_OPTIONAL_GPIOLIB
        select CLONE_BACKWARDS
+       select IRQ_DOMAIN
        help
          Xtensa processors are 32-bit RISC machines designed by Tensilica
          primarily for embedded systems.  These processors are both
@@ -150,6 +151,15 @@ config XTENSA_PLATFORM_S6105
        select SERIAL_CONSOLE
        select NO_IOPORT
 
+config XTENSA_PLATFORM_XTFPGA
+       bool "XTFPGA"
+       select SERIAL_CONSOLE
+       select ETHOC
+       select XTENSA_CALIBRATE_CCOUNT
+       help
+         XTFPGA is the name of Tensilica board family (LX60, LX110, LX200, ML605).
+         This hardware is capable of running a full Linux distribution.
+
 endchoice
 
 
@@ -177,6 +187,17 @@ config CMDLINE
          time by entering them here. As a minimum, you should specify the
          memory size and the root device (e.g., mem=64M root=/dev/nfs).
 
+config USE_OF
+       bool "Flattened Device Tree support"
+       select OF
+       select OF_EARLY_FLATTREE
+       help
+         Include support for flattened device tree machine descriptions.
+
+config BUILTIN_DTB
+       string "DTB to build into the kernel image"
+       depends on OF
+
 source "mm/Kconfig"
 
 source "drivers/pcmcia/Kconfig"
index 11c585295dd7b830b0dcab0393ec1f4f4ec3b3f2..a34010e0e51c3fcfece542266886ced6563a47eb 100644 (file)
@@ -2,6 +2,26 @@ menu "Kernel hacking"
 
 source "lib/Kconfig.debug"
 
-endmenu
+config LD_NO_RELAX
+       bool "Disable linker relaxation"
+       default n
+       help
+         Enable this function to disable link-time optimizations.
+         The default linker behavior is to combine identical literal
+         values to reduce code size and remove unnecessary overhead from
+         assembler-generated 'longcall' sequences.
+         Enabling this option improves the link time but increases the
+         code size, and possibly execution time.
+
+config S32C1I_SELFTEST
+       bool "Perform S32C1I instruction self-test at boot"
+       default y
+       help
+         Enable this option to test S32C1I instruction behavior at boot.
+         Correct operation of this instruction requires some cooperation from hardware
+         external to the processor (such as bus bridge, bus fabric, or memory controller).
+         It is easy to make wrong hardware configuration, this test should catch it early.
 
+         Say 'N' on stable hardware.
 
+endmenu
index bb5ba61723f73d4feab322008524c3d90801d38b..0aa72702f1796b1892258ba995c4128a9df00a7b 100644 (file)
@@ -38,6 +38,7 @@ endif
 platform-$(CONFIG_XTENSA_PLATFORM_XT2000)      := xt2000
 platform-$(CONFIG_XTENSA_PLATFORM_ISS)         := iss
 platform-$(CONFIG_XTENSA_PLATFORM_S6105)       := s6105
+platform-$(CONFIG_XTENSA_PLATFORM_XTFPGA)      := xtfpga
 
 PLATFORM = $(platform-y)
 export PLATFORM
@@ -49,6 +50,17 @@ KBUILD_CFLAGS += -pipe -mlongcalls
 
 KBUILD_CFLAGS += $(call cc-option,-mforce-no-pic,)
 
+ifneq ($(CONFIG_LD_NO_RELAX),)
+LDFLAGS := --no-relax
+endif
+
+ifeq ($(shell echo -e __XTENSA_EB__ | $(CC) -E - | grep -v "\#"),1)
+CHECKFLAGS += -D__XTENSA_EB__
+endif
+ifeq ($(shell echo -e __XTENSA_EL__ | $(CC) -E - | grep -v "\#"),1)
+CHECKFLAGS += -D__XTENSA_EL__
+endif
+
 vardirs := $(patsubst %,arch/xtensa/variants/%/,$(variant-y))
 plfdirs := $(patsubst %,arch/xtensa/platforms/%/,$(platform-y))
 
@@ -75,6 +87,10 @@ core-y               += $(buildvar) $(buildplf)
 
 libs-y         += arch/xtensa/lib/ $(LIBGCC)
 
+ifneq ($(CONFIG_BUILTIN_DTB),"")
+core-$(CONFIG_OF) += arch/xtensa/boot/
+endif
+
 boot           := arch/xtensa/boot
 
 all: zImage
@@ -84,7 +100,9 @@ bzImage : zImage
 zImage: vmlinux
        $(Q)$(MAKE) $(build)=$(boot) $@
 
+%.dtb:
+       $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
+
 define archhelp
   @echo '* zImage      - Compressed kernel image (arch/xtensa/boot/images/zImage.*)'
 endef
-
index 4018f899419603253841f67520c65cea57a9e1ec..818647e815d7e4bb6812668d56f7db6f2d9d5c32 100644 (file)
@@ -22,12 +22,35 @@ subdir-y    := lib
 # Subdirs for the boot loader(s)
 
 bootdir-$(CONFIG_XTENSA_PLATFORM_ISS)   += boot-elf
-bootdir-$(CONFIG_XTENSA_PLATFORM_XT2000) += boot-redboot boot-elf
+bootdir-$(CONFIG_XTENSA_PLATFORM_XT2000) += boot-redboot boot-elf boot-uboot
+bootdir-$(CONFIG_XTENSA_PLATFORM_XTFPGA) += boot-redboot boot-elf boot-uboot
 
 
+BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB)).dtb.o
+ifneq ($(CONFIG_BUILTIN_DTB),"")
+obj-$(CONFIG_OF) += $(BUILTIN_DTB)
+endif
+
+# Rule to build device tree blobs
+$(obj)/%.dtb: $(src)/dts/%.dts FORCE
+       $(call if_changed_dep,dtc)
+
+clean-files := *.dtb.S
+
 zImage Image: $(bootdir-y)
 
 $(bootdir-y): $(addprefix $(obj)/,$(subdir-y)) \
              $(addprefix $(obj)/,$(host-progs))
        $(Q)$(MAKE) $(build)=$(obj)/$@ $(MAKECMDGOALS)
 
+OBJCOPYFLAGS = --strip-all -R .comment -R .note.gnu.build-id -O binary
+
+vmlinux.bin: vmlinux FORCE
+       $(call if_changed,objcopy)
+
+vmlinux.bin.gz: vmlinux.bin FORCE
+       $(call if_changed,gzip)
+
+boot-elf: vmlinux.bin
+boot-redboot: vmlinux.bin.gz
+boot-uboot: vmlinux.bin.gz
index f10992b890273de29bce8a8b2df264196e739426..1fe01b78c1247d40ebf96de4bf05c60a9c988e2a 100644 (file)
@@ -4,9 +4,6 @@
 # for more details.
 #
 
-GZIP = gzip
-GZIP_FLAGS = -v9fc
-
 ifeq ($(BIG_ENDIAN),1)
 OBJCOPY_ARGS    := -O elf32-xtensa-be
 else
@@ -20,18 +17,17 @@ boot-y              := bootstrap.o
 
 OBJS           := $(addprefix $(obj)/,$(boot-y))
 
-vmlinux.tmp: vmlinux
-       $(OBJCOPY) --strip-all -R .comment -R .note.gnu.build-id -O binary \
-               $^ $@
-
-Image: vmlinux.tmp $(OBJS) arch/$(ARCH)/boot/boot-elf/boot.lds
-       $(OBJCOPY) $(OBJCOPY_ARGS) -R .comment \
-               --add-section image=vmlinux.tmp \
+$(obj)/Image.o: vmlinux.bin $(OBJS)
+       $(Q)$(OBJCOPY) $(OBJCOPY_ARGS) -R .comment \
+               --add-section image=vmlinux.bin \
                --set-section-flags image=contents,alloc,load,load,data \
-               $(OBJS) $@.tmp
-       $(LD) $(LDFLAGS) $(LDFLAGS_vmlinux) \
-               -T arch/$(ARCH)/boot/boot-elf/boot.lds \
-               -o arch/$(ARCH)/boot/$@.elf $@.tmp
+               $(OBJS) $@
 
-zImage:        Image
+$(obj)/../Image.elf: $(obj)/Image.o $(obj)/boot.lds
+       $(Q)$(LD) $(LDFLAGS) $(LDFLAGS_vmlinux) \
+               -T $(obj)/boot.lds \
+               --build-id=none \
+               -o $@ $(obj)/Image.o
+       $(Q)$(kecho) '  Kernel: $@ is ready'
 
+zImage:        $(obj)/../Image.elf
index 25a78c6b153002b9a5486a4cd3a4628b217b2f81..8be8b943698178716093b06f40e53a13261e1cfd 100644 (file)
@@ -4,8 +4,6 @@
 # for more details.
 #
 
-GZIP = gzip
-GZIP_FLAGS = -v9fc
 ifeq ($(BIG_ENDIAN),1)
 OBJCOPY_ARGS   := -O elf32-xtensa-be
 else
@@ -21,17 +19,17 @@ LIBS        := arch/xtensa/boot/lib/lib.a arch/xtensa/lib/lib.a
 
 LIBGCC := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name)
 
-vmlinux.tmp: vmlinux
-       $(OBJCOPY) --strip-all -R .comment -R .note.gnu.build-id -O binary \
-               $^ $@
+$(obj)/zImage.o: vmlinux.bin.gz $(OBJS)
+       $(Q)$(OBJCOPY) $(OBJCOPY_ARGS) -R .comment \
+               --add-section image=vmlinux.bin.gz \
+               --set-section-flags image=contents,alloc,load,load,data \
+               $(OBJS) $@
 
-vmlinux.tmp.gz: vmlinux.tmp
-       $(GZIP) $(GZIP_FLAGS) $^ > $@
+$(obj)/zImage.elf: $(obj)/zImage.o $(LIBS)
+       $(Q)$(LD) $(LD_ARGS) -o $@ $^ -L/xtensa-elf/lib $(LIBGCC)
 
-zImage: vmlinux.tmp.gz $(OBJS) $(LIBS)
-       $(OBJCOPY) $(OBJCOPY_ARGS) -R .comment \
-               --add-section image=vmlinux.tmp.gz \
-               --set-section-flags image=contents,alloc,load,load,data \
-               $(OBJS) $@.tmp
-       $(LD) $(LD_ARGS) -o $@.elf $@.tmp $(LIBS) -L/xtensa-elf/lib $(LIBGCC)
-       $(OBJCOPY) -S -O binary $@.elf arch/$(ARCH)/boot/$@.redboot
+$(obj)/../zImage.redboot: $(obj)/zImage.elf
+       $(Q)$(OBJCOPY) -S -O binary $< $@
+       $(Q)$(kecho) '  Kernel: $@ is ready'
+
+zImage: $(obj)/../zImage.redboot
diff --git a/arch/xtensa/boot/boot-uboot/Makefile b/arch/xtensa/boot/boot-uboot/Makefile
new file mode 100644 (file)
index 0000000..bfbf8af
--- /dev/null
@@ -0,0 +1,14 @@
+#
+# This file is subject to the terms and conditions of the GNU General Public
+# License.  See the file "COPYING" in the main directory of this archive
+# for more details.
+#
+
+UIMAGE_LOADADDR = 0xd0001000
+UIMAGE_COMPRESSION = gzip
+
+$(obj)/../uImage: vmlinux.bin.gz FORCE
+       $(call if_changed,uimage)
+       $(Q)$(kecho) '  Kernel: $@ is ready'
+
+zImage: $(obj)/../uImage
diff --git a/arch/xtensa/boot/dts/lx60.dts b/arch/xtensa/boot/dts/lx60.dts
new file mode 100644 (file)
index 0000000..2eab365
--- /dev/null
@@ -0,0 +1,11 @@
+/dts-v1/;
+/include/ "xtfpga.dtsi"
+/include/ "xtfpga-flash-4m.dtsi"
+
+/ {
+       compatible = "xtensa,lx60";
+       memory@0 {
+               device_type = "memory";
+               reg = <0x00000000 0x04000000>;
+       };
+};
diff --git a/arch/xtensa/boot/dts/ml605.dts b/arch/xtensa/boot/dts/ml605.dts
new file mode 100644 (file)
index 0000000..6ed51d6
--- /dev/null
@@ -0,0 +1,11 @@
+/dts-v1/;
+/include/ "xtfpga.dtsi"
+/include/ "xtfpga-flash-16m.dtsi"
+
+/ {
+       compatible = "xtensa,ml605";
+       memory@0 {
+               device_type = "memory";
+               reg = <0x00000000 0x08000000>;
+       };
+};
diff --git a/arch/xtensa/boot/dts/xtfpga-flash-16m.dtsi b/arch/xtensa/boot/dts/xtfpga-flash-16m.dtsi
new file mode 100644 (file)
index 0000000..e5703c7
--- /dev/null
@@ -0,0 +1,26 @@
+/ {
+       flash: flash@f8000000 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "cfi-flash";
+               reg = <0xf8000000 0x01000000>;
+               bank-width = <2>;
+               device-width = <2>;
+               partition@0x0 {
+                       label = "boot loader area";
+                       reg = <0x00000000 0x00400000>;
+               };
+               partition@0x400000 {
+                       label = "kernel image";
+                       reg = <0x00400000 0x00600000>;
+               };
+               partition@0xa00000 {
+                       label = "data";
+                       reg = <0x00a00000 0x005e0000>;
+               };
+               partition@0xfe0000 {
+                       label = "boot environment";
+                       reg = <0x00fe0000 0x00020000>;
+               };
+        };
+};
diff --git a/arch/xtensa/boot/dts/xtfpga-flash-4m.dtsi b/arch/xtensa/boot/dts/xtfpga-flash-4m.dtsi
new file mode 100644 (file)
index 0000000..6f9c10d
--- /dev/null
@@ -0,0 +1,18 @@
+/ {
+       flash: flash@f8000000 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "cfi-flash";
+               reg = <0xf8000000 0x00400000>;
+               bank-width = <2>;
+               device-width = <2>;
+               partition@0x0 {
+                       label = "boot loader area";
+                       reg = <0x00000000 0x003f0000>;
+               };
+               partition@0x3f0000 {
+                       label = "boot environment";
+                       reg = <0x003f0000 0x00010000>;
+               };
+        };
+};
diff --git a/arch/xtensa/boot/dts/xtfpga.dtsi b/arch/xtensa/boot/dts/xtfpga.dtsi
new file mode 100644 (file)
index 0000000..7eda6ec
--- /dev/null
@@ -0,0 +1,56 @@
+/ {
+       compatible = "xtensa,xtfpga";
+       #address-cells = <1>;
+       #size-cells = <1>;
+       interrupt-parent = <&pic>;
+
+       chosen {
+               bootargs = "earlycon=uart8250,mmio32,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug";
+       };
+
+       memory@0 {
+               device_type = "memory";
+               reg = <0x00000000 0x06000000>;
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               cpu@0 {
+                       compatible = "xtensa,cpu";
+                       reg = <0>;
+                       /* Filled in by platform_setup from FPGA register
+                        * clock-frequency = <100000000>;
+                        */
+               };
+       };
+
+       pic: pic {
+               compatible = "xtensa,pic";
+               /* one cell: internal irq number,
+                * two cells: second cell == 0: internal irq number
+                *            second cell == 1: external irq number
+                */
+               #interrupt-cells = <2>;
+               interrupt-controller;
+       };
+
+       serial0: serial@fd050020 {
+               device_type = "serial";
+               compatible = "ns16550a";
+               no-loopback-test;
+               reg = <0xfd050020 0x20>;
+               reg-shift = <2>;
+               interrupts = <0 1>; /* external irq 0 */
+               /* Filled in by platform_setup from FPGA register
+                * clock-frequency = <100000000>;
+                */
+       };
+
+       enet0: ethoc@fd030000 {
+               compatible = "opencores,ethoc";
+               reg = <0xfd030000 0x4000 0xfd800000 0x4000>;
+               interrupts = <1 1>; /* external irq 1 */
+               local-mac-address = [00 50 c2 13 6f 00];
+       };
+};
index 24f50cada70c27ae041356f960b728dc285e4e5b..c3f289174c1056e82bb0a55c2026b4afef235d0f 100644 (file)
  */
 static inline void atomic_add(int i, atomic_t * v)
 {
-    unsigned int vval;
-
-    __asm__ __volatile__(
-       "rsil    a15, "__stringify(LOCKLEVEL)"\n\t"
-       "l32i    %0, %2, 0              \n\t"
-       "add     %0, %0, %1             \n\t"
-       "s32i    %0, %2, 0              \n\t"
-       "wsr     a15, ps                \n\t"
-       "rsync                          \n"
-       : "=&a" (vval)
-       : "a" (i), "a" (v)
-       : "a15", "memory"
-       );
+#if XCHAL_HAVE_S32C1I
+       unsigned long tmp;
+       int result;
+
+       __asm__ __volatile__(
+                       "1:     l32i    %1, %3, 0\n"
+                       "       wsr     %1, scompare1\n"
+                       "       add     %0, %1, %2\n"
+                       "       s32c1i  %0, %3, 0\n"
+                       "       bne     %0, %1, 1b\n"
+                       : "=&a" (result), "=&a" (tmp)
+                       : "a" (i), "a" (v)
+                       : "memory"
+                       );
+#else
+       unsigned int vval;
+
+       __asm__ __volatile__(
+                       "       rsil    a15, "__stringify(LOCKLEVEL)"\n"
+                       "       l32i    %0, %2, 0\n"
+                       "       add     %0, %0, %1\n"
+                       "       s32i    %0, %2, 0\n"
+                       "       wsr     a15, ps\n"
+                       "       rsync\n"
+                       : "=&a" (vval)
+                       : "a" (i), "a" (v)
+                       : "a15", "memory"
+                       );
+#endif
 }
 
 /**
@@ -90,19 +106,35 @@ static inline void atomic_add(int i, atomic_t * v)
  */
 static inline void atomic_sub(int i, atomic_t *v)
 {
-    unsigned int vval;
-
-    __asm__ __volatile__(
-       "rsil    a15, "__stringify(LOCKLEVEL)"\n\t"
-       "l32i    %0, %2, 0              \n\t"
-       "sub     %0, %0, %1             \n\t"
-       "s32i    %0, %2, 0              \n\t"
-       "wsr     a15, ps                \n\t"
-       "rsync                          \n"
-       : "=&a" (vval)
-       : "a" (i), "a" (v)
-       : "a15", "memory"
-       );
+#if XCHAL_HAVE_S32C1I
+       unsigned long tmp;
+       int result;
+
+       __asm__ __volatile__(
+                       "1:     l32i    %1, %3, 0\n"
+                       "       wsr     %1, scompare1\n"
+                       "       sub     %0, %1, %2\n"
+                       "       s32c1i  %0, %3, 0\n"
+                       "       bne     %0, %1, 1b\n"
+                       : "=&a" (result), "=&a" (tmp)
+                       : "a" (i), "a" (v)
+                       : "memory"
+                       );
+#else
+       unsigned int vval;
+
+       __asm__ __volatile__(
+                       "       rsil    a15, "__stringify(LOCKLEVEL)"\n"
+                       "       l32i    %0, %2, 0\n"
+                       "       sub     %0, %0, %1\n"
+                       "       s32i    %0, %2, 0\n"
+                       "       wsr     a15, ps\n"
+                       "       rsync\n"
+                       : "=&a" (vval)
+                       : "a" (i), "a" (v)
+                       : "a15", "memory"
+                       );
+#endif
 }
 
 /*
@@ -111,40 +143,78 @@ static inline void atomic_sub(int i, atomic_t *v)
 
 static inline int atomic_add_return(int i, atomic_t * v)
 {
-     unsigned int vval;
-
-    __asm__ __volatile__(
-       "rsil    a15,"__stringify(LOCKLEVEL)"\n\t"
-       "l32i    %0, %2, 0             \n\t"
-       "add     %0, %0, %1            \n\t"
-       "s32i    %0, %2, 0             \n\t"
-       "wsr     a15, ps               \n\t"
-       "rsync                         \n"
-       : "=&a" (vval)
-       : "a" (i), "a" (v)
-       : "a15", "memory"
-       );
-
-    return vval;
+#if XCHAL_HAVE_S32C1I
+       unsigned long tmp;
+       int result;
+
+       __asm__ __volatile__(
+                       "1:     l32i    %1, %3, 0\n"
+                       "       wsr     %1, scompare1\n"
+                       "       add     %0, %1, %2\n"
+                       "       s32c1i  %0, %3, 0\n"
+                       "       bne     %0, %1, 1b\n"
+                       "       add     %0, %0, %2\n"
+                       : "=&a" (result), "=&a" (tmp)
+                       : "a" (i), "a" (v)
+                       : "memory"
+                       );
+
+       return result;
+#else
+       unsigned int vval;
+
+       __asm__ __volatile__(
+                       "       rsil    a15,"__stringify(LOCKLEVEL)"\n"
+                       "       l32i    %0, %2, 0\n"
+                       "       add     %0, %0, %1\n"
+                       "       s32i    %0, %2, 0\n"
+                       "       wsr     a15, ps\n"
+                       "       rsync\n"
+                       : "=&a" (vval)
+                       : "a" (i), "a" (v)
+                       : "a15", "memory"
+                       );
+
+       return vval;
+#endif
 }
 
 static inline int atomic_sub_return(int i, atomic_t * v)
 {
-    unsigned int vval;
-
-    __asm__ __volatile__(
-       "rsil    a15,"__stringify(LOCKLEVEL)"\n\t"
-       "l32i    %0, %2, 0             \n\t"
-       "sub     %0, %0, %1            \n\t"
-       "s32i    %0, %2, 0             \n\t"
-       "wsr     a15, ps               \n\t"
-       "rsync                         \n"
-       : "=&a" (vval)
-       : "a" (i), "a" (v)
-       : "a15", "memory"
-       );
-
-    return vval;
+#if XCHAL_HAVE_S32C1I
+       unsigned long tmp;
+       int result;
+
+       __asm__ __volatile__(
+                       "1:     l32i    %1, %3, 0\n"
+                       "       wsr     %1, scompare1\n"
+                       "       sub     %0, %1, %2\n"
+                       "       s32c1i  %0, %3, 0\n"
+                       "       bne     %0, %1, 1b\n"
+                       "       sub     %0, %0, %2\n"
+                       : "=&a" (result), "=&a" (tmp)
+                       : "a" (i), "a" (v)
+                       : "memory"
+                       );
+
+       return result;
+#else
+       unsigned int vval;
+
+       __asm__ __volatile__(
+                       "       rsil    a15,"__stringify(LOCKLEVEL)"\n"
+                       "       l32i    %0, %2, 0\n"
+                       "       sub     %0, %0, %1\n"
+                       "       s32i    %0, %2, 0\n"
+                       "       wsr     a15, ps\n"
+                       "       rsync\n"
+                       : "=&a" (vval)
+                       : "a" (i), "a" (v)
+                       : "a15", "memory"
+                       );
+
+       return vval;
+#endif
 }
 
 /**
@@ -251,38 +321,70 @@ static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
 
 static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
 {
-    unsigned int all_f = -1;
-    unsigned int vval;
-
-    __asm__ __volatile__(
-       "rsil    a15,"__stringify(LOCKLEVEL)"\n\t"
-       "l32i    %0, %2, 0             \n\t"
-       "xor     %1, %4, %3            \n\t"
-       "and     %0, %0, %4            \n\t"
-       "s32i    %0, %2, 0             \n\t"
-       "wsr     a15, ps               \n\t"
-       "rsync                         \n"
-       : "=&a" (vval), "=a" (mask)
-       : "a" (v), "a" (all_f), "1" (mask)
-       : "a15", "memory"
-       );
+#if XCHAL_HAVE_S32C1I
+       unsigned long tmp;
+       int result;
+
+       __asm__ __volatile__(
+                       "1:     l32i    %1, %3, 0\n"
+                       "       wsr     %1, scompare1\n"
+                       "       and     %0, %1, %2\n"
+                       "       s32c1i  %0, %3, 0\n"
+                       "       bne     %0, %1, 1b\n"
+                       : "=&a" (result), "=&a" (tmp)
+                       : "a" (~mask), "a" (v)
+                       : "memory"
+                       );
+#else
+       unsigned int all_f = -1;
+       unsigned int vval;
+
+       __asm__ __volatile__(
+                       "       rsil    a15,"__stringify(LOCKLEVEL)"\n"
+                       "       l32i    %0, %2, 0\n"
+                       "       xor     %1, %4, %3\n"
+                       "       and     %0, %0, %4\n"
+                       "       s32i    %0, %2, 0\n"
+                       "       wsr     a15, ps\n"
+                       "       rsync\n"
+                       : "=&a" (vval), "=a" (mask)
+                       : "a" (v), "a" (all_f), "1" (mask)
+                       : "a15", "memory"
+                       );
+#endif
 }
 
 static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
 {
-    unsigned int vval;
-
-    __asm__ __volatile__(
-       "rsil    a15,"__stringify(LOCKLEVEL)"\n\t"
-       "l32i    %0, %2, 0             \n\t"
-       "or      %0, %0, %1            \n\t"
-       "s32i    %0, %2, 0             \n\t"
-       "wsr     a15, ps               \n\t"
-       "rsync                         \n"
-       : "=&a" (vval)
-       : "a" (mask), "a" (v)
-       : "a15", "memory"
-       );
+#if XCHAL_HAVE_S32C1I
+       unsigned long tmp;
+       int result;
+
+       __asm__ __volatile__(
+                       "1:     l32i    %1, %3, 0\n"
+                       "       wsr     %1, scompare1\n"
+                       "       or      %0, %1, %2\n"
+                       "       s32c1i  %0, %3, 0\n"
+                       "       bne     %0, %1, 1b\n"
+                       : "=&a" (result), "=&a" (tmp)
+                       : "a" (mask), "a" (v)
+                       : "memory"
+                       );
+#else
+       unsigned int vval;
+
+       __asm__ __volatile__(
+                       "       rsil    a15,"__stringify(LOCKLEVEL)"\n"
+                       "       l32i    %0, %2, 0\n"
+                       "       or      %0, %0, %1\n"
+                       "       s32i    %0, %2, 0\n"
+                       "       wsr     a15, ps\n"
+                       "       rsync\n"
+                       : "=&a" (vval)
+                       : "a" (mask), "a" (v)
+                       : "a15", "memory"
+                       );
+#endif
 }
 
 /* Atomic operations are already serializing */
@@ -294,4 +396,3 @@ static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
 #endif /* __KERNEL__ */
 
 #endif /* _XTENSA_ATOMIC_H */
-
index 55707a8009d3aacd5703c484a69c361b49e938a4..ef021677d536538c817021c89f0841ada0ed0c30 100644 (file)
@@ -3,7 +3,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2001 - 2005 Tensilica Inc.
+ * Copyright (C) 2001 - 2012 Tensilica Inc.
  */
 
 #ifndef _XTENSA_SYSTEM_H
@@ -12,8 +12,8 @@
 #define smp_read_barrier_depends() do { } while(0)
 #define read_barrier_depends() do { } while(0)
 
-#define mb()  barrier()
-#define rmb() mb()
+#define mb()  ({ __asm__ __volatile__("memw" : : : "memory"); })
+#define rmb() barrier()
 #define wmb() mb()
 
 #ifdef CONFIG_SMP
index 5270197ddd369bd76771ab1f05a2c5bbb24563cb..84afe58d5d374bc7cc19f8d02dbcc279b3b0014a 100644 (file)
@@ -29,7 +29,6 @@
 #define smp_mb__before_clear_bit()     barrier()
 #define smp_mb__after_clear_bit()      barrier()
 
-#include <asm-generic/bitops/atomic.h>
 #include <asm-generic/bitops/non-atomic.h>
 
 #if XCHAL_HAVE_NSA
@@ -104,6 +103,132 @@ static inline unsigned long __fls(unsigned long word)
 #endif
 
 #include <asm-generic/bitops/fls64.h>
+
+#if XCHAL_HAVE_S32C1I
+
+static inline void set_bit(unsigned int bit, volatile unsigned long *p)
+{
+       unsigned long tmp, value;
+       unsigned long mask = 1UL << (bit & 31);
+
+       p += bit >> 5;
+
+       __asm__ __volatile__(
+                       "1:     l32i    %1, %3, 0\n"
+                       "       wsr     %1, scompare1\n"
+                       "       or      %0, %1, %2\n"
+                       "       s32c1i  %0, %3, 0\n"
+                       "       bne     %0, %1, 1b\n"
+                       : "=&a" (tmp), "=&a" (value)
+                       : "a" (mask), "a" (p)
+                       : "memory");
+}
+
+static inline void clear_bit(unsigned int bit, volatile unsigned long *p)
+{
+       unsigned long tmp, value;
+       unsigned long mask = 1UL << (bit & 31);
+
+       p += bit >> 5;
+
+       __asm__ __volatile__(
+                       "1:     l32i    %1, %3, 0\n"
+                       "       wsr     %1, scompare1\n"
+                       "       and     %0, %1, %2\n"
+                       "       s32c1i  %0, %3, 0\n"
+                       "       bne     %0, %1, 1b\n"
+                       : "=&a" (tmp), "=&a" (value)
+                       : "a" (~mask), "a" (p)
+                       : "memory");
+}
+
+static inline void change_bit(unsigned int bit, volatile unsigned long *p)
+{
+       unsigned long tmp, value;
+       unsigned long mask = 1UL << (bit & 31);
+
+       p += bit >> 5;
+
+       __asm__ __volatile__(
+                       "1:     l32i    %1, %3, 0\n"
+                       "       wsr     %1, scompare1\n"
+                       "       xor     %0, %1, %2\n"
+                       "       s32c1i  %0, %3, 0\n"
+                       "       bne     %0, %1, 1b\n"
+                       : "=&a" (tmp), "=&a" (value)
+                       : "a" (mask), "a" (p)
+                       : "memory");
+}
+
+static inline int
+test_and_set_bit(unsigned int bit, volatile unsigned long *p)
+{
+       unsigned long tmp, value;
+       unsigned long mask = 1UL << (bit & 31);
+
+       p += bit >> 5;
+
+       __asm__ __volatile__(
+                       "1:     l32i    %1, %3, 0\n"
+                       "       wsr     %1, scompare1\n"
+                       "       or      %0, %1, %2\n"
+                       "       s32c1i  %0, %3, 0\n"
+                       "       bne     %0, %1, 1b\n"
+                       : "=&a" (tmp), "=&a" (value)
+                       : "a" (mask), "a" (p)
+                       : "memory");
+
+       return tmp & mask;
+}
+
+static inline int
+test_and_clear_bit(unsigned int bit, volatile unsigned long *p)
+{
+       unsigned long tmp, value;
+       unsigned long mask = 1UL << (bit & 31);
+
+       p += bit >> 5;
+
+       __asm__ __volatile__(
+                       "1:     l32i    %1, %3, 0\n"
+                       "       wsr     %1, scompare1\n"
+                       "       and     %0, %1, %2\n"
+                       "       s32c1i  %0, %3, 0\n"
+                       "       bne     %0, %1, 1b\n"
+                       : "=&a" (tmp), "=&a" (value)
+                       : "a" (~mask), "a" (p)
+                       : "memory");
+
+       return tmp & mask;
+}
+
+static inline int
+test_and_change_bit(unsigned int bit, volatile unsigned long *p)
+{
+       unsigned long tmp, value;
+       unsigned long mask = 1UL << (bit & 31);
+
+       p += bit >> 5;
+
+       __asm__ __volatile__(
+                       "1:     l32i    %1, %3, 0\n"
+                       "       wsr     %1, scompare1\n"
+                       "       xor     %0, %1, %2\n"
+                       "       s32c1i  %0, %3, 0\n"
+                       "       bne     %0, %1, 1b\n"
+                       : "=&a" (tmp), "=&a" (value)
+                       : "a" (mask), "a" (p)
+                       : "memory");
+
+       return tmp & mask;
+}
+
+#else
+
+#include <asm-generic/bitops/atomic.h>
+
+#endif /* XCHAL_HAVE_S32C1I */
+
 #include <asm-generic/bitops/find.h>
 #include <asm-generic/bitops/le.h>
 
index 9983f2c1b7ee905ad6e15770808d4cce1507cfb1..0c25799facabf9ab9fb50d73e6707b6846a12994 100644 (file)
@@ -22,6 +22,7 @@
 #define BP_TAG_MEMORY          0x1003  /* memory addr and size (bp_meminfo) */
 #define BP_TAG_SERIAL_BAUSRATE 0x1004  /* baud rate of current console. */
 #define BP_TAG_SERIAL_PORT     0x1005  /* serial device of current console */
+#define BP_TAG_FDT             0x1006  /* flat device tree addr */
 
 #define BP_TAG_FIRST           0x7B0B  /* first tag with a version number */
 #define BP_TAG_LAST            0x7E0B  /* last tag */
 /* All records are aligned to 4 bytes */
 
 typedef struct bp_tag {
-  unsigned short id;           /* tag id */
-  unsigned short size;         /* size of this record excluding the structure*/
-  unsigned long data[0];       /* data */
+       unsigned short id;      /* tag id */
+       unsigned short size;    /* size of this record excluding the structure*/
+       unsigned long data[0];  /* data */
 } bp_tag_t;
 
 typedef struct meminfo {
-  unsigned long type;
-  unsigned long start;
-  unsigned long end;
+       unsigned long type;
+       unsigned long start;
+       unsigned long end;
 } meminfo_t;
 
 #define SYSMEM_BANKS_MAX 5
@@ -48,14 +49,11 @@ typedef struct meminfo {
 #define MEMORY_TYPE_NONE               0x2000
 
 typedef struct sysmem_info {
-  int nr_banks;
-  meminfo_t bank[SYSMEM_BANKS_MAX];
+       int nr_banks;
+       meminfo_t bank[SYSMEM_BANKS_MAX];
 } sysmem_info_t;
 
 extern sysmem_info_t sysmem;
 
 #endif
 #endif
-
-
-
index 2c20a58f94cdd8629164b3974e4a76d75eb90f66..60e18773ecb81837b4a06e2f4b5e19fe99f2aa1e 100644 (file)
        __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH
 
        .endm
-
index 569fec4f9a20db0899e8ee92085ba4faea2fa4d2..127cd48883c4274526c63631b181bea6dc366941 100644 (file)
@@ -104,7 +104,8 @@ static inline void __invalidate_icache_page_alias(unsigned long virt,
 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
 extern void flush_dcache_page(struct page*);
 extern void flush_cache_range(struct vm_area_struct*, ulong, ulong);
-extern void flush_cache_page(struct vm_area_struct*, unsigned long, unsigned long);
+extern void flush_cache_page(struct vm_area_struct*,
+                            unsigned long, unsigned long);
 
 #else
 
index e4d831a307720c4c70b6390c139a0bed9a401ef1..aed7ad68ca46e9a9a5f80ddef999ec8f003512d0 100644 (file)
@@ -36,8 +36,9 @@ asmlinkage __wsum csum_partial(const void *buff, int len, __wsum sum);
  * better 64-bit) boundary
  */
 
-asmlinkage __wsum csum_partial_copy_generic(const void *src, void *dst, int len, __wsum sum,
-                                                  int *src_err_ptr, int *dst_err_ptr);
+asmlinkage __wsum csum_partial_copy_generic(const void *src, void *dst,
+                                           int len, __wsum sum,
+                                           int *src_err_ptr, int *dst_err_ptr);
 
 /*
  *     Note: when you get a NULL pointer exception here this means someone
@@ -54,7 +55,7 @@ __wsum csum_partial_copy_nocheck(const void *src, void *dst,
 
 static inline
 __wsum csum_partial_copy_from_user(const void __user *src, void *dst,
-                                               int len, __wsum sum, int *err_ptr)
+                                  int len, __wsum sum, int *err_ptr)
 {
        return csum_partial_copy_generic((__force const void *)src, dst,
                                        len, sum, err_ptr, NULL);
@@ -112,7 +113,8 @@ static __inline__ __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
        /* Since the input registers which are loaded with iph and ihl
           are modified, we must also specify them as outputs, or gcc
           will assume they contain their original values. */
-               : "=r" (sum), "=r" (iph), "=r" (ihl), "=&r" (tmp), "=&r" (endaddr)
+               : "=r" (sum), "=r" (iph), "=r" (ihl), "=&r" (tmp),
+                 "=&r" (endaddr)
                : "1" (iph), "2" (ihl)
                : "memory");
 
@@ -168,7 +170,7 @@ static __inline__ __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
 
 static __inline__ __sum16 ip_compute_csum(const void *buff, int len)
 {
-    return csum_fold (csum_partial(buff, len, 0));
+       return csum_fold (csum_partial(buff, len, 0));
 }
 
 #define _HAVE_ARCH_IPV6_CSUM
@@ -238,11 +240,12 @@ static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
  *     Copy and checksum to user
  */
 #define HAVE_CSUM_COPY_USER
-static __inline__ __wsum csum_and_copy_to_user(const void *src, void __user *dst,
-                                   int len, __wsum sum, int *err_ptr)
+static __inline__ __wsum csum_and_copy_to_user(const void *src,
+                                              void __user *dst, int len,
+                                              __wsum sum, int *err_ptr)
 {
        if (access_ok(VERIFY_WRITE, dst, len))
-               return csum_partial_copy_generic(src, dst, len, sum, NULL, err_ptr);
+               return csum_partial_copy_generic(src,dst,len,sum,NULL,err_ptr);
 
        if (len)
                *err_ptr = -EFAULT;
index 64dad04a9d276453cfca46df63eabcad816a07e2..d9ab131bc1aa8c8cefa243f97bb6e9d5e8561161 100644 (file)
 static inline unsigned long
 __cmpxchg_u32(volatile int *p, int old, int new)
 {
-  __asm__ __volatile__("rsil    a15, "__stringify(LOCKLEVEL)"\n\t"
-                      "l32i    %0, %1, 0              \n\t"
-                      "bne     %0, %2, 1f             \n\t"
-                      "s32i    %3, %1, 0              \n\t"
-                      "1:                             \n\t"
-                      "wsr     a15, ps                \n\t"
-                      "rsync                          \n\t"
-                      : "=&a" (old)
-                      : "a" (p), "a" (old), "r" (new)
-                      : "a15", "memory");
-  return old;
+#if XCHAL_HAVE_S32C1I
+       __asm__ __volatile__(
+                       "       wsr     %2, scompare1\n"
+                       "       s32c1i  %0, %1, 0\n"
+                       : "+a" (new)
+                       : "a" (p), "a" (old)
+                       : "memory"
+                       );
+
+       return new;
+#else
+       __asm__ __volatile__(
+                       "       rsil    a15, "__stringify(LOCKLEVEL)"\n"
+                       "       l32i    %0, %1, 0\n"
+                       "       bne     %0, %2, 1f\n"
+                       "       s32i    %3, %1, 0\n"
+                       "1:\n"
+                       "       wsr     a15, ps\n"
+                       "       rsync\n"
+                       : "=&a" (old)
+                       : "a" (p), "a" (old), "r" (new)
+                       : "a15", "memory");
+       return old;
+#endif
 }
 /* This function doesn't exist, so you'll get a linker error
  * if something tries to do an invalid cmpxchg(). */
@@ -93,19 +106,36 @@ static inline unsigned long __cmpxchg_local(volatile void *ptr,
 
 static inline unsigned long xchg_u32(volatile int * m, unsigned long val)
 {
-  unsigned long tmp;
-  __asm__ __volatile__("rsil    a15, "__stringify(LOCKLEVEL)"\n\t"
-                      "l32i    %0, %1, 0              \n\t"
-                      "s32i    %2, %1, 0              \n\t"
-                      "wsr     a15, ps                \n\t"
-                      "rsync                          \n\t"
-                      : "=&a" (tmp)
-                      : "a" (m), "a" (val)
-                      : "a15", "memory");
-  return tmp;
+#if XCHAL_HAVE_S32C1I
+       unsigned long tmp, result;
+       __asm__ __volatile__(
+                       "1:     l32i    %1, %2, 0\n"
+                       "       mov     %0, %3\n"
+                       "       wsr     %1, scompare1\n"
+                       "       s32c1i  %0, %2, 0\n"
+                       "       bne     %0, %1, 1b\n"
+                       : "=&a" (result), "=&a" (tmp)
+                       : "a" (m), "a" (val)
+                       : "memory"
+                       );
+       return result;
+#else
+       unsigned long tmp;
+       __asm__ __volatile__(
+                       "       rsil    a15, "__stringify(LOCKLEVEL)"\n"
+                       "       l32i    %0, %1, 0\n"
+                       "       s32i    %2, %1, 0\n"
+                       "       wsr     a15, ps\n"
+                       "       rsync\n"
+                       : "=&a" (tmp)
+                       : "a" (m), "a" (val)
+                       : "a15", "memory");
+       return tmp;
+#endif
 }
 
-#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
+#define xchg(ptr,x) \
+       ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
 
 /*
  * This only works if the compiler isn't horribly bad at optimizing.
index 8d1eb5d786491124ff02953f6345928e3e44c557..47e46dcf5d49e741e76f025e151b7aa62c441835 100644 (file)
@@ -30,7 +30,7 @@ static inline struct task_struct *get_current(void)
 
 #define GET_CURRENT(reg,sp)            \
        GET_THREAD_INFO(reg,sp);        \
-       l32i reg, reg, TI_TASK          \
+       l32i reg, reg, TI_TASK          \
 
 #endif
 
index 58c0a4fd4003891f18cd1c9a4f8babe4f1923be3..61fc5faeb46c65e8be7a613328daf4204bbf2781 100644 (file)
@@ -19,9 +19,9 @@ extern unsigned long loops_per_jiffy;
 
 static inline void __delay(unsigned long loops)
 {
-  /* 2 cycles per loop. */
-  __asm__ __volatile__ ("1: addi %0, %0, -2; bgeui %0, 2, 1b"
-                       : "=r" (loops) : "0" (loops));
+       /* 2 cycles per loop. */
+       __asm__ __volatile__ ("1: addi %0, %0, -2; bgeui %0, 2, 1b"
+                             : "=r" (loops) : "0" (loops));
 }
 
 static __inline__ u32 xtensa_get_ccount(void)
@@ -46,4 +46,3 @@ static __inline__ void udelay (unsigned long usecs)
 }
 
 #endif
-
index 492c95790ad5ac2072ab60720ee6469d53e5d0f0..4acb5feba1fb7ae0bb830fed17b0391ae7a8483a 100644 (file)
@@ -16,6 +16,8 @@
 #include <linux/mm.h>
 #include <linux/scatterlist.h>
 
+#define DMA_ERROR_CODE         (~(dma_addr_t)0x0)
+
 /*
  * DMA-consistent mapping functions.
  */
@@ -98,8 +100,8 @@ dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size,
 }
 
 static inline void
-dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t size,
-               enum dma_data_direction direction)
+dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
+                          size_t size, enum dma_data_direction direction)
 {
        consistent_sync((void *)bus_to_virt(dma_handle), size, direction);
 }
index 5293312bc6a4c55d842519ef6c16cede7e5e197b..264d5fa450d8a9756ab46eee25f85691c42818be 100644 (file)
@@ -168,11 +168,11 @@ extern void xtensa_elf_core_copy_regs (xtensa_gregset_t *, struct pt_regs *);
  */
 
 #define ELF_PLAT_INIT(_r, load_addr) \
-  do { _r->areg[0]=0; /*_r->areg[1]=0;*/ _r->areg[2]=0;  _r->areg[3]=0;  \
-       _r->areg[4]=0;  _r->areg[5]=0;    _r->areg[6]=0;  _r->areg[7]=0;  \
-       _r->areg[8]=0;  _r->areg[9]=0;    _r->areg[10]=0; _r->areg[11]=0; \
-       _r->areg[12]=0; _r->areg[13]=0;   _r->areg[14]=0; _r->areg[15]=0; \
-  } while (0)
+       do { _r->areg[0]=0; /*_r->areg[1]=0;*/ _r->areg[2]=0;  _r->areg[3]=0;  \
+            _r->areg[4]=0;  _r->areg[5]=0;    _r->areg[6]=0;  _r->areg[7]=0;  \
+            _r->areg[8]=0;  _r->areg[9]=0;    _r->areg[10]=0; _r->areg[11]=0; \
+            _r->areg[12]=0; _r->areg[13]=0;   _r->areg[14]=0; _r->areg[15]=0; \
+       } while (0)
 
 typedef struct {
        xtregs_opt_t    opt;
index 0a046ca5a687ec3603593f1ec3e26cfeac2be314..80be15124697d8e85a23859a466e97f178936010 100644 (file)
@@ -14,4 +14,3 @@
 extern void flush_cache_kmaps(void);
 
 #endif
-
diff --git a/arch/xtensa/include/asm/initialize_mmu.h b/arch/xtensa/include/asm/initialize_mmu.h
new file mode 100644 (file)
index 0000000..e1f8ba4
--- /dev/null
@@ -0,0 +1,55 @@
+/*
+ * arch/xtensa/include/asm/initialize_mmu.h
+ *
+ * Initializes MMU:
+ *
+ *      For the new V3 MMU we remap the TLB from virtual == physical
+ *      to the standard Linux mapping used in earlier MMU's.
+ *
+ *      The the MMU we also support a new configuration register that
+ *      specifies how the S32C1I instruction operates with the cache
+ *      controller.
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file "COPYING" in the main directory of
+ * this archive for more details.
+ *
+ * Copyright (C) 2008 - 2012 Tensilica, Inc.
+ *
+ *   Marc Gauthier <marc@tensilica.com>
+ *   Pete Delaney <piet@tensilica.com>
+ */
+
+#ifndef _XTENSA_INITIALIZE_MMU_H
+#define _XTENSA_INITIALIZE_MMU_H
+
+#ifdef __ASSEMBLY__
+
+#define XTENSA_HWVERSION_RC_2009_0 230000
+
+       .macro  initialize_mmu
+
+#if XCHAL_HAVE_S32C1I && (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0)
+/*
+ * We Have Atomic Operation Control (ATOMCTL) Register; Initialize it.
+ * For details see Documentation/xtensa/atomctl.txt
+ */
+#if XCHAL_DCACHE_IS_COHERENT
+       movi    a3, 0x25        /* For SMP/MX -- internal for writeback,
+                                * RCW otherwise
+                                */
+#else
+       movi    a3, 0x29        /* non-MX -- Most cores use Std Memory
+                                * Controlers which usually can't use RCW
+                                */
+#endif
+       wsr     a3, atomctl
+#endif  /* XCHAL_HAVE_S32C1I &&
+        * (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0)
+        */
+
+       .endm
+
+#endif /*__ASSEMBLY__*/
+
+#endif /* _XTENSA_INITIALIZE_MMU_H */
index feb10af96519900e3cf64341b6c425b5e017e924..d43525a286bbf248b43e36fb878f6ee7fb31fa1e 100644 (file)
@@ -107,7 +107,7 @@ activate_mm(struct mm_struct *prev, struct mm_struct *next)
 
 
 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
-                             struct task_struct *tsk)
+                            struct task_struct *tsk)
 {
        unsigned long asid = asid_cache;
 
index 599e7a2e729dc7984cdd47ef1013b1aa612c0ea9..3407cf7989b7b5717eddbc30cb76cb14cfa639fa 100644 (file)
@@ -2,7 +2,7 @@ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
 {
 }
 
-static inline int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
+static inline int init_new_context(struct task_struct *tsk,struct mm_struct *mm)
 {
        return 0;
 }
index 7a5591a71f85093a8f58effc5a195f4f9b48c147..47f582333f6b799b246a39577e96bf1dced7cee3 100644 (file)
  * PAGE_SHIFT determines the page size
  */
 
-#define PAGE_SHIFT             12
-#define PAGE_SIZE              (__XTENSA_UL_CONST(1) << PAGE_SHIFT)
-#define PAGE_MASK              (~(PAGE_SIZE-1))
+#define PAGE_SHIFT     12
+#define PAGE_SIZE      (__XTENSA_UL_CONST(1) << PAGE_SHIFT)
+#define PAGE_MASK      (~(PAGE_SIZE-1))
 
 #ifdef CONFIG_MMU
-#define PAGE_OFFSET            XCHAL_KSEG_CACHED_VADDR
-#define MAX_MEM_PFN            XCHAL_KSEG_SIZE
+#define PAGE_OFFSET    XCHAL_KSEG_CACHED_VADDR
+#define MAX_MEM_PFN    XCHAL_KSEG_SIZE
 #else
-#define PAGE_OFFSET            0
-#define MAX_MEM_PFN            (PLATFORM_DEFAULT_MEM_START + PLATFORM_DEFAULT_MEM_SIZE)
+#define PAGE_OFFSET    0
+#define MAX_MEM_PFN    (PLATFORM_DEFAULT_MEM_START + PLATFORM_DEFAULT_MEM_SIZE)
 #endif
 
-#define PGTABLE_START          0x80000000
+#define PGTABLE_START  0x80000000
 
 /*
  * Cache aliasing:
@@ -161,7 +161,9 @@ extern void copy_user_page(void*, void*, unsigned long, struct page*);
 
 #define __pa(x)                        ((unsigned long) (x) - PAGE_OFFSET)
 #define __va(x)                        ((void *)((unsigned long) (x) + PAGE_OFFSET))
-#define pfn_valid(pfn)         ((pfn) >= ARCH_PFN_OFFSET && ((pfn) - ARCH_PFN_OFFSET) < max_mapnr)
+#define pfn_valid(pfn) \
+       ((pfn) >= ARCH_PFN_OFFSET && ((pfn) - ARCH_PFN_OFFSET) < max_mapnr)
+
 #ifdef CONFIG_DISCONTIGMEM
 # error CONFIG_DISCONTIGMEM not supported
 #endif
index 00fcbd7c534a472523b488e71ec382dc4dda88dd..0b68c76ec1e6054e5e4bbdc21c14b82356e96800 100644 (file)
@@ -35,7 +35,7 @@ struct pci_space {
 struct pci_controller {
        int index;                      /* used for pci_controller_num */
        struct pci_controller *next;
-        struct pci_bus *bus;
+       struct pci_bus *bus;
        void *arch_data;
 
        int first_busno;
index 05244f07dd31cc4a1fb32d5735e1f1d00920f551..614be031a79ab543295d8fe6b045db3a0aadb258 100644 (file)
@@ -53,7 +53,7 @@ struct pci_dev;
 
 /* Map a range of PCI memory or I/O space for a device into user space */
 int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
-                        enum pci_mmap_state mmap_state, int write_combine);
+                       enum pci_mmap_state mmap_state, int write_combine);
 
 /* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */
 #define HAVE_PCI_MMAP  1
index 40cf9bceda2cb92625112a951b174f5b56dd5471..cf914c8c249a0b801efa0e6e5768c5c1392ec926 100644 (file)
@@ -42,7 +42,7 @@ static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
 
 extern struct kmem_cache *pgtable_cache;
 
-static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, 
+static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
                                         unsigned long address)
 {
        return kmem_cache_alloc(pgtable_cache, GFP_KERNEL|__GFP_REPEAT);
index b03c043ce75b1243f18f080bbb06750913853a03..c90ea5bfa1b4da8d7790f01560802227b4fb3dcc 100644 (file)
@@ -284,7 +284,7 @@ struct vm_area_struct;
 
 static inline int
 ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr,
-                         pte_t *ptep)
+                         pte_t *ptep)
 {
        pte_t pte = *ptep;
        if (!pte_young(pte))
@@ -304,8 +304,8 @@ ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 static inline void
 ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 {
-       pte_t pte = *ptep;
-       update_pte(ptep, pte_wrprotect(pte));
+       pte_t pte = *ptep;
+       update_pte(ptep, pte_wrprotect(pte));
 }
 
 /* to find an entry in a kernel page-table-directory */
@@ -399,7 +399,7 @@ extern  void update_mmu_cache(struct vm_area_struct * vma,
  */
 
 #define io_remap_pfn_range(vma,from,pfn,size,prot) \
-                remap_pfn_range(vma, from, pfn, size, prot)
+       remap_pfn_range(vma, from, pfn, size, prot)
 
 typedef pte_t *pte_addr_t;
 
index 7d936e58e9be0a00dee26f90f0c5a0ca36954f29..ec098b68fb9a8035e2907c557a342622bb7488d4 100644 (file)
@@ -75,4 +75,3 @@ extern int platform_pcibios_fixup (void);
 extern void platform_calibrate_ccount (void);
 
 #endif /* _XTENSA_PLATFORM_H */
-
index 2d630e7399ca4f94584a77cdf2a150d6c9ff7319..e5fb6b0abdf49f738f192b2d6341f0e0f817476e 100644 (file)
@@ -89,7 +89,7 @@
 #define MAKE_PC_FROM_RA(ra,sp)    (((ra) & 0x3fffffff) | ((sp) & 0xc0000000))
 
 typedef struct {
-    unsigned long seg;
+       unsigned long seg;
 } mm_segment_t;
 
 struct thread_struct {
@@ -145,10 +145,10 @@ struct thread_struct {
  *       set_thread_state in signal.c depends on it.
  */
 #define USER_PS_VALUE ((1 << PS_WOE_BIT) |                             \
-                       (1 << PS_CALLINC_SHIFT) |                       \
-                       (USER_RING << PS_RING_SHIFT) |                  \
-                       (1 << PS_UM_BIT) |                              \
-                       (1 << PS_EXCM_BIT))
+                      (1 << PS_CALLINC_SHIFT) |                        \
+                      (USER_RING << PS_RING_SHIFT) |                   \
+                      (1 << PS_UM_BIT) |                               \
+                      (1 << PS_EXCM_BIT))
 
 /* Clearing a0 terminates the backtrace. */
 #define start_thread(regs, new_pc, new_sp) \
diff --git a/arch/xtensa/include/asm/prom.h b/arch/xtensa/include/asm/prom.h
new file mode 100644 (file)
index 0000000..f3d7cd2
--- /dev/null
@@ -0,0 +1,6 @@
+#ifndef _XTENSA_ASM_PROM_H
+#define _XTENSA_ASM_PROM_H
+
+#define HAVE_ARCH_DEVTREE_FIXUPS
+
+#endif /* _XTENSA_ASM_PROM_H */
index da21c17f23aad235c313c02683e87ccbfb9e23bf..58bf6fd3f913d4458162c4ddef8a4234a0a7cf6e 100644 (file)
@@ -37,7 +37,7 @@ struct pt_regs {
        unsigned long windowstart;      /*  52 */
        unsigned long syscall;          /*  56 */
        unsigned long icountlevel;      /*  60 */
-       int reserved[1];                /*  64 */
+       unsigned long scompare1;        /*  64 */
 
        /* Additional configurable registers that are used by the compiler. */
        xtregs_opt_t xtregs_opt;
@@ -55,7 +55,7 @@ struct pt_regs {
 
 # define arch_has_single_step()        (1)
 # define task_pt_regs(tsk) ((struct pt_regs*) \
-  (task_stack_page(tsk) + KERNEL_STACK_SIZE - (XCHAL_NUM_AREGS-16)*4) - 1)
+       (task_stack_page(tsk) + KERNEL_STACK_SIZE - (XCHAL_NUM_AREGS-16)*4) - 1)
 # define user_mode(regs) (((regs)->ps & 0x00000020)!=0)
 # define instruction_pointer(regs) ((regs)->pc)
 
index 8a8aa61ccc8df27075e4f2671715e9884571cc26..76096a4e5b8d7c43475154f9f235a163808a921d 100644 (file)
 #define EXCCAUSE_SPECULATION                   7
 #define EXCCAUSE_PRIVILEGED                    8
 #define EXCCAUSE_UNALIGNED                     9
+#define EXCCAUSE_INSTR_DATA_ERROR              12
+#define EXCCAUSE_LOAD_STORE_DATA_ERROR         13
+#define EXCCAUSE_INSTR_ADDR_ERROR              14
+#define EXCCAUSE_LOAD_STORE_ADDR_ERROR         15
 #define EXCCAUSE_ITLB_MISS                     16
 #define EXCCAUSE_ITLB_MULTIHIT                 17
 #define EXCCAUSE_ITLB_PRIVILEGE                        18
 #define DEBUGCAUSE_ICOUNT_BIT          0       /* ICOUNT would incr. to zero */
 
 #endif /* _XTENSA_SPECREG_H */
-
index 8ff23649581b7e1d3565463f60d08b10ec08759d..03975906b36fc34dc6a47abbe979c899ddc4f3e0 100644 (file)
 #ifndef _XTENSA_SPINLOCK_H
 #define _XTENSA_SPINLOCK_H
 
-#include <linux/spinlock.h>
+/*
+ * spinlock
+ *
+ * There is at most one owner of a spinlock.  There are not different
+ * types of spinlock owners like there are for rwlocks (see below).
+ *
+ * When trying to obtain a spinlock, the function "spins" forever, or busy-
+ * waits, until the lock is obtained.  When spinning, presumably some other
+ * owner will soon give up the spinlock making it available to others.  Use
+ * the trylock functions to avoid spinning forever.
+ *
+ * possible values:
+ *
+ *    0         nobody owns the spinlock
+ *    1         somebody owns the spinlock
+ */
+
+#define __raw_spin_is_locked(x) ((x)->slock != 0)
+#define __raw_spin_unlock_wait(lock) \
+       do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
+
+#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
+
+static inline void __raw_spin_lock(raw_spinlock_t *lock)
+{
+       unsigned long tmp;
+
+       __asm__ __volatile__(
+                       "       movi    %0, 0\n"
+                       "       wsr     %0, scompare1\n"
+                       "1:     movi    %0, 1\n"
+                       "       s32c1i  %0, %1, 0\n"
+                       "       bnez    %0, 1b\n"
+                       : "=&a" (tmp)
+                       : "a" (&lock->slock)
+                       : "memory");
+}
+
+/* Returns 1 if the lock is obtained, 0 otherwise. */
+
+static inline int __raw_spin_trylock(raw_spinlock_t *lock)
+{
+       unsigned long tmp;
+
+       __asm__ __volatile__(
+                       "       movi    %0, 0\n"
+                       "       wsr     %0, scompare1\n"
+                       "       movi    %0, 1\n"
+                       "       s32c1i  %0, %1, 0\n"
+                       : "=&a" (tmp)
+                       : "a" (&lock->slock)
+                       : "memory");
+
+       return tmp == 0 ? 1 : 0;
+}
+
+static inline void __raw_spin_unlock(raw_spinlock_t *lock)
+{
+       unsigned long tmp;
+
+       __asm__ __volatile__(
+                       "       movi    %0, 0\n"
+                       "       s32ri   %0, %1, 0\n"
+                       : "=&a" (tmp)
+                       : "a" (&lock->slock)
+                       : "memory");
+}
+
+/*
+ * rwlock
+ *
+ * Read-write locks are really a more flexible spinlock.  They allow
+ * multiple readers but only one writer.  Write ownership is exclusive
+ * (i.e., all other readers and writers are blocked from ownership while
+ * there is a write owner).  These rwlocks are unfair to writers.  Writers
+ * can be starved for an indefinite time by readers.
+ *
+ * possible values:
+ *
+ *   0          nobody owns the rwlock
+ *  >0          one or more readers own the rwlock
+ *                (the positive value is the actual number of readers)
+ *  0x80000000  one writer owns the rwlock, no other writers, no readers
+ */
+
+#define __raw_write_can_lock(x)  ((x)->lock == 0)
+
+static inline void __raw_write_lock(raw_rwlock_t *rw)
+{
+       unsigned long tmp;
+
+       __asm__ __volatile__(
+                       "       movi    %0, 0\n"
+                       "       wsr     %0, scompare1\n"
+                       "1:     movi    %0, 1\n"
+                       "       slli    %0, %0, 31\n"
+                       "       s32c1i  %0, %1, 0\n"
+                       "       bnez    %0, 1b\n"
+                       : "=&a" (tmp)
+                       : "a" (&rw->lock)
+                       : "memory");
+}
+
+/* Returns 1 if the lock is obtained, 0 otherwise. */
+
+static inline int __raw_write_trylock(raw_rwlock_t *rw)
+{
+       unsigned long tmp;
+
+       __asm__ __volatile__(
+                       "       movi    %0, 0\n"
+                       "       wsr     %0, scompare1\n"
+                       "       movi    %0, 1\n"
+                       "       slli    %0, %0, 31\n"
+                       "       s32c1i  %0, %1, 0\n"
+                       : "=&a" (tmp)
+                       : "a" (&rw->lock)
+                       : "memory");
+
+       return tmp == 0 ? 1 : 0;
+}
+
+static inline void __raw_write_unlock(raw_rwlock_t *rw)
+{
+       unsigned long tmp;
+
+       __asm__ __volatile__(
+                       "       movi    %0, 0\n"
+                       "       s32ri   %0, %1, 0\n"
+                       : "=&a" (tmp)
+                       : "a" (&rw->lock)
+                       : "memory");
+}
+
+static inline void __raw_read_lock(raw_rwlock_t *rw)
+{
+       unsigned long tmp;
+       unsigned long result;
+
+       __asm__ __volatile__(
+                       "1:     l32i    %1, %2, 0\n"
+                       "       bltz    %1, 1b\n"
+                       "       wsr     %1, scompare1\n"
+                       "       addi    %0, %1, 1\n"
+                       "       s32c1i  %0, %2, 0\n"
+                       "       bne     %0, %1, 1b\n"
+                       : "=&a" (result), "=&a" (tmp)
+                       : "a" (&rw->lock)
+                       : "memory");
+}
+
+/* Returns 1 if the lock is obtained, 0 otherwise. */
+
+static inline int __raw_read_trylock(raw_rwlock_t *rw)
+{
+       unsigned long result;
+       unsigned long tmp;
+
+       __asm__ __volatile__(
+                       "       l32i    %1, %2, 0\n"
+                       "       addi    %0, %1, 1\n"
+                       "       bltz    %0, 1f\n"
+                       "       wsr     %1, scompare1\n"
+                       "       s32c1i  %0, %2, 0\n"
+                       "       sub     %0, %0, %1\n"
+                       "1:\n"
+                       : "=&a" (result), "=&a" (tmp)
+                       : "a" (&rw->lock)
+                       : "memory");
+
+       return result == 0;
+}
+
+static inline void __raw_read_unlock(raw_rwlock_t *rw)
+{
+       unsigned long tmp1, tmp2;
+
+       __asm__ __volatile__(
+                       "1:     l32i    %1, %2, 0\n"
+                       "       addi    %0, %1, -1\n"
+                       "       wsr     %1, scompare1\n"
+                       "       s32c1i  %0, %2, 0\n"
+                       "       bne     %0, %1, 1b\n"
+                       : "=&a" (tmp1), "=&a" (tmp2)
+                       : "a" (&rw->lock)
+                       : "memory");
+}
 
 #endif /* _XTENSA_SPINLOCK_H */
index b00c928d4cce44d8316fa838bf0c240d7ea5f535..8d5e47fad0958160abcc117c9f5f1da3c7c5ae50 100644 (file)
@@ -25,9 +25,10 @@ asmlinkage long xtensa_fadvise64_64(int, int,
 /* Should probably move to linux/syscalls.h */
 struct pollfd;
 asmlinkage long sys_pselect6(int n, fd_set __user *inp, fd_set __user *outp,
-       fd_set __user *exp, struct timespec __user *tsp, void __user *sig);
+                            fd_set __user *exp, struct timespec __user *tsp,
+                            void __user *sig);
 asmlinkage long sys_ppoll(struct pollfd __user *ufds, unsigned int nfds,
-       struct timespec __user *tsp, const sigset_t __user *sigmask,
-       size_t sigsetsize);
-asmlinkage long sys_rt_sigsuspend(sigset_t __user *unewset,
-               size_t sigsetsize);
+                         struct timespec __user *tsp,
+                         const sigset_t __user *sigmask,
+                         size_t sigsetsize);
+asmlinkage long sys_rt_sigsuspend(sigset_t __user *unewset, size_t sigsetsize);
diff --git a/arch/xtensa/include/asm/traps.h b/arch/xtensa/include/asm/traps.h
new file mode 100644 (file)
index 0000000..54f7044
--- /dev/null
@@ -0,0 +1,23 @@
+/*
+ * arch/xtensa/include/asm/traps.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2012 Tensilica Inc.
+ */
+#ifndef _XTENSA_TRAPS_H
+#define _XTENSA_TRAPS_H
+
+#include <asm/ptrace.h>
+
+/*
+ * handler must be either of the following:
+ *  void (*)(struct pt_regs *regs);
+ *  void (*)(struct pt_regs *regs, unsigned long exccause);
+ */
+extern void * __init trap_set_handler(int cause, void *handler);
+extern void do_unhandled(struct pt_regs *regs, unsigned long exccause);
+
+#endif /* _XTENSA_TRAPS_H */
index 6e4bb3b791ab709c221840a5d6987f7067b268d1..fd686dc45d1a95b5016de15341c6d3fe173837fe 100644 (file)
 #define segment_eq(a,b)        ((a).seg == (b).seg)
 
 #define __kernel_ok (segment_eq(get_fs(), KERNEL_DS))
-#define __user_ok(addr,size) (((size) <= TASK_SIZE)&&((addr) <= TASK_SIZE-(size)))
+#define __user_ok(addr,size) \
+               (((size) <= TASK_SIZE)&&((addr) <= TASK_SIZE-(size)))
 #define __access_ok(addr,size) (__kernel_ok || __user_ok((addr),(size)))
 #define access_ok(type,addr,size) __access_ok((unsigned long)(addr),(size))
 
@@ -234,10 +235,10 @@ do {                                                                      \
        int __cb;                                                       \
        retval = 0;                                                     \
        switch (size) {                                                 \
-        case 1: __put_user_asm(x,ptr,retval,1,"s8i",__cb);  break;     \
-        case 2: __put_user_asm(x,ptr,retval,2,"s16i",__cb); break;     \
-        case 4: __put_user_asm(x,ptr,retval,4,"s32i",__cb); break;     \
-        case 8: {                                                      \
+       case 1: __put_user_asm(x,ptr,retval,1,"s8i",__cb);  break;      \
+       case 2: __put_user_asm(x,ptr,retval,2,"s16i",__cb); break;      \
+       case 4: __put_user_asm(x,ptr,retval,4,"s32i",__cb); break;      \
+       case 8: {                                                       \
                     __typeof__(*ptr) __v64 = x;                        \
                     retval = __copy_to_user(ptr,&__v64,8);             \
                     break;                                             \
@@ -291,7 +292,7 @@ do {                                                                        \
  * __check_align_* macros still work.
  */
 #define __put_user_asm(x, addr, err, align, insn, cb)  \
-   __asm__ __volatile__(                               \
+__asm__ __volatile__(                                  \
        __check_align_##align                           \
        "1: "insn"  %2, %3, 0           \n"             \
        "2:                             \n"             \
@@ -301,8 +302,8 @@ do {                                                                        \
        "   .long  2b                   \n"             \
        "5:                             \n"             \
        "   l32r   %1, 4b               \n"             \
-        "   movi   %0, %4              \n"             \
-        "   jx     %1                  \n"             \
+       "   movi   %0, %4               \n"             \
+       "   jx     %1                   \n"             \
        "   .previous                   \n"             \
        "   .section  __ex_table,\"a\"  \n"             \
        "   .long       1b, 5b          \n"             \
@@ -334,13 +335,13 @@ extern long __get_user_bad(void);
 do {                                                                   \
        int __cb;                                                       \
        retval = 0;                                                     \
-        switch (size) {                                                        \
-          case 1: __get_user_asm(x,ptr,retval,1,"l8ui",__cb);  break;  \
-          case 2: __get_user_asm(x,ptr,retval,2,"l16ui",__cb); break;  \
-          case 4: __get_user_asm(x,ptr,retval,4,"l32i",__cb);  break;  \
-          case 8: retval = __copy_from_user(&x,ptr,8);    break;       \
-          default: (x) = __get_user_bad();                             \
-        }                                                              \
+       switch (size) {                                                 \
+       case 1: __get_user_asm(x,ptr,retval,1,"l8ui",__cb);  break;     \
+       case 2: __get_user_asm(x,ptr,retval,2,"l16ui",__cb); break;     \
+       case 4: __get_user_asm(x,ptr,retval,4,"l32i",__cb);  break;     \
+       case 8: retval = __copy_from_user(&x,ptr,8);    break;  \
+       default: (x) = __get_user_bad();                                \
+                                                                     \
 } while (0)
 
 
@@ -349,7 +350,7 @@ do {                                                                        \
  * __check_align_* macros still work.
  */
 #define __get_user_asm(x, addr, err, align, insn, cb) \
-   __asm__ __volatile__(                       \
+__asm__ __volatile__(                  \
        __check_align_##align                   \
        "1: "insn"  %2, %3, 0           \n"     \
        "2:                             \n"     \
@@ -360,8 +361,8 @@ do {                                                                        \
        "5:                             \n"     \
        "   l32r   %1, 4b               \n"     \
        "   movi   %2, 0                \n"     \
-        "   movi   %0, %4              \n"     \
-        "   jx     %1                  \n"     \
+       "   movi   %0, %4               \n"     \
+       "   jx     %1                   \n"     \
        "   .previous                   \n"     \
        "   .section  __ex_table,\"a\"  \n"     \
        "   .long       1b, 5b          \n"     \
@@ -421,8 +422,10 @@ __generic_copy_from_user(void *to, const void *from, unsigned long n)
 
 #define copy_to_user(to,from,n) __generic_copy_to_user((to),(from),(n))
 #define copy_from_user(to,from,n) __generic_copy_from_user((to),(from),(n))
-#define __copy_to_user(to,from,n) __generic_copy_to_user_nocheck((to),(from),(n))
-#define __copy_from_user(to,from,n) __generic_copy_from_user_nocheck((to),(from),(n))
+#define __copy_to_user(to,from,n) \
+       __generic_copy_to_user_nocheck((to),(from),(n))
+#define __copy_from_user(to,from,n) \
+       __generic_copy_from_user_nocheck((to),(from),(n))
 #define __copy_to_user_inatomic __copy_to_user
 #define __copy_from_user_inatomic __copy_from_user
 
index f36cef5a62ff74a08ac9e0a9039153dfb26f5398..c3a59d992ac0378b28d86e176431710f5dfdec8f 100644 (file)
@@ -23,13 +23,13 @@ obj-$(CONFIG_MODULES) += xtensa_ksyms.o module.o
 #
 # Replicate rules in scripts/Makefile.build
 
-sed-y = -e 's/\*(\(\.[a-z]*it\|\.ref\|\)\.text)/*(\1.literal \1.text)/g'    \
-       -e 's/\.text\.unlikely/.literal.unlikely .text.unlikely/g' \
+sed-y = -e 's/\*(\(\.[a-z]*it\|\.ref\|\)\.text)/*(\1.literal \1.text)/g' \
+       -e 's/\.text\.unlikely/.literal.unlikely .text.unlikely/g'       \
        -e 's/\*(\(\.text\.[a-z]*\))/*(\1.literal \1)/g'
 
 quiet_cmd__cpp_lds_S = LDS     $@
-      cmd__cpp_lds_S = $(CPP) $(cpp_flags) -P -C -Uxtensa -D__ASSEMBLY__ $< \
-                       | sed $(sed-y) >$@
+cmd__cpp_lds_S = $(CPP) $(cpp_flags) -P -C -Uxtensa -D__ASSEMBLY__ $<    \
+                 | sed $(sed-y) >$@
 
 $(obj)/vmlinux.lds: $(src)/vmlinux.lds.S FORCE
        $(call if_changed_dep,_cpp_lds_S)
index 934ae58e2c79766f46cba80ac12ed63649faae9b..aa2e87b8566a7dbabb7c0227ea6a8f489674ab05 100644 (file)
@@ -442,7 +442,7 @@ ENTRY(fast_unaligned)
        mov     a1, a2
 
        rsr     a0, ps
-        bbsi.l  a2, PS_UM_BIT, 1f     # jump if user mode
+       bbsi.l  a2, PS_UM_BIT, 1f     # jump if user mode
 
        movi    a0, _kernel_exception
        jx      a0
@@ -450,6 +450,6 @@ ENTRY(fast_unaligned)
 1:     movi    a0, _user_exception
        jx      a0
 
+ENDPROC(fast_unaligned)
 
 #endif /* XCHAL_UNALIGNED_LOAD_EXCEPTION || XCHAL_UNALIGNED_STORE_EXCEPTION */
-
index 7dc3f91571856e0eabe7e1e791d527e024a0280e..0701fad170db5b0ab4eb4bd7fddf07463d424558 100644 (file)
@@ -41,6 +41,7 @@ int main(void)
        DEFINE(PT_SAR, offsetof (struct pt_regs, sar));
        DEFINE(PT_ICOUNTLEVEL, offsetof (struct pt_regs, icountlevel));
        DEFINE(PT_SYSCALL, offsetof (struct pt_regs, syscall));
+       DEFINE(PT_SCOMPARE1, offsetof(struct pt_regs, scompare1));
        DEFINE(PT_AREG, offsetof (struct pt_regs, areg[0]));
        DEFINE(PT_AREG0, offsetof (struct pt_regs, areg[0]));
        DEFINE(PT_AREG1, offsetof (struct pt_regs, areg[1]));
@@ -91,7 +92,8 @@ int main(void)
 #endif
        DEFINE(THREAD_XTREGS_USER, offsetof (struct thread_info, xtregs_user));
        DEFINE(XTREGS_USER_SIZE, sizeof(xtregs_user_t));
-       DEFINE(THREAD_CURRENT_DS, offsetof (struct task_struct, thread.current_ds));
+       DEFINE(THREAD_CURRENT_DS, offsetof (struct task_struct, \
+              thread.current_ds));
 
        /* struct mm_struct */
        DEFINE(MM_USERS, offsetof(struct mm_struct, mm_users));
@@ -108,4 +110,3 @@ int main(void)
 
        return 0;
 }
-
index 54c3be313bfa8141e79f84606f8f3d6093d6946f..647657484866dde30f8dd92217c3cb719fc31bea 100644 (file)
 /* IO protection is currently unsupported. */
 
 ENTRY(fast_io_protect)
+
        wsr     a0, excsave1
        movi    a0, unrecoverable_exception
        callx0  a0
 
+ENDPROC(fast_io_protect)
+
 #if XTENSA_HAVE_COPROCESSORS
 
 /*
@@ -139,6 +142,7 @@ ENTRY(fast_io_protect)
  */
 
 ENTRY(coprocessor_save)
+
        entry   a1, 32
        s32i    a0, a1, 0
        movi    a0, .Lsave_cp_regs_jump_table
@@ -150,7 +154,10 @@ ENTRY(coprocessor_save)
 1:     l32i    a0, a1, 0
        retw
 
+ENDPROC(coprocessor_save)
+
 ENTRY(coprocessor_load)
+
        entry   a1, 32
        s32i    a0, a1, 0
        movi    a0, .Lload_cp_regs_jump_table
@@ -162,8 +169,10 @@ ENTRY(coprocessor_load)
 1:     l32i    a0, a1, 0
        retw
 
+ENDPROC(coprocessor_load)
+
 /*
- * coprocessor_flush(struct task_info*, index) 
+ * coprocessor_flush(struct task_info*, index)
  *                             a2        a3
  * coprocessor_restore(struct task_info*, index)
  *                              a2         a3
@@ -178,6 +187,7 @@ ENTRY(coprocessor_load)
 
 
 ENTRY(coprocessor_flush)
+
        entry   a1, 32
        s32i    a0, a1, 0
        movi    a0, .Lsave_cp_regs_jump_table
@@ -191,6 +201,8 @@ ENTRY(coprocessor_flush)
 1:     l32i    a0, a1, 0
        retw
 
+ENDPROC(coprocessor_flush)
+
 ENTRY(coprocessor_restore)
        entry   a1, 32
        s32i    a0, a1, 0
@@ -205,6 +217,8 @@ ENTRY(coprocessor_restore)
 1:     l32i    a0, a1, 0
        retw
 
+ENDPROC(coprocessor_restore)
+
 /*
  * Entry condition:
  *
@@ -220,10 +234,12 @@ ENTRY(coprocessor_restore)
  */
 
 ENTRY(fast_coprocessor_double)
+
        wsr     a0, excsave1
        movi    a0, unrecoverable_exception
        callx0  a0
 
+ENDPROC(fast_coprocessor_double)
 
 ENTRY(fast_coprocessor)
 
@@ -327,9 +343,14 @@ ENTRY(fast_coprocessor)
 
        rfe
 
+ENDPROC(fast_coprocessor)
+
        .data
+
 ENTRY(coprocessor_owner)
+
        .fill XCHAL_CP_MAX, 4, 0
 
-#endif /* XTENSA_HAVE_COPROCESSORS */
+END(coprocessor_owner)
 
+#endif /* XTENSA_HAVE_COPROCESSORS */
index 90bfc1dbc13dcf46992e4fb09bb7eab3cfe1bea3..3777fec85e7cac69911eae8eeee2899a29df5e68 100644 (file)
@@ -219,6 +219,7 @@ _user_exception:
 
        j       common_exception
 
+ENDPROC(user_exception)
 
 /*
  * First-level exit handler for kernel exceptions
@@ -371,6 +372,13 @@ common_exception:
        s32i    a2, a1, PT_LBEG
        s32i    a3, a1, PT_LEND
 
+       /* Save SCOMPARE1 */
+
+#if XCHAL_HAVE_S32C1I
+       rsr     a2, scompare1
+       s32i    a2, a1, PT_SCOMPARE1
+#endif
+
        /* Save optional registers. */
 
        save_xtregs_opt a1 a2 a4 a5 a6 a7 PT_XTREGS_OPT
@@ -432,6 +440,12 @@ common_exception_return:
 
        load_xtregs_opt a1 a2 a4 a5 a6 a7 PT_XTREGS_OPT
 
+       /* Restore SCOMPARE1 */
+
+#if XCHAL_HAVE_S32C1I
+       l32i    a2, a1, PT_SCOMPARE1
+       wsr     a2, scompare1
+#endif
        wsr     a3, ps          /* disable interrupts */
 
        _bbci.l a3, PS_UM_BIT, kernel_exception_exit
@@ -641,6 +655,8 @@ common_exception_exit:
        l32i    a1, a1, PT_AREG1
        rfde
 
+ENDPROC(kernel_exception)
+
 /*
  * Debug exception handler.
  *
@@ -701,6 +717,7 @@ ENTRY(debug_exception)
        /* Debug exception while in exception mode. */
 1:     j       1b      // FIXME!!
 
+ENDPROC(debug_exception)
 
 /*
  * We get here in case of an unrecoverable exception.
@@ -751,6 +768,7 @@ ENTRY(unrecoverable_exception)
 
 1:     j       1b
 
+ENDPROC(unrecoverable_exception)
 
 /* -------------------------- FAST EXCEPTION HANDLERS ----------------------- */
 
@@ -856,7 +874,7 @@ ENTRY(fast_alloca)
 
        _bnei   a0, 1, 1f               # no 'movsp a1, ax': jump
 
-        /* Move the save area. This implies the use of the L32E
+       /* Move the save area. This implies the use of the L32E
         * and S32E instructions, because this move must be done with
         * the user's PS.RING privilege levels, not with ring 0
         * (kernel's) privileges currently active with PS.EXCM
@@ -929,6 +947,7 @@ ENTRY(fast_alloca)
        l32i    a2, a2, PT_AREG2
        rfe
 
+ENDPROC(fast_alloca)
 
 /*
  * fast system calls.
@@ -966,6 +985,8 @@ ENTRY(fast_syscall_kernel)
 
        j       kernel_exception
 
+ENDPROC(fast_syscall_kernel)
+
 ENTRY(fast_syscall_user)
 
        /* Skip syscall. */
@@ -983,19 +1004,21 @@ ENTRY(fast_syscall_user)
 
        j       user_exception
 
-ENTRY(fast_syscall_unrecoverable)
+ENDPROC(fast_syscall_user)
 
-        /* Restore all states. */
+ENTRY(fast_syscall_unrecoverable)
 
-        l32i    a0, a2, PT_AREG0        # restore a0
-        xsr     a2, depc                # restore a2, depc
-        rsr     a3, excsave1
+       /* Restore all states. */
 
-        wsr     a0, excsave1
-        movi    a0, unrecoverable_exception
-        callx0  a0
+       l32i    a0, a2, PT_AREG0        # restore a0
+       xsr     a2, depc                # restore a2, depc
+       rsr     a3, excsave1
 
+       wsr     a0, excsave1
+       movi    a0, unrecoverable_exception
+       callx0  a0
 
+ENDPROC(fast_syscall_unrecoverable)
 
 /*
  * sysxtensa syscall handler
@@ -1101,7 +1124,7 @@ CATCH
        movi    a2, -EINVAL
        rfe
 
-
+ENDPROC(fast_syscall_xtensa)
 
 
 /* fast_syscall_spill_registers.
@@ -1160,6 +1183,8 @@ ENTRY(fast_syscall_spill_registers)
        movi    a2, 0
        rfe
 
+ENDPROC(fast_syscall_spill_registers)
+
 /* Fixup handler.
  *
  * We get here if the spill routine causes an exception, e.g. tlb miss.
@@ -1228,9 +1253,9 @@ fast_syscall_spill_registers_fixup:
 
        movi    a3, exc_table
        rsr     a0, exccause
-        addx4  a0, a0, a3                      # find entry in table
-        l32i   a0, a0, EXC_TABLE_FAST_USER     # load handler
-        jx     a0
+       addx4   a0, a0, a3                      # find entry in table
+       l32i    a0, a0, EXC_TABLE_FAST_USER     # load handler
+       jx      a0
 
 fast_syscall_spill_registers_fixup_return:
 
@@ -1432,7 +1457,7 @@ ENTRY(_spill_registers)
        rsr     a0, ps
        _bbci.l a0, PS_UM_BIT, 1f
 
-       /* User space: Setup a dummy frame and kill application.
+       /* User space: Setup a dummy frame and kill application.
         * Note: We assume EXC_TABLE_KSTK contains a valid stack pointer.
         */
 
@@ -1464,6 +1489,8 @@ ENTRY(_spill_registers)
        callx0  a0              # should not return
 1:     j       1b
 
+ENDPROC(_spill_registers)
+
 #ifdef CONFIG_MMU
 /*
  * We should never get here. Bail out!
@@ -1475,6 +1502,8 @@ ENTRY(fast_second_level_miss_double_kernel)
        callx0  a0              # should not return
 1:     j       1b
 
+ENDPROC(fast_second_level_miss_double_kernel)
+
 /* First-level entry handler for user, kernel, and double 2nd-level
  * TLB miss exceptions.  Note that for now, user and kernel miss
  * exceptions share the same entry point and are handled identically.
@@ -1682,6 +1711,7 @@ ENTRY(fast_second_level_miss)
        j       _kernel_exception
 1:     j       _user_exception
 
+ENDPROC(fast_second_level_miss)
 
 /*
  * StoreProhibitedException
@@ -1777,6 +1807,9 @@ ENTRY(fast_store_prohibited)
        bbsi.l  a2, PS_UM_BIT, 1f
        j       _kernel_exception
 1:     j       _user_exception
+
+ENDPROC(fast_store_prohibited)
+
 #endif /* CONFIG_MMU */
 
 /*
@@ -1787,6 +1820,7 @@ ENTRY(fast_store_prohibited)
  */
 
 ENTRY(system_call)
+
        entry   a1, 32
 
        /* regs->syscall = regs->areg[2] */
@@ -1831,6 +1865,8 @@ ENTRY(system_call)
        callx4  a4
        retw
 
+ENDPROC(system_call)
+
 
 /*
  * Task switch.
@@ -1899,6 +1935,7 @@ ENTRY(_switch_to)
 
        retw
 
+ENDPROC(_switch_to)
 
 ENTRY(ret_from_fork)
 
@@ -1914,6 +1951,8 @@ ENTRY(ret_from_fork)
 
        j       common_exception_return
 
+ENDPROC(ret_from_fork)
+
 /*
  * Kernel thread creation helper
  * On entry, set up by copy_thread: a2 = thread_fn, a3 = thread_fn arg
index bdc50788f35e13e9e4d89b54e65af887f1a26610..91d9095284dee76104b1be0b2e8ecc129885e32f 100644 (file)
@@ -18,6 +18,7 @@
 #include <asm/processor.h>
 #include <asm/page.h>
 #include <asm/cacheasm.h>
+#include <asm/initialize_mmu.h>
 
 #include <linux/init.h>
 #include <linux/linkage.h>
         */
 
        __HEAD
-       .globl _start
-_start:        _j      2f
+ENTRY(_start)
+
+       _j      2f
        .align  4
 1:     .word   _startup
 2:     l32r    a0, 1b
        jx      a0
 
+ENDPROC(_start)
+
        .section .init.text, "ax"
-       .align 4
-_startup:
+
+ENTRY(_startup)
 
        /* Disable interrupts and exceptions. */
 
@@ -107,7 +111,7 @@ _startup:
        /* Disable all timers. */
 
        .set    _index, 0
-       .rept   XCHAL_NUM_TIMERS - 1
+       .rept   XCHAL_NUM_TIMERS
        wsr     a0, SREG_CCOMPARE + _index
        .set    _index, _index + 1
        .endr
@@ -120,7 +124,7 @@ _startup:
 
        /* Disable coprocessors. */
 
-#if XCHAL_CP_NUM > 0
+#if XCHAL_HAVE_CP
        wsr     a0, cpenable
 #endif
 
@@ -152,6 +156,8 @@ _startup:
 
        isync
 
+       initialize_mmu
+
        /* Unpack data sections
         *
         * The linker script used to build the Linux kernel image
@@ -230,6 +236,7 @@ _startup:
 should_never_return:
        j       should_never_return
 
+ENDPROC(_startup)
 
 /*
  * BSS section
@@ -239,6 +246,8 @@ __PAGE_ALIGNED_BSS
 #ifdef CONFIG_MMU
 ENTRY(swapper_pg_dir)
        .fill   PAGE_SIZE, 1, 0
+END(swapper_pg_dir)
 #endif
 ENTRY(empty_zero_page)
        .fill   PAGE_SIZE, 1, 0
+END(empty_zero_page)
index a6ce3e563739f1b56d34eea2a0c2f770159c9f46..6f4f9749cff773f229a76a35bf50373ec18731ab 100644 (file)
@@ -18,6 +18,8 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/kernel_stat.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
 
 #include <asm/uaccess.h>
 #include <asm/platform.h>
@@ -26,19 +28,22 @@ static unsigned int cached_irq_mask;
 
 atomic_t irq_err_count;
 
+static struct irq_domain *root_domain;
+
 /*
  * do_IRQ handles all normal device IRQ's (the special
  * SMP cross-CPU interrupts have their own specific
  * handlers).
  */
 
-asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
+asmlinkage void do_IRQ(int hwirq, struct pt_regs *regs)
 {
        struct pt_regs *old_regs = set_irq_regs(regs);
+       int irq = irq_find_mapping(root_domain, hwirq);
 
-       if (irq >= NR_IRQS) {
+       if (hwirq >= NR_IRQS) {
                printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
-                               __func__, irq);
+                               __func__, hwirq);
        }
 
        irq_enter();
@@ -71,40 +76,39 @@ int arch_show_interrupts(struct seq_file *p, int prec)
 
 static void xtensa_irq_mask(struct irq_data *d)
 {
-       cached_irq_mask &= ~(1 << d->irq);
+       cached_irq_mask &= ~(1 << d->hwirq);
        set_sr (cached_irq_mask, intenable);
 }
 
 static void xtensa_irq_unmask(struct irq_data *d)
 {
-       cached_irq_mask |= 1 << d->irq;
+       cached_irq_mask |= 1 << d->hwirq;
        set_sr (cached_irq_mask, intenable);
 }
 
 static void xtensa_irq_enable(struct irq_data *d)
 {
-       variant_irq_enable(d->irq);
+       variant_irq_enable(d->hwirq);
        xtensa_irq_unmask(d);
 }
 
 static void xtensa_irq_disable(struct irq_data *d)
 {
        xtensa_irq_mask(d);
-       variant_irq_disable(d->irq);
+       variant_irq_disable(d->hwirq);
 }
 
 static void xtensa_irq_ack(struct irq_data *d)
 {
-       set_sr(1 << d->irq, intclear);
+       set_sr(1 << d->hwirq, intclear);
 }
 
 static int xtensa_irq_retrigger(struct irq_data *d)
 {
-       set_sr (1 << d->irq, INTSET);
+       set_sr(1 << d->hwirq, intset);
        return 1;
 }
 
-
 static struct irq_chip xtensa_irq_chip = {
        .name           = "xtensa",
        .irq_enable     = xtensa_irq_enable,
@@ -115,37 +119,99 @@ static struct irq_chip xtensa_irq_chip = {
        .irq_retrigger  = xtensa_irq_retrigger,
 };
 
-void __init init_IRQ(void)
+static int xtensa_irq_map(struct irq_domain *d, unsigned int irq,
+               irq_hw_number_t hw)
 {
-       int index;
-
-       for (index = 0; index < XTENSA_NR_IRQS; index++) {
-               int mask = 1 << index;
-
-               if (mask & XCHAL_INTTYPE_MASK_SOFTWARE)
-                       irq_set_chip_and_handler(index, &xtensa_irq_chip,
-                                                handle_simple_irq);
+       u32 mask = 1 << hw;
+
+       if (mask & XCHAL_INTTYPE_MASK_SOFTWARE) {
+               irq_set_chip_and_handler_name(irq, &xtensa_irq_chip,
+                               handle_simple_irq, "level");
+               irq_set_status_flags(irq, IRQ_LEVEL);
+       } else if (mask & XCHAL_INTTYPE_MASK_EXTERN_EDGE) {
+               irq_set_chip_and_handler_name(irq, &xtensa_irq_chip,
+                               handle_edge_irq, "edge");
+               irq_clear_status_flags(irq, IRQ_LEVEL);
+       } else if (mask & XCHAL_INTTYPE_MASK_EXTERN_LEVEL) {
+               irq_set_chip_and_handler_name(irq, &xtensa_irq_chip,
+                               handle_level_irq, "level");
+               irq_set_status_flags(irq, IRQ_LEVEL);
+       } else if (mask & XCHAL_INTTYPE_MASK_TIMER) {
+               irq_set_chip_and_handler_name(irq, &xtensa_irq_chip,
+                               handle_edge_irq, "edge");
+               irq_clear_status_flags(irq, IRQ_LEVEL);
+       } else {/* XCHAL_INTTYPE_MASK_WRITE_ERROR */
+               /* XCHAL_INTTYPE_MASK_NMI */
+
+               irq_set_chip_and_handler_name(irq, &xtensa_irq_chip,
+                               handle_level_irq, "level");
+               irq_set_status_flags(irq, IRQ_LEVEL);
+       }
+       return 0;
+}
 
-               else if (mask & XCHAL_INTTYPE_MASK_EXTERN_EDGE)
-                       irq_set_chip_and_handler(index, &xtensa_irq_chip,
-                                                handle_edge_irq);
+static unsigned map_ext_irq(unsigned ext_irq)
+{
+       unsigned mask = XCHAL_INTTYPE_MASK_EXTERN_EDGE |
+               XCHAL_INTTYPE_MASK_EXTERN_LEVEL;
+       unsigned i;
 
-               else if (mask & XCHAL_INTTYPE_MASK_EXTERN_LEVEL)
-                       irq_set_chip_and_handler(index, &xtensa_irq_chip,
-                                                handle_level_irq);
+       for (i = 0; mask; ++i, mask >>= 1) {
+               if ((mask & 1) && ext_irq-- == 0)
+                       return i;
+       }
+       return XCHAL_NUM_INTERRUPTS;
+}
 
-               else if (mask & XCHAL_INTTYPE_MASK_TIMER)
-                       irq_set_chip_and_handler(index, &xtensa_irq_chip,
-                                                handle_edge_irq);
+/*
+ * Device Tree IRQ specifier translation function which works with one or
+ * two cell bindings. First cell value maps directly to the hwirq number.
+ * Second cell if present specifies whether hwirq number is external (1) or
+ * internal (0).
+ */
+int xtensa_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
+               const u32 *intspec, unsigned int intsize,
+               unsigned long *out_hwirq, unsigned int *out_type)
+{
+       if (WARN_ON(intsize < 1 || intsize > 2))
+               return -EINVAL;
+       if (intsize == 2 && intspec[1] == 1) {
+               unsigned int_irq = map_ext_irq(intspec[0]);
+               if (int_irq < XCHAL_NUM_INTERRUPTS)
+                       *out_hwirq = int_irq;
+               else
+                       return -EINVAL;
+       } else {
+               *out_hwirq = intspec[0];
+       }
+       *out_type = IRQ_TYPE_NONE;
+       return 0;
+}
 
-               else    /* XCHAL_INTTYPE_MASK_WRITE_ERROR */
-                       /* XCHAL_INTTYPE_MASK_NMI */
+static const struct irq_domain_ops xtensa_irq_domain_ops = {
+       .xlate = xtensa_irq_domain_xlate,
+       .map = xtensa_irq_map,
+};
 
-                       irq_set_chip_and_handler(index, &xtensa_irq_chip,
-                                                handle_level_irq);
-       }
+void __init init_IRQ(void)
+{
+       struct device_node *intc = NULL;
 
        cached_irq_mask = 0;
+       set_sr(~0, intclear);
+
+#ifdef CONFIG_OF
+       /* The interrupt controller device node is mandatory */
+       intc = of_find_compatible_node(NULL, NULL, "xtensa,pic");
+       BUG_ON(!intc);
+
+       root_domain = irq_domain_add_linear(intc, NR_IRQS,
+                       &xtensa_irq_domain_ops, NULL);
+#else
+       root_domain = irq_domain_add_legacy(intc, NR_IRQS, 0, 0,
+                       &xtensa_irq_domain_ops, NULL);
+#endif
+       irq_set_default_host(root_domain);
 
        variant_init_irq();
 }
index 451dda928c934539b2733545686fff1ee2058288..b715237bae61e4a7509fe77e8c734726c0a71f0d 100644 (file)
@@ -53,7 +53,7 @@ int apply_relocate_add(Elf32_Shdr *sechdrs,
                       struct module *mod)
 {
        unsigned int i;
-        Elf32_Rela *rela = (void *)sechdrs[relsec].sh_addr;
+       Elf32_Rela *rela = (void *)sechdrs[relsec].sh_addr;
        Elf32_Sym *sym;
        unsigned char *location;
        uint32_t value;
index 97230e46cbe77d1439b51154233ff54ba17c67c3..44bf21c3769a17df99a51032dac639142c9e0be5 100644 (file)
@@ -44,4 +44,3 @@ _F(void, calibrate_ccount, (void),
        ccount_per_jiffy = 10 * (1000000UL/HZ);
 });
 #endif
-
index 1accf28da5f571722aba9e1de23d57c7defbedbe..0dd5784416d307972bcfd710ab54620ef0fa0067 100644 (file)
@@ -108,7 +108,7 @@ void coprocessor_flush_all(struct thread_info *ti)
 
 void cpu_idle(void)
 {
-       local_irq_enable();
+       local_irq_enable();
 
        /* endless idle loop with no priority at all */
        while (1) {
index 33eea4c16f121bde393508ed132bab7bd4d16d47..61fb2e9e903561954878c9cffc6b3e5a09577e32 100644 (file)
@@ -154,7 +154,7 @@ int ptrace_setxregs(struct task_struct *child, void __user *uregs)
        coprocessor_flush_all(ti);
        coprocessor_release_all(ti);
 
-       ret |= __copy_from_user(&ti->xtregs_cp, &xtregs->cp0, 
+       ret |= __copy_from_user(&ti->xtregs_cp, &xtregs->cp0,
                                sizeof(xtregs_coprocessor_t));
 #endif
        ret |= __copy_from_user(&regs->xtregs_opt, &xtregs->opt,
@@ -343,4 +343,3 @@ void do_syscall_trace_leave(struct pt_regs *regs)
                        && (current->ptrace & PT_PTRACED))
                do_syscall_trace();
 }
-
index b237988ba6d77b789ca2766509e66fd50985c840..24c1a57abb40b6446951438614a29e805f93c1f4 100644 (file)
 #include <linux/bootmem.h>
 #include <linux/kernel.h>
 
+#ifdef CONFIG_OF
+#include <linux/of_fdt.h>
+#include <linux/of_platform.h>
+#endif
+
 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
 # include <linux/console.h>
 #endif
@@ -42,6 +47,7 @@
 #include <asm/page.h>
 #include <asm/setup.h>
 #include <asm/param.h>
+#include <asm/traps.h>
 
 #include <platform/hardware.h>
 
@@ -64,6 +70,11 @@ int initrd_is_mapped = 0;
 extern int initrd_below_start_ok;
 #endif
 
+#ifdef CONFIG_OF
+extern u32 __dtb_start[];
+void *dtb_start = __dtb_start;
+#endif
+
 unsigned char aux_device_present;
 extern unsigned long loops_per_jiffy;
 
@@ -83,6 +94,8 @@ extern void init_mmu(void);
 static inline void init_mmu(void) { }
 #endif
 
+extern int mem_reserve(unsigned long, unsigned long, int);
+extern void bootmem_init(void);
 extern void zones_init(void);
 
 /*
@@ -104,28 +117,33 @@ typedef struct tagtable {
 
 /* parse current tag */
 
-static int __init parse_tag_mem(const bp_tag_t *tag)
+static int __init add_sysmem_bank(unsigned long type, unsigned long start,
+               unsigned long end)
 {
-       meminfo_t *mi = (meminfo_t*)(tag->data);
-
-       if (mi->type != MEMORY_TYPE_CONVENTIONAL)
-               return -1;
-
        if (sysmem.nr_banks >= SYSMEM_BANKS_MAX) {
                printk(KERN_WARNING
-                      "Ignoring memory bank 0x%08lx size %ldKB\n",
-                      (unsigned long)mi->start,
-                      (unsigned long)mi->end - (unsigned long)mi->start);
+                               "Ignoring memory bank 0x%08lx size %ldKB\n",
+                               start, end - start);
                return -EINVAL;
        }
-       sysmem.bank[sysmem.nr_banks].type  = mi->type;
-       sysmem.bank[sysmem.nr_banks].start = PAGE_ALIGN(mi->start);
-       sysmem.bank[sysmem.nr_banks].end   = mi->end & PAGE_MASK;
+       sysmem.bank[sysmem.nr_banks].type  = type;
+       sysmem.bank[sysmem.nr_banks].start = PAGE_ALIGN(start);
+       sysmem.bank[sysmem.nr_banks].end   = end & PAGE_MASK;
        sysmem.nr_banks++;
 
        return 0;
 }
 
+static int __init parse_tag_mem(const bp_tag_t *tag)
+{
+       meminfo_t *mi = (meminfo_t *)(tag->data);
+
+       if (mi->type != MEMORY_TYPE_CONVENTIONAL)
+               return -1;
+
+       return add_sysmem_bank(mi->type, mi->start, mi->end);
+}
+
 __tagtable(BP_TAG_MEMORY, parse_tag_mem);
 
 #ifdef CONFIG_BLK_DEV_INITRD
@@ -142,12 +160,31 @@ static int __init parse_tag_initrd(const bp_tag_t* tag)
 
 __tagtable(BP_TAG_INITRD, parse_tag_initrd);
 
+#ifdef CONFIG_OF
+
+static int __init parse_tag_fdt(const bp_tag_t *tag)
+{
+       dtb_start = (void *)(tag->data[0]);
+       return 0;
+}
+
+__tagtable(BP_TAG_FDT, parse_tag_fdt);
+
+void __init early_init_dt_setup_initrd_arch(unsigned long start,
+               unsigned long end)
+{
+       initrd_start = (void *)__va(start);
+       initrd_end = (void *)__va(end);
+       initrd_below_start_ok = 1;
+}
+
+#endif /* CONFIG_OF */
+
 #endif /* CONFIG_BLK_DEV_INITRD */
 
 static int __init parse_tag_cmdline(const bp_tag_t* tag)
 {
-       strncpy(command_line, (char*)(tag->data), COMMAND_LINE_SIZE);
-       command_line[COMMAND_LINE_SIZE - 1] = '\0';
+       strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
        return 0;
 }
 
@@ -185,6 +222,58 @@ static int __init parse_bootparam(const bp_tag_t* tag)
        return 0;
 }
 
+#ifdef CONFIG_OF
+
+void __init early_init_dt_add_memory_arch(u64 base, u64 size)
+{
+       size &= PAGE_MASK;
+       add_sysmem_bank(MEMORY_TYPE_CONVENTIONAL, base, base + size);
+}
+
+void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
+{
+       return __alloc_bootmem(size, align, 0);
+}
+
+void __init early_init_devtree(void *params)
+{
+       /* Setup flat device-tree pointer */
+       initial_boot_params = params;
+
+       /* Retrieve various informations from the /chosen node of the
+        * device-tree, including the platform type, initrd location and
+        * size, TCE reserve, and more ...
+        */
+       if (!command_line[0])
+               of_scan_flat_dt(early_init_dt_scan_chosen, command_line);
+
+       /* Scan memory nodes and rebuild MEMBLOCKs */
+       of_scan_flat_dt(early_init_dt_scan_root, NULL);
+       if (sysmem.nr_banks == 0)
+               of_scan_flat_dt(early_init_dt_scan_memory, NULL);
+}
+
+static void __init copy_devtree(void)
+{
+       void *alloc = early_init_dt_alloc_memory_arch(
+                       be32_to_cpu(initial_boot_params->totalsize), 0);
+       if (alloc) {
+               memcpy(alloc, initial_boot_params,
+                               be32_to_cpu(initial_boot_params->totalsize));
+               initial_boot_params = alloc;
+       }
+}
+
+static int __init xtensa_device_probe(void)
+{
+       of_platform_populate(NULL, NULL, NULL, NULL);
+       return 0;
+}
+
+device_initcall(xtensa_device_probe);
+
+#endif /* CONFIG_OF */
+
 /*
  * Initialize architecture. (Early stage)
  */
@@ -193,14 +282,14 @@ void __init init_arch(bp_tag_t *bp_start)
 {
        sysmem.nr_banks = 0;
 
-#ifdef CONFIG_CMDLINE_BOOL
-       strcpy(command_line, default_command_line);
-#endif
-
        /* Parse boot parameters */
 
-        if (bp_start)
-         parse_bootparam(bp_start);
+       if (bp_start)
+               parse_bootparam(bp_start);
+
+#ifdef CONFIG_OF
+       early_init_devtree(dtb_start);
+#endif
 
        if (sysmem.nr_banks == 0) {
                sysmem.nr_banks = 1;
@@ -209,6 +298,11 @@ void __init init_arch(bp_tag_t *bp_start)
                                     + PLATFORM_DEFAULT_MEM_SIZE;
        }
 
+#ifdef CONFIG_CMDLINE_BOOL
+       if (!command_line[0])
+               strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
+#endif
+
        /* Early hook for platforms */
 
        platform_init(bp_start);
@@ -235,15 +329,130 @@ extern char _UserExceptionVector_text_end;
 extern char _DoubleExceptionVector_literal_start;
 extern char _DoubleExceptionVector_text_end;
 
-void __init setup_arch(char **cmdline_p)
+
+#ifdef CONFIG_S32C1I_SELFTEST
+#if XCHAL_HAVE_S32C1I
+
+static int __initdata rcw_word, rcw_probe_pc, rcw_exc;
+
+/*
+ * Basic atomic compare-and-swap, that records PC of S32C1I for probing.
+ *
+ * If *v == cmp, set *v = set.  Return previous *v.
+ */
+static inline int probed_compare_swap(int *v, int cmp, int set)
+{
+       int tmp;
+
+       __asm__ __volatile__(
+                       "       movi    %1, 1f\n"
+                       "       s32i    %1, %4, 0\n"
+                       "       wsr     %2, scompare1\n"
+                       "1:     s32c1i  %0, %3, 0\n"
+                       : "=a" (set), "=&a" (tmp)
+                       : "a" (cmp), "a" (v), "a" (&rcw_probe_pc), "0" (set)
+                       : "memory"
+                       );
+       return set;
+}
+
+/* Handle probed exception */
+
+void __init do_probed_exception(struct pt_regs *regs, unsigned long exccause)
+{
+       if (regs->pc == rcw_probe_pc) { /* exception on s32c1i ? */
+               regs->pc += 3;          /* skip the s32c1i instruction */
+               rcw_exc = exccause;
+       } else {
+               do_unhandled(regs, exccause);
+       }
+}
+
+/* Simple test of S32C1I (soc bringup assist) */
+
+void __init check_s32c1i(void)
+{
+       int n, cause1, cause2;
+       void *handbus, *handdata, *handaddr; /* temporarily saved handlers */
+
+       rcw_probe_pc = 0;
+       handbus  = trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR,
+                       do_probed_exception);
+       handdata = trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR,
+                       do_probed_exception);
+       handaddr = trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR,
+                       do_probed_exception);
+
+       /* First try an S32C1I that does not store: */
+       rcw_exc = 0;
+       rcw_word = 1;
+       n = probed_compare_swap(&rcw_word, 0, 2);
+       cause1 = rcw_exc;
+
+       /* took exception? */
+       if (cause1 != 0) {
+               /* unclean exception? */
+               if (n != 2 || rcw_word != 1)
+                       panic("S32C1I exception error");
+       } else if (rcw_word != 1 || n != 1) {
+               panic("S32C1I compare error");
+       }
+
+       /* Then an S32C1I that stores: */
+       rcw_exc = 0;
+       rcw_word = 0x1234567;
+       n = probed_compare_swap(&rcw_word, 0x1234567, 0xabcde);
+       cause2 = rcw_exc;
+
+       if (cause2 != 0) {
+               /* unclean exception? */
+               if (n != 0xabcde || rcw_word != 0x1234567)
+                       panic("S32C1I exception error (b)");
+       } else if (rcw_word != 0xabcde || n != 0x1234567) {
+               panic("S32C1I store error");
+       }
+
+       /* Verify consistency of exceptions: */
+       if (cause1 || cause2) {
+               pr_warn("S32C1I took exception %d, %d\n", cause1, cause2);
+               /* If emulation of S32C1I upon bus error gets implemented,
+                  we can get rid of this panic for single core (not SMP) */
+               panic("S32C1I exceptions not currently supported");
+       }
+       if (cause1 != cause2)
+               panic("inconsistent S32C1I exceptions");
+
+       trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR, handbus);
+       trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR, handdata);
+       trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR, handaddr);
+}
+
+#else /* XCHAL_HAVE_S32C1I */
+
+/* This condition should not occur with a commercially deployed processor.
+   Display reminder for early engr test or demo chips / FPGA bitstreams */
+void __init check_s32c1i(void)
+{
+       pr_warn("Processor configuration lacks atomic compare-and-swap support!\n");
+}
+
+#endif /* XCHAL_HAVE_S32C1I */
+#else /* CONFIG_S32C1I_SELFTEST */
+
+void __init check_s32c1i(void)
 {
-       extern int mem_reserve(unsigned long, unsigned long, int);
-       extern void bootmem_init(void);
+}
+
+#endif /* CONFIG_S32C1I_SELFTEST */
 
-       memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
-       boot_command_line[COMMAND_LINE_SIZE-1] = '\0';
+
+void __init setup_arch(char **cmdline_p)
+{
+       strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
        *cmdline_p = command_line;
 
+       check_s32c1i();
+
        /* Reserve some memory regions */
 
 #ifdef CONFIG_BLK_DEV_INITRD
@@ -251,7 +460,7 @@ void __init setup_arch(char **cmdline_p)
                initrd_is_mapped = mem_reserve(__pa(initrd_start),
                                               __pa(initrd_end), 0);
                initrd_below_start_ok = 1;
-       } else {
+       } else {
                initrd_start = 0;
        }
 #endif
@@ -275,8 +484,12 @@ void __init setup_arch(char **cmdline_p)
 
        bootmem_init();
 
-       platform_setup(cmdline_p);
+#ifdef CONFIG_OF
+       copy_devtree();
+       unflatten_device_tree();
+#endif
 
+       platform_setup(cmdline_p);
 
        paging_init();
        zones_init();
@@ -326,7 +539,7 @@ c_show(struct seq_file *f, void *slot)
                     "core ID\t\t: " XCHAL_CORE_ID "\n"
                     "build ID\t: 0x%x\n"
                     "byte order\t: %s\n"
-                    "cpu MHz\t\t: %lu.%02lu\n"
+                    "cpu MHz\t\t: %lu.%02lu\n"
                     "bogomips\t: %lu.%02lu\n",
                     XCHAL_BUILD_UNIQUE_ID,
                     XCHAL_HAVE_BE ?  "big" : "little",
@@ -380,6 +593,9 @@ c_show(struct seq_file *f, void *slot)
 #endif
 #if XCHAL_HAVE_FP
                     "fpu "
+#endif
+#if XCHAL_HAVE_S32C1I
+                    "s32c1i "
 #endif
                     "\n");
 
@@ -412,7 +628,7 @@ c_show(struct seq_file *f, void *slot)
                     "icache size\t: %d\n"
                     "icache flags\t: "
 #if XCHAL_ICACHE_LINE_LOCKABLE
-                    "lock"
+                    "lock "
 #endif
                     "\n"
                     "dcache line size: %d\n"
@@ -420,10 +636,10 @@ c_show(struct seq_file *f, void *slot)
                     "dcache size\t: %d\n"
                     "dcache flags\t: "
 #if XCHAL_DCACHE_IS_WRITEBACK
-                    "writeback"
+                    "writeback "
 #endif
 #if XCHAL_DCACHE_LINE_LOCKABLE
-                    "lock"
+                    "lock "
 #endif
                     "\n",
                     XCHAL_ICACHE_LINESIZE,
@@ -465,4 +681,3 @@ const struct seq_operations cpuinfo_op =
 };
 
 #endif /* CONFIG_PROC_FS */
-
index 63c566f627bc9ca13ac0df36a9752698ca9a62c0..de34d6be91cd4b53dc5f232901e10bef53f15bdd 100644 (file)
@@ -212,7 +212,7 @@ restore_sigcontext(struct pt_regs *regs, struct rt_sigframe __user *frame)
        if (err)
                return err;
 
-       /* The signal handler may have used coprocessors in which
+       /* The signal handler may have used coprocessors in which
         * case they are still enabled.  We disable them to force a
         * reloading of the original task's CP state by the lazy
         * context-switching mechanisms of CP exception handling.
@@ -396,7 +396,7 @@ static int setup_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
         */
 
        /* Set up registers for signal handler */
-       start_thread(regs, (unsigned long) ka->sa.sa_handler, 
+       start_thread(regs, (unsigned long) ka->sa.sa_handler,
                     (unsigned long) frame);
 
        /* Set up a stack frame for a call4
@@ -424,9 +424,9 @@ give_sigsegv:
        return -EFAULT;
 }
 
-asmlinkage long xtensa_sigaltstack(const stack_t __user *uss, 
+asmlinkage long xtensa_sigaltstack(const stack_t __user *uss,
                                   stack_t __user *uoss,
-                                  long a2, long a3, long a4, long a5,
+                                  long a2, long a3, long a4, long a5,
                                   struct pt_regs *regs)
 {
        return do_sigaltstack(uss, uoss, regs->areg[1]);
index 5702065f472a88bebc4df721dec0629208957395..54fa8425cee23593b5aded18162a8040d7644185 100644 (file)
@@ -52,4 +52,3 @@ asmlinkage long xtensa_fadvise64_64(int fd, int advice,
 {
        return sys_fadvise64_64(fd, offset, len, advice);
 }
-
index ac62f9cf1e100518ce719d10beb7110385b149ba..ffb4741043116dc0bb76a5ccdb11f161257ac9cd 100644 (file)
@@ -22,6 +22,7 @@
 #include <linux/irq.h>
 #include <linux/profile.h>
 #include <linux/delay.h>
+#include <linux/irqdomain.h>
 
 #include <asm/timex.h>
 #include <asm/platform.h>
@@ -31,7 +32,7 @@ unsigned long ccount_per_jiffy;               /* per 1/HZ */
 unsigned long nsec_per_ccount;         /* nsec per ccount increment */
 #endif
 
-static cycle_t ccount_read(void)
+static cycle_t ccount_read(struct clocksource *cs)
 {
        return (cycle_t)get_ccount();
 }
@@ -52,6 +53,7 @@ static struct irqaction timer_irqaction = {
 
 void __init time_init(void)
 {
+       unsigned int irq;
 #ifdef CONFIG_XTENSA_CALIBRATE_CCOUNT
        printk("Calibrating CPU frequency ");
        platform_calibrate_ccount();
@@ -62,7 +64,8 @@ void __init time_init(void)
 
        /* Initialize the linux timer interrupt. */
 
-       setup_irq(LINUX_TIMER_INT, &timer_irqaction);
+       irq = irq_create_mapping(NULL, LINUX_TIMER_INT);
+       setup_irq(irq, &timer_irqaction);
        set_linux_timer(get_ccount() + CCOUNT_PER_JIFFY);
 }
 
index 5caf2b64d43ac846c7a0c148166c54877dec8178..01e0111bf787f610ac004c976aaf585a3928e5d6 100644 (file)
@@ -293,6 +293,17 @@ do_debug(struct pt_regs *regs)
 }
 
 
+/* Set exception C handler - for temporary use when probing exceptions */
+
+void * __init trap_set_handler(int cause, void *handler)
+{
+       unsigned long *entry = &exc_table[EXC_TABLE_DEFAULT / 4 + cause];
+       void *previous = (void *)*entry;
+       *entry = (unsigned long)handler;
+       return previous;
+}
+
+
 /*
  * Initialize dispatch tables.
  *
@@ -397,7 +408,8 @@ static inline void spill_registers(void)
                "wsr    a13, sar\n\t"
                "wsr    a14, ps\n\t"
                :: "a" (&a0), "a" (&ps)
-               : "a2", "a3", "a4", "a7", "a11", "a12", "a13", "a14", "a15", "memory");
+               : "a2", "a3", "a4", "a7", "a11", "a12", "a13", "a14", "a15",
+                 "memory");
 }
 
 void show_trace(struct task_struct *task, unsigned long *sp)
@@ -452,7 +464,7 @@ void show_stack(struct task_struct *task, unsigned long *sp)
 
        if (!sp)
                sp = stack_pointer(task);
-       stack = sp;
+       stack = sp;
 
        printk("\nStack: ");
 
@@ -523,5 +535,3 @@ void die(const char * str, struct pt_regs * regs, long err)
 
        do_exit(err);
 }
-
-
index 4462c1e595c2b1ed87f772e11335561ed1885d6d..68df35f66ce395ee75353d6c6a5cef71ebd11edc 100644 (file)
@@ -79,6 +79,8 @@ ENTRY(_UserExceptionVector)
        l32i    a0, a0, EXC_TABLE_FAST_USER     # load handler
        jx      a0
 
+ENDPROC(_UserExceptionVector)
+
 /*
  * Kernel exception vector. (Exceptions with PS.UM == 0, PS.EXCM == 0)
  *
@@ -103,6 +105,7 @@ ENTRY(_KernelExceptionVector)
        l32i    a0, a0, EXC_TABLE_FAST_KERNEL   # load handler address
        jx      a0
 
+ENDPROC(_KernelExceptionVector)
 
 /*
  * Double exception vector (Exceptions with PS.EXCM == 1)
@@ -225,7 +228,13 @@ ENTRY(_DoubleExceptionVector)
        /* Window overflow/underflow exception. Get stack pointer. */
 
        mov     a3, a2
-       movi    a2, exc_table
+       /* This explicit literal and the following references to it are made
+        * in order to fit DoubleExceptionVector.literals into the available
+        * 16-byte gap before DoubleExceptionVector.text in the absence of
+        * link time relaxation. See kernel/vmlinux.lds.S
+        */
+       .literal .Lexc_table, exc_table
+       l32r    a2, .Lexc_table
        l32i    a2, a2, EXC_TABLE_KSTK
 
        /* Check for overflow/underflow exception, jump if overflow. */
@@ -255,7 +264,7 @@ ENTRY(_DoubleExceptionVector)
        s32i    a0, a2, PT_AREG0
 
        wsr     a3, excsave1            # save a3
-       movi    a3, exc_table
+       l32r    a3, .Lexc_table
 
        rsr     a0, exccause
        s32i    a0, a2, PT_DEPC         # mark it as a regular exception
@@ -267,7 +276,7 @@ ENTRY(_DoubleExceptionVector)
 
        /* a0: depc, a1: a1, a2: a2, a3: trashed, depc: a0, excsave1: a3 */
 
-       movi    a3, exc_table
+       l32r    a3, .Lexc_table
        s32i    a2, a3, EXC_TABLE_DOUBLE_SAVE   # temporary variable
 
        /* Enter critical section. */
@@ -296,7 +305,7 @@ ENTRY(_DoubleExceptionVector)
 
        /* a0: avail, a1: a1, a2: kstk, a3: avail, depc: a2, excsave: a3 */
 
-       movi    a3, exc_table
+       l32r    a3, .Lexc_table
        rsr     a0, exccause
        addx4   a0, a0, a3
        l32i    a0, a0, EXC_TABLE_FAST_USER
@@ -338,6 +347,7 @@ ENTRY(_DoubleExceptionVector)
 
        .end literal_prefix
 
+ENDPROC(_DoubleExceptionVector)
 
 /*
  * Debug interrupt vector
@@ -349,9 +359,11 @@ ENTRY(_DoubleExceptionVector)
        .section .DebugInterruptVector.text, "ax"
 
 ENTRY(_DebugInterruptVector)
+
        xsr     a0, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
        jx      a0
 
+ENDPROC(_DebugInterruptVector)
 
 
 /* Window overflow and underflow handlers.
@@ -363,38 +375,43 @@ ENTRY(_DebugInterruptVector)
  *      we try to access any page that would cause a page fault early.
  */
 
+#define ENTRY_ALIGN64(name)    \
+       .globl name;            \
+       .align 64;              \
+       name:
+
        .section                .WindowVectors.text, "ax"
 
 
 /* 4-Register Window Overflow Vector (Handler) */
 
-       .align 64
-.global _WindowOverflow4
-_WindowOverflow4:
+ENTRY_ALIGN64(_WindowOverflow4)
+
        s32e    a0, a5, -16
        s32e    a1, a5, -12
        s32e    a2, a5,  -8
        s32e    a3, a5,  -4
        rfwo
 
+ENDPROC(_WindowOverflow4)
+
 
 /* 4-Register Window Underflow Vector (Handler) */
 
-       .align 64
-.global _WindowUnderflow4
-_WindowUnderflow4:
+ENTRY_ALIGN64(_WindowUnderflow4)
+
        l32e    a0, a5, -16
        l32e    a1, a5, -12
        l32e    a2, a5,  -8
        l32e    a3, a5,  -4
        rfwu
 
+ENDPROC(_WindowUnderflow4)
 
 /* 8-Register Window Overflow Vector (Handler) */
 
-       .align 64
-.global _WindowOverflow8
-_WindowOverflow8:
+ENTRY_ALIGN64(_WindowOverflow8)
+
        s32e    a0, a9, -16
        l32e    a0, a1, -12
        s32e    a2, a9,  -8
@@ -406,11 +423,12 @@ _WindowOverflow8:
        s32e    a7, a0, -20
        rfwo
 
+ENDPROC(_WindowOverflow8)
+
 /* 8-Register Window Underflow Vector (Handler) */
 
-       .align 64
-.global _WindowUnderflow8
-_WindowUnderflow8:
+ENTRY_ALIGN64(_WindowUnderflow8)
+
        l32e    a1, a9, -12
        l32e    a0, a9, -16
        l32e    a7, a1, -12
@@ -422,12 +440,12 @@ _WindowUnderflow8:
        l32e    a7, a7, -20
        rfwu
 
+ENDPROC(_WindowUnderflow8)
 
 /* 12-Register Window Overflow Vector (Handler) */
 
-       .align 64
-.global _WindowOverflow12
-_WindowOverflow12:
+ENTRY_ALIGN64(_WindowOverflow12)
+
        s32e    a0,  a13, -16
        l32e    a0,  a1,  -12
        s32e    a1,  a13, -12
@@ -443,11 +461,12 @@ _WindowOverflow12:
        s32e    a11, a0,  -20
        rfwo
 
+ENDPROC(_WindowOverflow12)
+
 /* 12-Register Window Underflow Vector (Handler) */
 
-       .align 64
-.global _WindowUnderflow12
-_WindowUnderflow12:
+ENTRY_ALIGN64(_WindowUnderflow12)
+
        l32e    a1,  a13, -12
        l32e    a0,  a13, -16
        l32e    a11, a1,  -12
@@ -463,6 +482,6 @@ _WindowUnderflow12:
        l32e    a11, a11, -20
        rfwu
 
-       .text
-
+ENDPROC(_WindowUnderflow12)
 
+       .text
index df397f932d0e0ea28ee84b11a5b0a89c675ff885..4eb573d2720e7ccd7577f11b27ad79347c2f472a 100644 (file)
 
 .text
 ENTRY(csum_partial)
-         /*
-          * Experiments with Ethernet and SLIP connections show that buf
-          * is aligned on either a 2-byte or 4-byte boundary.
-          */
+
+       /*
+        * Experiments with Ethernet and SLIP connections show that buf
+        * is aligned on either a 2-byte or 4-byte boundary.
+        */
        entry   sp, 32
        extui   a5, a2, 0, 2
        bnez    a5, 8f          /* branch if 2-byte aligned */
@@ -170,7 +171,7 @@ ENTRY(csum_partial)
 3:
        j       5b              /* branch to handle the remaining byte */
 
-
+ENDPROC(csum_partial)
 
 /*
  * Copy from ds while checksumming, otherwise like csum_partial
@@ -211,6 +212,7 @@ unsigned int csum_partial_copy_generic (const char *src, char *dst, int len,
  */
 
 ENTRY(csum_partial_copy_generic)
+
        entry   sp, 32
        mov     a12, a3
        mov     a11, a4
@@ -367,6 +369,8 @@ DST(        s8i     a8, a3, 1       )
 6:
        j       4b              /* process the possible trailing odd byte */
 
+ENDPROC(csum_partial_copy_generic)
+
 
 # Exception handler:
 .section .fixup, "ax"
@@ -406,4 +410,3 @@ DST(        s8i     a8, a3, 1       )
        retw
 
 .previous
-
index c48b80acb5f014813c9d509f425e95e4f3b872e0..b1c219acabe7a56b2bd06b5ff3f42e63505e9031 100644 (file)
@@ -210,8 +210,10 @@ memcpy:
        _beqz   a4, .Ldone      # avoid loading anything for zero-length copies
        # copy 16 bytes per iteration for word-aligned dst and unaligned src
        ssa8    a3              # set shift amount from byte offset
-#define SIM_CHECKS_ALIGNMENT   1       /* set to 1 when running on ISS (simulator) with the
-                                          lint or ferret client, or 0 to save a few cycles */
+
+/* set to 1 when running on ISS (simulator) with the
+   lint or ferret client, or 0 to save a few cycles */
+#define SIM_CHECKS_ALIGNMENT   1
 #if XCHAL_UNALIGNED_LOAD_EXCEPTION || SIM_CHECKS_ALIGNMENT
        and     a11, a3, a8     # save unalignment offset for below
        sub     a3, a3, a11     # align a3
index a71733ae119326fb7a99c211da375b023828b99a..34d05abbd921a397d2335f6618f5da36d9807147 100644 (file)
@@ -241,8 +241,8 @@ int __init pciauto_bus_scan(struct pci_controller *pci_ctrl, int current_bus)
        unsigned char header_type;
        struct pci_dev *dev = &pciauto_dev;
 
-        pciauto_dev.bus = &pciauto_bus;
-        pciauto_dev.sysdata = pci_ctrl;
+       pciauto_dev.bus = &pciauto_bus;
+       pciauto_dev.sysdata = pci_ctrl;
        pciauto_bus.ops = pci_ctrl->ops;
 
        /*
@@ -345,8 +345,3 @@ int __init pciauto_bus_scan(struct pci_controller *pci_ctrl, int current_bus)
        }
        return sub_bus;
 }
-
-
-
-
-
index 9f603cdaaa6839a6820860656fb1f46dab255918..1ad0ecf45368ea554565dfa1ae8737295f5710d4 100644 (file)
@@ -166,7 +166,7 @@ __strncpy_user:
        retw
 .Lz1:  # byte 1 is zero
 #ifdef __XTENSA_EB__
-        extui   a9, a9, 16, 16
+       extui   a9, a9, 16, 16
 #endif /* __XTENSA_EB__ */
        EX(s16i, a9, a11, 0, fixup_s)
        addi    a11, a11, 1             # advance dst pointer
@@ -174,7 +174,7 @@ __strncpy_user:
        retw
 .Lz2:  # byte 2 is zero
 #ifdef __XTENSA_EB__
-        extui   a9, a9, 16, 16
+       extui   a9, a9, 16, 16
 #endif /* __XTENSA_EB__ */
        EX(s16i, a9, a11, 0, fixup_s)
        movi    a9, 0
index 23f2a89816a14bd7a5983a7c2da2aa8d45bc6901..4c03b1e581e973f996798cb2ea81bc4d4f6a9450 100644 (file)
@@ -145,4 +145,3 @@ __strnlen_user:
 lenfixup:
        movi    a2, 0
        retw
-
index 46d60314bb160983a0696bcaf849bb01dda0ff5e..ace1892a875ea6505c12924474536586e894ef49 100644 (file)
@@ -318,4 +318,3 @@ l_fixup:
        /* Ignore memset return value in a6. */
        /* a2 still contains bytes not copied. */
        retw
-
index 85df4655d3264d8afda978c5ed0a229567b43989..81edeab82d174eb478ad303001da881d6758f2bb 100644 (file)
@@ -118,7 +118,7 @@ void flush_dcache_page(struct page *page)
  * For now, flush the whole cache. FIXME??
  */
 
-void flush_cache_range(struct vm_area_struct* vma, 
+void flush_cache_range(struct vm_area_struct* vma,
                       unsigned long start, unsigned long end)
 {
        __flush_invalidate_dcache_all();
@@ -133,7 +133,7 @@ void flush_cache_range(struct vm_area_struct* vma,
  */
 
 void flush_cache_page(struct vm_area_struct* vma, unsigned long address,
-                     unsigned long pfn)
+                     unsigned long pfn)
 {
        /* Note that we have to use the 'alias' address to avoid multi-hit */
 
@@ -166,14 +166,14 @@ update_mmu_cache(struct vm_area_struct * vma, unsigned long addr, pte_t *ptep)
 
        if (!PageReserved(page) && test_bit(PG_arch_1, &page->flags)) {
 
-               unsigned long vaddr = TLBTEMP_BASE_1 + (addr & DCACHE_ALIAS_MASK);
                unsigned long paddr = (unsigned long) page_address(page);
                unsigned long phys = page_to_phys(page);
+               unsigned long tmp = TLBTEMP_BASE_1 + (addr & DCACHE_ALIAS_MASK);
 
                __flush_invalidate_dcache_page(paddr);
 
-               __flush_invalidate_dcache_page_alias(vaddr, phys);
-               __invalidate_icache_page_alias(vaddr, ph