Merge branch 'tegra/cleanups' into next/cleanup2
authorArnd Bergmann <arnd@arndb.de>
Mon, 19 Mar 2012 21:02:20 +0000 (21:02 +0000)
committerArnd Bergmann <arnd@arndb.de>
Mon, 19 Mar 2012 21:02:20 +0000 (21:02 +0000)
318 files changed:
Documentation/feature-removal-schedule.txt
arch/arm/Kconfig
arch/arm/Kconfig.debug
arch/arm/boot/dts/at91sam9g25ek.dts [new file with mode: 0644]
arch/arm/boot/dts/at91sam9x5.dtsi [new file with mode: 0644]
arch/arm/boot/dts/at91sam9x5cm.dtsi [new file with mode: 0644]
arch/arm/configs/at91cap9_defconfig [deleted file]
arch/arm/include/asm/assembler.h
arch/arm/include/asm/io.h
arch/arm/kernel/debug.S
arch/arm/kernel/entry-armv.S
arch/arm/mach-at91/Kconfig
arch/arm/mach-at91/Makefile
arch/arm/mach-at91/Makefile.boot
arch/arm/mach-at91/at91cap9.c [deleted file]
arch/arm/mach-at91/at91cap9_devices.c [deleted file]
arch/arm/mach-at91/at91rm9200.c
arch/arm/mach-at91/at91rm9200_devices.c
arch/arm/mach-at91/at91rm9200_time.c
arch/arm/mach-at91/at91sam9260.c
arch/arm/mach-at91/at91sam9260_devices.c
arch/arm/mach-at91/at91sam9261.c
arch/arm/mach-at91/at91sam9261_devices.c
arch/arm/mach-at91/at91sam9263.c
arch/arm/mach-at91/at91sam9263_devices.c
arch/arm/mach-at91/at91sam9_alt_reset.S
arch/arm/mach-at91/at91sam9g45.c
arch/arm/mach-at91/at91sam9g45_devices.c
arch/arm/mach-at91/at91sam9g45_reset.S
arch/arm/mach-at91/at91sam9rl.c
arch/arm/mach-at91/at91sam9rl_devices.c
arch/arm/mach-at91/at91sam9x5.c [new file with mode: 0644]
arch/arm/mach-at91/at91x40.c
arch/arm/mach-at91/at91x40_time.c
arch/arm/mach-at91/board-cap9adk.c [deleted file]
arch/arm/mach-at91/board-cpu9krea.c
arch/arm/mach-at91/board-cpuat91.c
arch/arm/mach-at91/board-dt.c
arch/arm/mach-at91/board-eco920.c
arch/arm/mach-at91/board-flexibity.c
arch/arm/mach-at91/board-kb9202.c
arch/arm/mach-at91/board-picotux200.c
arch/arm/mach-at91/board-rm9200dk.c
arch/arm/mach-at91/board-rm9200ek.c
arch/arm/mach-at91/board-sam9m10g45ek.c
arch/arm/mach-at91/board-yl-9200.c
arch/arm/mach-at91/clock.c
arch/arm/mach-at91/cpuidle.c
arch/arm/mach-at91/generic.h
arch/arm/mach-at91/include/mach/at91_matrix.h [new file with mode: 0644]
arch/arm/mach-at91/include/mach/at91_pmc.h
arch/arm/mach-at91/include/mach/at91_ramc.h [new file with mode: 0644]
arch/arm/mach-at91/include/mach/at91_st.h
arch/arm/mach-at91/include/mach/at91cap9.h [deleted file]
arch/arm/mach-at91/include/mach/at91cap9_matrix.h [deleted file]
arch/arm/mach-at91/include/mach/at91rm9200.h
arch/arm/mach-at91/include/mach/at91rm9200_mc.h
arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h [new file with mode: 0644]
arch/arm/mach-at91/include/mach/at91sam9260.h
arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
arch/arm/mach-at91/include/mach/at91sam9261.h
arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
arch/arm/mach-at91/include/mach/at91sam9263.h
arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
arch/arm/mach-at91/include/mach/at91sam9g45.h
arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
arch/arm/mach-at91/include/mach/at91sam9rl.h
arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
arch/arm/mach-at91/include/mach/at91sam9x5.h [new file with mode: 0644]
arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h [new file with mode: 0644]
arch/arm/mach-at91/include/mach/at91x40.h
arch/arm/mach-at91/include/mach/board.h
arch/arm/mach-at91/include/mach/cpu.h
arch/arm/mach-at91/include/mach/hardware.h
arch/arm/mach-at91/include/mach/io.h [deleted file]
arch/arm/mach-at91/include/mach/uncompress.h
arch/arm/mach-at91/pm.c
arch/arm/mach-at91/pm.h
arch/arm/mach-at91/pm_slowclock.S
arch/arm/mach-at91/setup.c
arch/arm/mach-at91/soc.h
arch/arm/mach-bcmring/include/mach/io.h [deleted file]
arch/arm/mach-clps711x/include/mach/io.h [deleted file]
arch/arm/mach-clps711x/include/mach/uncompress.h
arch/arm/mach-cns3xxx/core.c
arch/arm/mach-cns3xxx/devices.c
arch/arm/mach-cns3xxx/include/mach/io.h [deleted file]
arch/arm/mach-davinci/include/mach/entry-macro.S
arch/arm/mach-davinci/include/mach/hardware.h
arch/arm/mach-davinci/include/mach/io.h [deleted file]
arch/arm/mach-davinci/include/mach/uncompress.h
arch/arm/mach-dove/addr-map.c
arch/arm/mach-dove/include/mach/io.h
arch/arm/mach-ebsa110/core.c
arch/arm/mach-ebsa110/include/mach/io.h
arch/arm/mach-ep93xx/include/mach/io.h [deleted file]
arch/arm/mach-exynos/include/mach/io.h [deleted file]
arch/arm/mach-footbridge/include/mach/io.h
arch/arm/mach-gemini/include/mach/io.h [deleted file]
arch/arm/mach-h720x/include/mach/io.h [deleted file]
arch/arm/mach-highbank/include/mach/io.h [deleted file]
arch/arm/mach-imx/mm-imx3.c
arch/arm/mach-integrator/include/mach/io.h
arch/arm/mach-iop13xx/include/mach/io.h
arch/arm/mach-iop13xx/include/mach/iop13xx.h
arch/arm/mach-iop13xx/io.c
arch/arm/mach-iop13xx/iq81340mc.c
arch/arm/mach-iop13xx/iq81340sc.c
arch/arm/mach-iop13xx/pci.h [new file with mode: 0644]
arch/arm/mach-iop32x/include/mach/io.h
arch/arm/mach-iop33x/include/mach/io.h
arch/arm/mach-ixp2000/include/mach/io.h
arch/arm/mach-ixp23xx/include/mach/io.h
arch/arm/mach-ixp4xx/avila-setup.c
arch/arm/mach-ixp4xx/common.c
arch/arm/mach-ixp4xx/coyote-setup.c
arch/arm/mach-ixp4xx/dsmg600-setup.c
arch/arm/mach-ixp4xx/fsg-setup.c
arch/arm/mach-ixp4xx/gateway7001-setup.c
arch/arm/mach-ixp4xx/goramo_mlr.c
arch/arm/mach-ixp4xx/gtwx5715-setup.c
arch/arm/mach-ixp4xx/include/mach/io.h
arch/arm/mach-ixp4xx/include/mach/platform.h
arch/arm/mach-ixp4xx/ixdp425-setup.c
arch/arm/mach-ixp4xx/nas100d-setup.c
arch/arm/mach-ixp4xx/nslu2-setup.c
arch/arm/mach-ixp4xx/omixp-setup.c
arch/arm/mach-ixp4xx/vulcan-setup.c
arch/arm/mach-ixp4xx/wg302v2-setup.c
arch/arm/mach-kirkwood/include/mach/io.h
arch/arm/mach-ks8695/include/mach/io.h [deleted file]
arch/arm/mach-lpc32xx/include/mach/io.h [deleted file]
arch/arm/mach-mmp/include/mach/addr-map.h
arch/arm/mach-mmp/include/mach/io.h [deleted file]
arch/arm/mach-msm/board-halibut.c
arch/arm/mach-msm/board-trout.c
arch/arm/mach-msm/include/mach/io.h [deleted file]
arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
arch/arm/mach-msm/include/mach/msm_iomap-8960.h
arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
arch/arm/mach-msm/include/mach/msm_iomap.h
arch/arm/mach-msm/io.c
arch/arm/mach-mv78xx0/include/mach/io.h
arch/arm/mach-mxs/include/mach/hardware.h
arch/arm/mach-mxs/include/mach/io.h [deleted file]
arch/arm/mach-netx/generic.c
arch/arm/mach-netx/include/mach/hardware.h
arch/arm/mach-netx/include/mach/io.h [deleted file]
arch/arm/mach-netx/include/mach/netx-regs.h
arch/arm/mach-nomadik/include/mach/io.h [deleted file]
arch/arm/mach-omap1/ams-delta-fiq-handler.S
arch/arm/mach-omap1/ams-delta-fiq.c
arch/arm/mach-omap1/board-ams-delta.c
arch/arm/mach-omap1/board-fsample.c
arch/arm/mach-omap1/board-h2.c
arch/arm/mach-omap1/board-h3.c
arch/arm/mach-omap1/board-htcherald.c
arch/arm/mach-omap1/board-innovator.c
arch/arm/mach-omap1/board-nokia770.c
arch/arm/mach-omap1/board-osk.c
arch/arm/mach-omap1/board-palmte.c
arch/arm/mach-omap1/board-palmtt.c
arch/arm/mach-omap1/board-palmz71.c
arch/arm/mach-omap1/board-perseus2.c
arch/arm/mach-omap1/board-sx1.c
arch/arm/mach-omap1/board-voiceblue.c
arch/arm/mach-omap1/clock.c
arch/arm/mach-omap1/clock_data.c
arch/arm/mach-omap1/common.h
arch/arm/mach-omap1/devices.c
arch/arm/mach-omap1/dma.c
arch/arm/mach-omap1/flash.c
arch/arm/mach-omap1/fpga.c
arch/arm/mach-omap1/gpio16xx.c
arch/arm/mach-omap1/id.c
arch/arm/mach-omap1/include/mach/entry-macro.S
arch/arm/mach-omap1/include/mach/hardware.h
arch/arm/mach-omap1/include/mach/io.h [deleted file]
arch/arm/mach-omap1/include/mach/memory.h
arch/arm/mach-omap1/io.c
arch/arm/mach-omap1/iomap.h [new file with mode: 0644]
arch/arm/mach-omap1/irq.c
arch/arm/mach-omap1/lcd_dma.c
arch/arm/mach-omap1/mcbsp.c
arch/arm/mach-omap1/pm.c
arch/arm/mach-omap1/reset.c
arch/arm/mach-omap1/sleep.S
arch/arm/mach-omap1/sram.S
arch/arm/mach-omap1/time.c
arch/arm/mach-omap1/timer32k.c
arch/arm/mach-omap2/board-cm-t35.c
arch/arm/mach-omap2/board-n8x0.c
arch/arm/mach-omap2/board-rx51-peripherals.c
arch/arm/mach-omap2/board-zoom-display.c
arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
arch/arm/mach-omap2/clkt_dpll.c
arch/arm/mach-omap2/clock2420_data.c
arch/arm/mach-omap2/clock2430.c
arch/arm/mach-omap2/clock2430_data.c
arch/arm/mach-omap2/clock2xxx.c
arch/arm/mach-omap2/clock3xxx.c
arch/arm/mach-omap2/clock3xxx_data.c
arch/arm/mach-omap2/clock44xx_data.c
arch/arm/mach-omap2/cm2xxx_3xxx.c
arch/arm/mach-omap2/cm44xx.c
arch/arm/mach-omap2/cminst44xx.c
arch/arm/mach-omap2/common-board-devices.c
arch/arm/mach-omap2/common.c
arch/arm/mach-omap2/common.h
arch/arm/mach-omap2/control.c
arch/arm/mach-omap2/control.h
arch/arm/mach-omap2/devices.c
arch/arm/mach-omap2/display.c
arch/arm/mach-omap2/emu.c
arch/arm/mach-omap2/gpmc-nand.c
arch/arm/mach-omap2/gpmc-onenand.c
arch/arm/mach-omap2/include/mach/io.h [deleted file]
arch/arm/mach-omap2/io.c
arch/arm/mach-omap2/iomap.h [new file with mode: 0644]
arch/arm/mach-omap2/irq.c
arch/arm/mach-omap2/omap-smp.c
arch/arm/mach-omap2/opp2420_data.c
arch/arm/mach-omap2/opp2430_data.c
arch/arm/mach-omap2/pm24xx.c
arch/arm/mach-omap2/prcm_mpu44xx.c
arch/arm/mach-omap2/prm44xx.c
arch/arm/mach-omap2/prminst44xx.c
arch/arm/mach-omap2/sdram-nokia.c
arch/arm/mach-omap2/sdrc2xxx.c
arch/arm/mach-omap2/sleep24xx.S
arch/arm/mach-omap2/sleep34xx.S
arch/arm/mach-omap2/sram242x.S
arch/arm/mach-omap2/sram243x.S
arch/arm/mach-omap2/sram34xx.S
arch/arm/mach-orion5x/common.h
arch/arm/mach-orion5x/include/mach/io.h [deleted file]
arch/arm/mach-orion5x/pci.c
arch/arm/mach-orion5x/tsx09-common.c
arch/arm/mach-picoxcell/include/mach/io.h [deleted file]
arch/arm/mach-pnx4008/include/mach/io.h [deleted file]
arch/arm/mach-prima2/include/mach/io.h [deleted file]
arch/arm/mach-pxa/include/mach/io.h [deleted file]
arch/arm/mach-realview/include/mach/hardware.h
arch/arm/mach-realview/include/mach/io.h [deleted file]
arch/arm/mach-rpc/include/mach/hardware.h
arch/arm/mach-rpc/include/mach/io.h
arch/arm/mach-s3c2410/include/mach/io.h
arch/arm/mach-s3c64xx/include/mach/io.h [deleted file]
arch/arm/mach-s5p64x0/include/mach/io.h [deleted file]
arch/arm/mach-s5pc100/include/mach/io.h [deleted file]
arch/arm/mach-s5pv210/include/mach/io.h [deleted file]
arch/arm/mach-sa1100/include/mach/io.h [deleted file]
arch/arm/mach-shark/include/mach/io.h
arch/arm/mach-shmobile/board-ag5evm.c
arch/arm/mach-shmobile/board-bonito.c
arch/arm/mach-shmobile/board-kota2.c
arch/arm/mach-shmobile/include/mach/io.h [deleted file]
arch/arm/mach-shmobile/intc-r8a7779.c
arch/arm/mach-shmobile/intc-sh73a0.c
arch/arm/mach-shmobile/smp-r8a7779.c
arch/arm/mach-shmobile/smp-sh73a0.c
arch/arm/mach-spear3xx/clock.c
arch/arm/mach-spear3xx/include/mach/io.h [deleted file]
arch/arm/mach-spear6xx/clock.c
arch/arm/mach-spear6xx/include/mach/io.h [deleted file]
arch/arm/mach-tegra/include/mach/debug-macro.S
arch/arm/mach-tegra/include/mach/io.h
arch/arm/mach-tegra/include/mach/iomap.h
arch/arm/mach-tegra/io.c
arch/arm/mach-u300/include/mach/io.h [deleted file]
arch/arm/mach-u300/include/mach/u300-regs.h
arch/arm/mach-ux500/include/mach/hardware.h
arch/arm/mach-ux500/include/mach/io.h [deleted file]
arch/arm/mach-versatile/include/mach/io.h [deleted file]
arch/arm/mach-vexpress/include/mach/io.h [deleted file]
arch/arm/mach-vt8500/include/mach/io.h [deleted file]
arch/arm/mach-w90x900/include/mach/io.h [deleted file]
arch/arm/mach-zynq/include/mach/io.h [deleted file]
arch/arm/mm/ioremap.c
arch/arm/mm/nommu.c
arch/arm/plat-mxc/include/mach/hardware.h
arch/arm/plat-mxc/include/mach/io.h [deleted file]
arch/arm/plat-omap/counter_32k.c
arch/arm/plat-omap/dma.c
arch/arm/plat-omap/dmtimer.c
arch/arm/plat-omap/include/plat/io.h [deleted file]
arch/arm/plat-omap/include/plat/keypad.h
arch/arm/plat-omap/include/plat/mcspi.h
arch/arm/plat-omap/include/plat/sdrc.h
arch/arm/plat-omap/include/plat/tc.h
arch/arm/plat-omap/include/plat/usb.h
arch/arm/plat-omap/mux.c
arch/arm/plat-omap/sram.c
arch/arm/plat-omap/usb.c
arch/arm/plat-spear/include/plat/hardware.h
arch/arm/plat-spear/include/plat/io.h [deleted file]
arch/avr32/mach-at32ap/at32ap700x.c
arch/avr32/mach-at32ap/include/mach/cpu.h
drivers/char/hw_random/omap-rng.c
drivers/gpio/gpio-omap.c
drivers/media/video/davinci/vpbe_osd.c
drivers/media/video/davinci/vpbe_venc.c
drivers/mmc/host/at91_mci.c
drivers/pcmcia/at91_cf.c
drivers/rtc/rtc-at91sam9.c
drivers/tty/serial/atmel_serial.c
drivers/usb/gadget/Kconfig
drivers/usb/gadget/at91_udc.c
drivers/usb/gadget/atmel_usba_udc.c
drivers/usb/host/ohci-pxa27x.c
drivers/video/omap2/dss/dispc.c
drivers/video/omap2/dss/dss.c
drivers/video/omap2/vrfb.c
drivers/watchdog/at91rm9200_wdt.c

index a0ffac029a0dc703322d922f3ec59435e3315ef3..1bea46a54b1ca252b5390c422f291dafe41a7c32 100644 (file)
@@ -510,17 +510,3 @@ Why:       The pci_scan_bus_parented() interface creates a new root bus.  The
        convert to using pci_scan_root_bus() so they can supply a list of
        bus resources when the bus is created.
 Who:   Bjorn Helgaas <bhelgaas@google.com>
-
-----------------------------
-
-What:  The CAP9 SoC family will be removed
-When:  3.4
-Files: arch/arm/mach-at91/at91cap9.c
-       arch/arm/mach-at91/at91cap9_devices.c
-       arch/arm/mach-at91/include/mach/at91cap9.h
-       arch/arm/mach-at91/include/mach/at91cap9_matrix.h
-       arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
-       arch/arm/mach-at91/board-cap9adk.c
-Why:   The code is not actively maintained and platforms are now hard to find.
-Who:   Nicolas Ferre <nicolas.ferre@atmel.com>
-       Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
index 7d809b7e0504eb345f1dfe355bc589db6cfd3ae3..31a2ddc2e4808a1e490e4ed6b020c37e2bc1446d 100644 (file)
@@ -217,6 +217,13 @@ config ARM_PATCH_PHYS_VIRT
          this feature (eg, building a kernel for a single machine) and
          you need to shrink the kernel to the minimal size.
 
+config NEED_MACH_IO_H
+       bool
+       help
+         Select this when mach/io.h is required to provide special
+         definitions for this platform.  The need for mach/io.h should
+         be avoided when possible.
+
 config NEED_MACH_MEMORY_H
        bool
        help
@@ -268,6 +275,7 @@ config ARCH_INTEGRATOR
        select GENERIC_CLOCKEVENTS
        select PLAT_VERSATILE
        select PLAT_VERSATILE_FPGA_IRQ
+       select NEED_MACH_IO_H
        select NEED_MACH_MEMORY_H
        help
          Support for ARM's Integrator platform.
@@ -327,7 +335,7 @@ config ARCH_AT91
        select CLKDEV_LOOKUP
        help
          This enables support for systems based on the Atmel AT91RM9200,
-         AT91SAM9 and AT91CAP9 processors.
+         AT91SAM9 processors.
 
 config ARCH_BCMRING
        bool "Broadcom BCMRING"
@@ -403,6 +411,7 @@ config ARCH_EBSA110
        select ISA
        select NO_IOPORT
        select ARCH_USES_GETTIMEOFFSET
+       select NEED_MACH_IO_H
        select NEED_MACH_MEMORY_H
        help
          This is an evaluation board for the StrongARM processor available
@@ -429,6 +438,7 @@ config ARCH_FOOTBRIDGE
        select FOOTBRIDGE
        select GENERIC_CLOCKEVENTS
        select HAVE_IDE
+       select NEED_MACH_IO_H
        select NEED_MACH_MEMORY_H
        help
          Support for systems based on the DC21285 companion chip
@@ -481,6 +491,7 @@ config ARCH_IOP13XX
        select PCI
        select ARCH_SUPPORTS_MSI
        select VMSPLIT_1G
+       select NEED_MACH_IO_H
        select NEED_MACH_MEMORY_H
        select NEED_RET_TO_USER
        help
@@ -490,6 +501,7 @@ config ARCH_IOP32X
        bool "IOP32x-based"
        depends on MMU
        select CPU_XSCALE
+       select NEED_MACH_IO_H
        select NEED_RET_TO_USER
        select PLAT_IOP
        select PCI
@@ -502,6 +514,7 @@ config ARCH_IOP33X
        bool "IOP33x-based"
        depends on MMU
        select CPU_XSCALE
+       select NEED_MACH_IO_H
        select NEED_RET_TO_USER
        select PLAT_IOP
        select PCI
@@ -515,6 +528,7 @@ config ARCH_IXP23XX
        select CPU_XSC3
        select PCI
        select ARCH_USES_GETTIMEOFFSET
+       select NEED_MACH_IO_H
        select NEED_MACH_MEMORY_H
        help
          Support for Intel's IXP23xx (XScale) family of processors.
@@ -525,6 +539,7 @@ config ARCH_IXP2000
        select CPU_XSCALE
        select PCI
        select ARCH_USES_GETTIMEOFFSET
+       select NEED_MACH_IO_H
        select NEED_MACH_MEMORY_H
        help
          Support for Intel's IXP2400/2800 (XScale) family of processors.
@@ -538,6 +553,7 @@ config ARCH_IXP4XX
        select GENERIC_CLOCKEVENTS
        select HAVE_SCHED_CLOCK
        select MIGHT_HAVE_PCI
+       select NEED_MACH_IO_H
        select DMABOUNCE if PCI
        help
          Support for Intel's IXP4XX (XScale) family of processors.
@@ -548,6 +564,7 @@ config ARCH_DOVE
        select PCI
        select ARCH_REQUIRE_GPIOLIB
        select GENERIC_CLOCKEVENTS
+       select NEED_MACH_IO_H
        select PLAT_ORION
        help
          Support for the Marvell Dove SoC 88AP510
@@ -558,6 +575,7 @@ config ARCH_KIRKWOOD
        select PCI
        select ARCH_REQUIRE_GPIOLIB
        select GENERIC_CLOCKEVENTS
+       select NEED_MACH_IO_H
        select PLAT_ORION
        help
          Support for the following Marvell Kirkwood series SoCs:
@@ -582,6 +600,7 @@ config ARCH_MV78XX0
        select PCI
        select ARCH_REQUIRE_GPIOLIB
        select GENERIC_CLOCKEVENTS
+       select NEED_MACH_IO_H
        select PLAT_ORION
        help
          Support for the following Marvell MV78xx0 series SoCs:
@@ -651,6 +670,7 @@ config ARCH_TEGRA
        select HAVE_SCHED_CLOCK
        select HAVE_SMP
        select MIGHT_HAVE_CACHE_L2X0
+       select NEED_MACH_IO_H if PCI
        select ARCH_HAS_CPUFREQ
        help
          This enables support for NVIDIA Tegra based systems (Tegra APX,
@@ -745,6 +765,7 @@ config ARCH_RPC
        select ARCH_SPARSEMEM_ENABLE
        select ARCH_USES_GETTIMEOFFSET
        select HAVE_IDE
+       select NEED_MACH_IO_H
        select NEED_MACH_MEMORY_H
        help
          On the Acorn Risc-PC, Linux can support the internal IDE disk and
@@ -777,6 +798,7 @@ config ARCH_S3C2410
        select CLKDEV_LOOKUP
        select ARCH_USES_GETTIMEOFFSET
        select HAVE_S3C2410_I2C if I2C
+       select NEED_MACH_IO_H
        help
          Samsung S3C2410X CPU based systems, such as the Simtec Electronics
          BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
@@ -883,6 +905,7 @@ config ARCH_SHARK
        select PCI
        select ARCH_USES_GETTIMEOFFSET
        select NEED_MACH_MEMORY_H
+       select NEED_MACH_IO_H
        help
          Support for the StrongARM based Digital DNARD machine, also known
          as "Shark" (<http://www.shark-linux.de/shark.html>).
index 03646c4c13d18becdccfcbf3897a25fa53e3a31e..b895a2a92da8186f5eda5aa04a5ee9ee51410cd1 100644 (file)
@@ -86,7 +86,7 @@ choice
                depends on HAVE_AT91_DBGU0
 
        config AT91_DEBUG_LL_DBGU1
-               bool "Kernel low-level debugging on 9263, 9g45 and cap9"
+               bool "Kernel low-level debugging on 9263 and 9g45"
                depends on HAVE_AT91_DBGU1
 
        config DEBUG_CLPS711X_UART1
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
new file mode 100644 (file)
index 0000000..e64eb93
--- /dev/null
@@ -0,0 +1,37 @@
+/*
+ * at91sam9g25ek.dts - Device Tree file for AT91SAM9G25-EK board
+ *
+ *  Copyright (C) 2012 Atmel,
+ *                2012 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "at91sam9x5.dtsi"
+/include/ "at91sam9x5cm.dtsi"
+
+/ {
+       model = "Atmel AT91SAM9G25-EK";
+       compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
+
+       chosen {
+               bootargs = "128M console=ttyS0,115200 mtdparts=atmel_nand:8M(bootstrap/uboot/kernel)ro,-(rootfs) root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
+       };
+
+       ahb {
+               apb {
+                       dbgu: serial@fffff200 {
+                               status = "okay";
+                       };
+
+                       usart0: serial@f801c000 {
+                               status = "okay";
+                       };
+
+                       macb0: ethernet@f802c000 {
+                               phy-mode = "rmii";
+                               status = "okay";
+                       };
+               };
+       };
+};
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
new file mode 100644 (file)
index 0000000..e91391f
--- /dev/null
@@ -0,0 +1,172 @@
+/*
+ * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
+ *                   applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
+ *                   AT91SAM9X25, AT91SAM9X35 SoC
+ *
+ *  Copyright (C) 2012 Atmel,
+ *                2012 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+       model = "Atmel AT91SAM9x5 family SoC";
+       compatible = "atmel,at91sam9x5";
+       interrupt-parent = <&aic>;
+
+       aliases {
+               serial0 = &dbgu;
+               serial1 = &usart0;
+               serial2 = &usart1;
+               serial3 = &usart2;
+               gpio0 = &pioA;
+               gpio1 = &pioB;
+               gpio2 = &pioC;
+               gpio3 = &pioD;
+               tcb0 = &tcb0;
+               tcb1 = &tcb1;
+       };
+       cpus {
+               cpu@0 {
+                       compatible = "arm,arm926ejs";
+               };
+       };
+
+       memory@20000000 {
+               reg = <0x20000000 0x10000000>;
+       };
+
+       ahb {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+               apb {
+                       compatible = "simple-bus";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+
+                       aic: interrupt-controller@fffff000 {
+                               #interrupt-cells = <2>;
+                               compatible = "atmel,at91rm9200-aic";
+                               interrupt-controller;
+                               interrupt-parent;
+                               reg = <0xfffff000 0x200>;
+                       };
+
+                       pit: timer@fffffe30 {
+                               compatible = "atmel,at91sam9260-pit";
+                               reg = <0xfffffe30 0xf>;
+                               interrupts = <1 4>;
+                       };
+
+                       tcb0: timer@f8008000 {
+                               compatible = "atmel,at91sam9x5-tcb";
+                               reg = <0xf8008000 0x100>;
+                               interrupts = <17 4>;
+                       };
+
+                       tcb1: timer@f800c000 {
+                               compatible = "atmel,at91sam9x5-tcb";
+                               reg = <0xf800c000 0x100>;
+                               interrupts = <17 4>;
+                       };
+
+                       dma0: dma-controller@ffffec00 {
+                               compatible = "atmel,at91sam9g45-dma";
+                               reg = <0xffffec00 0x200>;
+                               interrupts = <20 4>;
+                       };
+
+                       dma1: dma-controller@ffffee00 {
+                               compatible = "atmel,at91sam9g45-dma";
+                               reg = <0xffffee00 0x200>;
+                               interrupts = <21 4>;
+                       };
+
+                       pioA: gpio@fffff400 {
+                               compatible = "atmel,at91rm9200-gpio";
+                               reg = <0xfffff400 0x100>;
+                               interrupts = <2 4>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                       };
+
+                       pioB: gpio@fffff600 {
+                               compatible = "atmel,at91rm9200-gpio";
+                               reg = <0xfffff600 0x100>;
+                               interrupts = <2 4>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                       };
+
+                       pioC: gpio@fffff800 {
+                               compatible = "atmel,at91rm9200-gpio";
+                               reg = <0xfffff800 0x100>;
+                               interrupts = <3 4>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                       };
+
+                       pioD: gpio@fffffa00 {
+                               compatible = "atmel,at91rm9200-gpio";
+                               reg = <0xfffffa00 0x100>;
+                               interrupts = <3 4>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                       };
+
+                       dbgu: serial@fffff200 {
+                               compatible = "atmel,at91sam9260-usart";
+                               reg = <0xfffff200 0x200>;
+                               interrupts = <1 4>;
+                               status = "disabled";
+                       };
+
+                       usart0: serial@f801c000 {
+                               compatible = "atmel,at91sam9260-usart";
+                               reg = <0xf801c000 0x200>;
+                               interrupts = <5 4>;
+                               atmel,use-dma-rx;
+                               atmel,use-dma-tx;
+                               status = "disabled";
+                       };
+
+                       usart1: serial@f8020000 {
+                               compatible = "atmel,at91sam9260-usart";
+                               reg = <0xf8020000 0x200>;
+                               interrupts = <6 4>;
+                               atmel,use-dma-rx;
+                               atmel,use-dma-tx;
+                               status = "disabled";
+                       };
+
+                       usart2: serial@f8024000 {
+                               compatible = "atmel,at91sam9260-usart";
+                               reg = <0xf8024000 0x200>;
+                               interrupts = <7 4>;
+                               atmel,use-dma-rx;
+                               atmel,use-dma-tx;
+                               status = "disabled";
+                       };
+
+                       macb0: ethernet@f802c000 {
+                               compatible = "cdns,at32ap7000-macb", "cdns,macb";
+                               reg = <0xf802c000 0x100>;
+                               interrupts = <24 4>;
+                               status = "disabled";
+                       };
+
+                       macb1: ethernet@f8030000 {
+                               compatible = "cdns,at32ap7000-macb", "cdns,macb";
+                               reg = <0xf8030000 0x100>;
+                               interrupts = <27 4>;
+                               status = "disabled";
+                       };
+               };
+       };
+};
diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi
new file mode 100644 (file)
index 0000000..4ab5a77
--- /dev/null
@@ -0,0 +1,14 @@
+/*
+ * at91sam9x5cm.dtsi - Device Tree Include file for AT91SAM9x5 CPU Module
+ *
+ *  Copyright (C) 2012 Atmel,
+ *                2012 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/ {
+       memory@20000000 {
+               reg = <0x20000000 0x8000000>;
+       };
+};
diff --git a/arch/arm/configs/at91cap9_defconfig b/arch/arm/configs/at91cap9_defconfig
deleted file mode 100644 (file)
index 8826eb2..0000000
+++ /dev/null
@@ -1,108 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91CAP9=y
-CONFIG_MACH_AT91CAP9ADK=y
-CONFIG_MTD_AT91_DATAFLASH_CARD=y
-CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_AEABI=y
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/ram0 rw"
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_DATAFLASH=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ATMEL=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_NETDEVICES=y
-CONFIG_MII=y
-CONFIG_MACB=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=y
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_SPI=y
-CONFIG_SPI_ATMEL=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_FB=y
-CONFIG_FB_ATMEL=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-# CONFIG_USB_HID is not set
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=m
-CONFIG_USB_FILE_STORAGE=m
-CONFIG_MMC=y
-CONFIG_MMC_AT91=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_AT91SAM9=y
-CONFIG_EXT2_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_CRAMFS=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_USER=y
index 62f8095d46de8f4f2b4fad93c4338ac5df54fa7e..88374dd30fb9f836b12c8ffa41d9247bcda504b2 100644 (file)
@@ -23,6 +23,8 @@
 #include <asm/ptrace.h>
 #include <asm/domain.h>
 
+#define IOMEM(x)       (x)
+
 /*
  * Endian independent macros for shifting bytes within registers.
  */
index 9275828feb3df24f481934a080572f8d53be3136..35d91406af65f9e926823ef9de6de90bb69c3248 100644 (file)
@@ -83,6 +83,11 @@ extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, uns
 extern void __iomem *__arm_ioremap(unsigned long, size_t, unsigned int);
 extern void __iomem *__arm_ioremap_exec(unsigned long, size_t, bool cached);
 extern void __iounmap(volatile void __iomem *addr);
+extern void __arm_iounmap(volatile void __iomem *addr);
+
+extern void __iomem * (*arch_ioremap_caller)(unsigned long, size_t,
+       unsigned int, void *);
+extern void (*arch_iounmap)(volatile void __iomem *);
 
 /*
  * Bad read/write accesses...
@@ -97,6 +102,8 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
        return (void __iomem *)addr;
 }
 
+#define IOMEM(x)       ((void __force __iomem *)(x))
+
 /* IO barriers */
 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
 #define __iormb()              rmb()
@@ -109,7 +116,11 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
 /*
  * Now, pick up the machine-defined IO definitions
  */
+#ifdef CONFIG_NEED_MACH_IO_H
 #include <mach/io.h>
+#else
+#define __io(a)                ({ (void)(a); __typesafe_io(0); })
+#endif
 
 /*
  * This is the limit of PC card/PCI/ISA IO space, which is by default
@@ -211,18 +222,18 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
  * Again, this are defined to perform little endian accesses.  See the
  * IO port primitives for more information.
  */
-#ifdef __mem_pci
-#define readb_relaxed(c) ({ u8  __r = __raw_readb(__mem_pci(c)); __r; })
+#ifndef readl
+#define readb_relaxed(c) ({ u8  __r = __raw_readb(c); __r; })
 #define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
-                                       __raw_readw(__mem_pci(c))); __r; })
+                                       __raw_readw(c)); __r; })
 #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
-                                       __raw_readl(__mem_pci(c))); __r; })
+                                       __raw_readl(c)); __r; })
 
-#define writeb_relaxed(v,c)    ((void)__raw_writeb(v,__mem_pci(c)))
+#define writeb_relaxed(v,c)    ((void)__raw_writeb(v,c))
 #define writew_relaxed(v,c)    ((void)__raw_writew((__force u16) \
-                                       cpu_to_le16(v),__mem_pci(c)))
+                                       cpu_to_le16(v),c))
 #define writel_relaxed(v,c)    ((void)__raw_writel((__force u32) \
-                                       cpu_to_le32(v),__mem_pci(c)))
+                                       cpu_to_le32(v),c))
 
 #define readb(c)               ({ u8  __v = readb_relaxed(c); __iormb(); __v; })
 #define readw(c)               ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
@@ -232,30 +243,19 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
 #define writew(v,c)            ({ __iowmb(); writew_relaxed(v,c); })
 #define writel(v,c)            ({ __iowmb(); writel_relaxed(v,c); })
 
-#define readsb(p,d,l)          __raw_readsb(__mem_pci(p),d,l)
-#define readsw(p,d,l)          __raw_readsw(__mem_pci(p),d,l)
-#define readsl(p,d,l)          __raw_readsl(__mem_pci(p),d,l)
-
-#define writesb(p,d,l)         __raw_writesb(__mem_pci(p),d,l)
-#define writesw(p,d,l)         __raw_writesw(__mem_pci(p),d,l)
-#define writesl(p,d,l)         __raw_writesl(__mem_pci(p),d,l)
+#define readsb(p,d,l)          __raw_readsb(p,d,l)
+#define readsw(p,d,l)          __raw_readsw(p,d,l)
+#define readsl(p,d,l)          __raw_readsl(p,d,l)
 
-#define memset_io(c,v,l)       _memset_io(__mem_pci(c),(v),(l))
-#define memcpy_fromio(a,c,l)   _memcpy_fromio((a),__mem_pci(c),(l))
-#define memcpy_toio(c,a,l)     _memcpy_toio(__mem_pci(c),(a),(l))
+#define writesb(p,d,l)         __raw_writesb(p,d,l)
+#define writesw(p,d,l)         __raw_writesw(p,d,l)
+#define writesl(p,d,l)         __raw_writesl(p,d,l)
 
-#elif !defined(readb)
+#define memset_io(c,v,l)       _memset_io(c,(v),(l))
+#define memcpy_fromio(a,c,l)   _memcpy_fromio((a),c,(l))
+#define memcpy_toio(c,a,l)     _memcpy_toio(c,(a),(l))
 
-#define readb(c)                       (__readwrite_bug("readb"),0)
-#define readw(c)                       (__readwrite_bug("readw"),0)
-#define readl(c)                       (__readwrite_bug("readl"),0)
-#define writeb(v,c)                    __readwrite_bug("writeb")
-#define writew(v,c)                    __readwrite_bug("writew")
-#define writel(v,c)                    __readwrite_bug("writel")
-
-#define check_signature(io,sig,len)    (0)
-
-#endif /* __mem_pci */
+#endif /* readl */
 
 /*
  * ioremap and friends.
@@ -264,16 +264,11 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
  * Documentation/io-mapping.txt.
  *
  */
-#ifndef __arch_ioremap
-#define __arch_ioremap                 __arm_ioremap
-#define __arch_iounmap                 __iounmap
-#endif
-
-#define ioremap(cookie,size)           __arch_ioremap((cookie), (size), MT_DEVICE)
-#define ioremap_nocache(cookie,size)   __arch_ioremap((cookie), (size), MT_DEVICE)
-#define ioremap_cached(cookie,size)    __arch_ioremap((cookie), (size), MT_DEVICE_CACHED)
-#define ioremap_wc(cookie,size)                __arch_ioremap((cookie), (size), MT_DEVICE_WC)
-#define iounmap                                __arch_iounmap
+#define ioremap(cookie,size)           __arm_ioremap((cookie), (size), MT_DEVICE)
+#define ioremap_nocache(cookie,size)   __arm_ioremap((cookie), (size), MT_DEVICE)
+#define ioremap_cached(cookie,size)    __arm_ioremap((cookie), (size), MT_DEVICE_CACHED)
+#define ioremap_wc(cookie,size)                __arm_ioremap((cookie), (size), MT_DEVICE_WC)
+#define iounmap                                __arm_iounmap
 
 /*
  * io{read,write}{8,16,32} macros
index 204e2160cfccbdd5fa88a00285086d73a522ebcb..501cdbfc902c3b7968caa450b887ac496abd5ed7 100644 (file)
@@ -10,6 +10,7 @@
  *  32-bit debugging code
  */
 #include <linux/linkage.h>
+#include <asm/assembler.h>
 
                .text
 
index 22f0ed324f370b904279a349167ceba3a5ec8c5a..395f6271dfc268c3e5d2f92c44e9860a062192e7 100644 (file)
@@ -15,6 +15,7 @@
  *  that causes it to save wrong values...  Be aware!
  */
 
+#include <asm/assembler.h>
 #include <asm/memory.h>
 #include <asm/glue-df.h>
 #include <asm/glue-pf.h>
index 71feb00a1e995de0991b54189569b04c1cf02f06..e55cdcbd81fb5ce8970769cfcf02e38f3392cec6 100644 (file)
@@ -102,13 +102,13 @@ config ARCH_AT91SAM9G45
        select HAVE_AT91_DBGU1
        select AT91_SAM9G45_RESET
 
-config ARCH_AT91CAP9
-       bool "AT91CAP9"
+config ARCH_AT91SAM9X5
+       bool "AT91SAM9x5 family"
        select CPU_ARM926T
        select GENERIC_CLOCKEVENTS
        select HAVE_FB_ATMEL
        select HAVE_NET_MACB
-       select HAVE_AT91_DBGU1
+       select HAVE_AT91_DBGU0
        select AT91_SAM9G45_RESET
 
 config ARCH_AT91X40
@@ -447,21 +447,6 @@ endif
 
 # ----------------------------------------------------------
 
-if ARCH_AT91CAP9
-
-comment "AT91CAP9 Board Type"
-
-config MACH_AT91CAP9ADK
-       bool "Atmel AT91CAP9A-DK Evaluation Kit"
-       select HAVE_AT91_DATAFLASH_CARD
-       help
-         Select this if you are using Atmel's AT91CAP9A-DK Evaluation Kit.
-         <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4138>
-
-endif
-
-# ----------------------------------------------------------
-
 if ARCH_AT91X40
 
 comment "AT91X40 Board Type"
@@ -544,7 +529,7 @@ config AT91_EARLY_DBGU0
        depends on HAVE_AT91_DBGU0
 
 config AT91_EARLY_DBGU1
-       bool "DBGU on 9263, 9g45 and cap9"
+       bool "DBGU on 9263 and 9g45"
        depends on HAVE_AT91_DBGU1
 
 config AT91_EARLY_USART0
index 705e1fbded3919112efb5858ec921d49e05d1eaa..1b6518518d99e4e9c0ba2fddff74fb62ae766060 100644 (file)
@@ -20,7 +20,7 @@ obj-$(CONFIG_ARCH_AT91SAM9263)        += at91sam9263.o at91sam926x_time.o at91sam9263_d
 obj-$(CONFIG_ARCH_AT91SAM9RL)  += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
-obj-$(CONFIG_ARCH_AT91CAP9)    += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
+obj-$(CONFIG_ARCH_AT91SAM9X5)  += at91sam9x5.o at91sam926x_time.o
 obj-$(CONFIG_ARCH_AT91X40)     += at91x40.o at91x40_time.o
 
 # AT91RM9200 board-specific support
@@ -81,9 +81,6 @@ obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
 # AT91SAM board with device-tree
 obj-$(CONFIG_MACH_AT91SAM_DT) += board-dt.o
 
-# AT91CAP9 board-specific support
-obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o
-
 # AT91X40 board-specific support
 obj-$(CONFIG_MACH_AT91EB01)    += board-eb01.o
 
index 8ddafadfdc7dc94ac5f8319c5f56dc15fe798e8f..0da66ca4a4f83329dfd290b9582abb2b396153db 100644 (file)
@@ -3,11 +3,7 @@
 #   PARAMS_PHYS must be within 4MB of ZRELADDR
 #   INITRD_PHYS must be in RAM
 
-ifeq ($(CONFIG_ARCH_AT91CAP9),y)
-   zreladdr-y  += 0x70008000
-params_phys-y  := 0x70000100
-initrd_phys-y  := 0x70410000
-else ifeq ($(CONFIG_ARCH_AT91SAM9G45),y)
+ifeq ($(CONFIG_ARCH_AT91SAM9G45),y)
    zreladdr-y  += 0x70008000
 params_phys-y  := 0x70000100
 initrd_phys-y  := 0x70410000
@@ -17,4 +13,10 @@ params_phys-y        := 0x20000100
 initrd_phys-y  := 0x20410000
 endif
 
-dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb usb_a9g20.dtb
+# Keep dtb files sorted alphabetically for each SoC
+# sam9g20
+dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9g20.dtb
+# sam9g45
+dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb
+# sam9x5
+dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g25ek.dtb
diff --git a/arch/arm/mach-at91/at91cap9.c b/arch/arm/mach-at91/at91cap9.c
deleted file mode 100644 (file)
index 8967d75..0000000
+++ /dev/null
@@ -1,404 +0,0 @@
-/*
- * arch/arm/mach-at91/at91cap9.c
- *
- *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
- *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
- *  Copyright (C) 2007 Atmel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-
-#include <linux/module.h>
-
-#include <asm/proc-fns.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include <mach/cpu.h>
-#include <mach/at91cap9.h>
-#include <mach/at91_pmc.h>
-
-#include "soc.h"
-#include "generic.h"
-#include "clock.h"
-#include "sam9_smc.h"
-
-/* --------------------------------------------------------------------
- *  Clocks
- * -------------------------------------------------------------------- */
-
-/*
- * The peripheral clocks.
- */
-static struct clk pioABCD_clk = {
-       .name           = "pioABCD_clk",
-       .pmc_mask       = 1 << AT91CAP9_ID_PIOABCD,
-       .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mpb0_clk = {
-       .name           = "mpb0_clk",
-       .pmc_mask       = 1 << AT91CAP9_ID_MPB0,
-       .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mpb1_clk = {
-       .name           = "mpb1_clk",
-       .pmc_mask       = 1 << AT91CAP9_ID_MPB1,
-       .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mpb2_clk = {
-       .name           = "mpb2_clk",
-       .pmc_mask       = 1 << AT91CAP9_ID_MPB2,
-       .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mpb3_clk = {
-       .name           = "mpb3_clk",
-       .pmc_mask       = 1 << AT91CAP9_ID_MPB3,
-       .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mpb4_clk = {
-       .name           = "mpb4_clk",
-       .pmc_mask       = 1 << AT91CAP9_ID_MPB4,
-       .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
-       .name           = "usart0_clk",
-       .pmc_mask       = 1 << AT91CAP9_ID_US0,
-       .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
-       .name           = "usart1_clk",
-       .pmc_mask       = 1 << AT91CAP9_ID_US1,
-       .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
-       .name           = "usart2_clk",
-       .pmc_mask       = 1 << AT91CAP9_ID_US2,
-       .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc0_clk = {
-       .name           = "mci0_clk",
-       .pmc_mask       = 1 << AT91CAP9_ID_MCI0,
-       .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc1_clk = {
-       .name           = "mci1_clk",
-       .pmc_mask       = 1 << AT91CAP9_ID_MCI1,
-       .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk can_clk = {
-       .name           = "can_clk",
-       .pmc_mask       = 1 << AT91CAP9_ID_CAN,
-       .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi_clk = {
-       .name           = "twi_clk",
-       .pmc_mask       = 1 << AT91CAP9_ID_TWI,
-       .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi0_clk = {
-       .name           = "spi0_clk",
-       .pmc_mask       = 1 << AT91CAP9_ID_SPI0,
-       .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi1_clk = {
-       .name           = "spi1_clk",
-       .pmc_mask       = 1 << AT91CAP9_ID_SPI1,
-       .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc0_clk = {
-       .name           = "ssc0_clk",
-       .pmc_mask       = 1 << AT91CAP9_ID_SSC0,
-       .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc1_clk = {
-       .name           = "ssc1_clk",
-       .pmc_mask       = 1 << AT91CAP9_ID_SSC1,
-       .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ac97_clk = {
-       .name           = "ac97_clk",
-       .pmc_mask       = 1 << AT91CAP9_ID_AC97C,
-       .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tcb_clk = {
-       .name           = "tcb_clk",
-       .pmc_mask       = 1 << AT91CAP9_ID_TCB,
-       .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pwm_clk = {
-       .name           = "pwm_clk",
-       .pmc_mask       = 1 << AT91CAP9_ID_PWMC,
-       .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk macb_clk = {
-       .name           = "pclk",
-       .pmc_mask       = 1 << AT91CAP9_ID_EMAC,
-       .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk aestdes_clk = {
-       .name           = "aestdes_clk",
-       .pmc_mask       = 1 << AT91CAP9_ID_AESTDES,
-       .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk adc_clk = {
-       .name           = "adc_clk",
-       .pmc_mask       = 1 << AT91CAP9_ID_ADC,
-       .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk isi_clk = {
-       .name           = "isi_clk",
-       .pmc_mask       = 1 << AT91CAP9_ID_ISI,
-       .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk lcdc_clk = {
-       .name           = "lcdc_clk",
-       .pmc_mask       = 1 << AT91CAP9_ID_LCDC,
-       .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk dma_clk = {
-       .name           = "dma_clk",
-       .pmc_mask       = 1 << AT91CAP9_ID_DMA,
-       .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udphs_clk = {
-       .name           = "udphs_clk",
-       .pmc_mask       = 1 << AT91CAP9_ID_UDPHS,
-       .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ohci_clk = {
-       .name           = "ohci_clk",
-       .pmc_mask       = 1 << AT91CAP9_ID_UHP,
-       .type           = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk *periph_clocks[] __initdata = {
-       &pioABCD_clk,
-       &mpb0_clk,
-       &mpb1_clk,
-       &mpb2_clk,
-       &mpb3_clk,
-       &mpb4_clk,
-       &usart0_clk,
-       &usart1_clk,
-       &usart2_clk,
-       &mmc0_clk,
-       &mmc1_clk,
-       &can_clk,
-       &twi_clk,
-       &spi0_clk,
-       &spi1_clk,
-       &ssc0_clk,
-       &ssc1_clk,
-       &ac97_clk,
-       &tcb_clk,
-       &pwm_clk,
-       &macb_clk,
-       &aestdes_clk,
-       &adc_clk,
-       &isi_clk,
-       &lcdc_clk,
-       &dma_clk,
-       &udphs_clk,
-       &ohci_clk,
-       // irq0 .. irq1
-};
-
-static struct clk_lookup periph_clocks_lookups[] = {
-       /* One additional fake clock for macb_hclk */
-       CLKDEV_CON_ID("hclk", &macb_clk),
-       CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
-       CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
-       CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
-       CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
-       CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
-       CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
-       CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
-       CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
-       CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
-       /* fake hclk clock */
-       CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
-       CLKDEV_CON_ID("pioA", &pioABCD_clk),
-       CLKDEV_CON_ID("pioB", &pioABCD_clk),
-       CLKDEV_CON_ID("pioC", &pioABCD_clk),
-       CLKDEV_CON_ID("pioD", &pioABCD_clk),
-};
-
-static struct clk_lookup usart_clocks_lookups[] = {
-       CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
-       CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
-       CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
-       CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
-};
-
-/*
- * The four programmable clocks.
- * You must configure pin multiplexing to bring these signals out.
- */
-static struct clk pck0 = {
-       .name           = "pck0",
-       .pmc_mask       = AT91_PMC_PCK0,
-       .type           = CLK_TYPE_PROGRAMMABLE,
-       .id             = 0,
-};
-static struct clk pck1 = {
-       .name           = "pck1",
-       .pmc_mask       = AT91_PMC_PCK1,
-       .type           = CLK_TYPE_PROGRAMMABLE,
-       .id             = 1,
-};
-static struct clk pck2 = {
-       .name           = "pck2",
-       .pmc_mask       = AT91_PMC_PCK2,
-       .type           = CLK_TYPE_PROGRAMMABLE,
-       .id             = 2,
-};
-static struct clk pck3 = {
-       .name           = "pck3",
-       .pmc_mask       = AT91_PMC_PCK3,
-       .type           = CLK_TYPE_PROGRAMMABLE,
-       .id             = 3,
-};
-
-static void __init at91cap9_register_clocks(void)
-{
-       int i;
-
-       for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
-               clk_register(periph_clocks[i]);
-
-       clkdev_add_table(periph_clocks_lookups,
-                        ARRAY_SIZE(periph_clocks_lookups));
-       clkdev_add_table(usart_clocks_lookups,
-                        ARRAY_SIZE(usart_clocks_lookups));
-
-       clk_register(&pck0);
-       clk_register(&pck1);
-       clk_register(&pck2);
-       clk_register(&pck3);
-}
-
-static struct clk_lookup console_clock_lookup;
-
-void __init at91cap9_set_console_clock(int id)
-{
-       if (id >= ARRAY_SIZE(usart_clocks_lookups))
-               return;
-
-       console_clock_lookup.con_id = "usart";
-       console_clock_lookup.clk = usart_clocks_lookups[id].clk;
-       clkdev_add(&console_clock_lookup);
-}
-
-/* --------------------------------------------------------------------
- *  GPIO
- * -------------------------------------------------------------------- */
-
-static struct at91_gpio_bank at91cap9_gpio[] __initdata = {
-       {
-               .id             = AT91CAP9_ID_PIOABCD,
-               .regbase        = AT91CAP9_BASE_PIOA,
-       }, {
-               .id             = AT91CAP9_ID_PIOABCD,
-               .regbase        = AT91CAP9_BASE_PIOB,
-       }, {
-               .id             = AT91CAP9_ID_PIOABCD,
-               .regbase        = AT91CAP9_BASE_PIOC,
-       }, {
-               .id             = AT91CAP9_ID_PIOABCD,
-               .regbase        = AT91CAP9_BASE_PIOD,
-       }
-};
-
-static void at91cap9_idle(void)
-{
-       at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
-       cpu_do_idle();
-}
-
-/* --------------------------------------------------------------------
- *  AT91CAP9 processor initialization
- * -------------------------------------------------------------------- */
-
-static void __init at91cap9_map_io(void)
-{
-       at91_init_sram(0, AT91CAP9_SRAM_BASE, AT91CAP9_SRAM_SIZE);
-}
-
-static void __init at91cap9_ioremap_registers(void)
-{
-       at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC);
-       at91_ioremap_rstc(AT91CAP9_BASE_RSTC);
-       at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT);
-       at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC);
-}
-
-static void __init at91cap9_initialize(void)
-{
-       arm_pm_idle = at91cap9_idle;
-       arm_pm_restart = at91sam9g45_restart;
-       at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
-
-       /* Register GPIO subsystem */
-       at91_gpio_init(at91cap9_gpio, 4);
-
-       /* Remember the silicon revision */
-       if (cpu_is_at91cap9_revB())
-               system_rev = 0xB;
-       else if (cpu_is_at91cap9_revC())
-               system_rev = 0xC;
-}
-
-/* --------------------------------------------------------------------
- *  Interrupt initialization
- * -------------------------------------------------------------------- */
-
-/*
- * The default interrupt priority levels (0 = lowest, 7 = highest).
- */
-static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = {
-       7,      /* Advanced Interrupt Controller (FIQ) */
-       7,      /* System Peripherals */
-       1,      /* Parallel IO Controller A, B, C and D */
-       0,      /* MP Block Peripheral 0 */
-       0,      /* MP Block Peripheral 1 */
-       0,      /* MP Block Peripheral 2 */
-       0,      /* MP Block Peripheral 3 */
-       0,      /* MP Block Peripheral 4 */
-       5,      /* USART 0 */
-       5,      /* USART 1 */
-       5,      /* USART 2 */
-       0,      /* Multimedia Card Interface 0 */
-       0,      /* Multimedia Card Interface 1 */
-       3,      /* CAN */
-       6,      /* Two-Wire Interface */
-       5,      /* Serial Peripheral Interface 0 */
-       5,      /* Serial Peripheral Interface 1 */
-       4,      /* Serial Synchronous Controller 0 */
-       4,      /* Serial Synchronous Controller 1 */
-       5,      /* AC97 Controller */
-       0,      /* Timer Counter 0, 1 and 2 */
-       0,      /* Pulse Width Modulation Controller */
-       3,      /* Ethernet */
-       0,      /* Advanced Encryption Standard, Triple DES*/
-       0,      /* Analog-to-Digital Converter */
-       0,      /* Image Sensor Interface */
-       3,      /* LCD Controller */
-       0,      /* DMA Controller */
-       2,      /* USB Device Port */
-       2,      /* USB Host port */
-       0,      /* Advanced Interrupt Controller (IRQ0) */
-       0,      /* Advanced Interrupt Controller (IRQ1) */
-};
-
-struct at91_init_soc __initdata at91cap9_soc = {
-       .map_io = at91cap9_map_io,
-       .default_irq_priority = at91cap9_default_irq_priority,
-       .ioremap_registers = at91cap9_ioremap_registers,
-       .register_clocks = at91cap9_register_clocks,
-       .init = at91cap9_initialize,
-};
diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c
deleted file mode 100644 (file)
index d298fb7..0000000
+++ /dev/null
@@ -1,1273 +0,0 @@
-/*
- * arch/arm/mach-at91/at91cap9_devices.c
- *
- *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
- *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
- *  Copyright (C) 2007 Atmel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-#include <linux/platform_device.h>
-#include <linux/i2c-gpio.h>
-
-#include <video/atmel_lcdc.h>
-
-#include <mach/board.h>
-#include <mach/cpu.h>
-#include <mach/at91cap9.h>
-#include <mach/at91cap9_matrix.h>
-#include <mach/at91sam9_smc.h>
-
-#include "generic.h"
-
-
-/* --------------------------------------------------------------------
- *  USB Host
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-static u64 ohci_dmamask = DMA_BIT_MASK(32);
-static struct at91_usbh_data usbh_data;
-
-static struct resource usbh_resources[] = {
-       [0] = {
-               .start  = AT91CAP9_UHP_BASE,
-               .end    = AT91CAP9_UHP_BASE + SZ_1M - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = AT91CAP9_ID_UHP,
-               .end    = AT91CAP9_ID_UHP,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static struct platform_device at91_usbh_device = {
-       .name           = "at91_ohci",
-       .id             = -1,
-       .dev            = {
-                               .dma_mask               = &ohci_dmamask,
-                               .coherent_dma_mask      = DMA_BIT_MASK(32),
-                               .platform_data          = &usbh_data,
-       },
-       .resource       = usbh_resources,
-       .num_resources  = ARRAY_SIZE(usbh_resources),
-};
-
-void __init at91_add_device_usbh(struct at91_usbh_data *data)
-{
-       int i;
-
-       if (!data)
-               return;
-
-       if (cpu_is_at91cap9_revB())
-               irq_set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH);
-
-       /* Enable VBus control for UHP ports */
-       for (i = 0; i < data->ports; i++) {
-               if (gpio_is_valid(data->vbus_pin[i]))
-                       at91_set_gpio_output(data->vbus_pin[i], 0);
-       }
-
-       /* Enable overcurrent notification */
-       for (i = 0; i < data->ports; i++) {
-               if (data->overcurrent_pin[i])
-                       at91_set_gpio_input(data->overcurrent_pin[i], 1);
-       }
-
-       usbh_data = *data;
-       platform_device_register(&at91_usbh_device);
-}
-#else
-void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  USB HS Device (Gadget)
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_USB_ATMEL_USBA) || defined(CONFIG_USB_ATMEL_USBA_MODULE)
-
-static struct resource usba_udc_resources[] = {
-       [0] = {
-               .start  = AT91CAP9_UDPHS_FIFO,
-               .end    = AT91CAP9_UDPHS_FIFO + SZ_512K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = AT91CAP9_BASE_UDPHS,
-               .end    = AT91CAP9_BASE_UDPHS + SZ_1K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [2] = {
-               .start  = AT91CAP9_ID_UDPHS,
-               .end    = AT91CAP9_ID_UDPHS,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-#define EP(nam, idx, maxpkt, maxbk, dma, isoc)                 \
-       [idx] = {                                               \
-               .name           = nam,                          \
-               .index          = idx,                          \
-               .fifo_size      = maxpkt,                       \
-               .nr_banks       = maxbk,                        \
-               .can_dma        = dma,                          \
-               .can_isoc       = isoc,                         \
-       }
-
-static struct usba_ep_data usba_udc_ep[] = {
-       EP("ep0", 0,   64, 1, 0, 0),
-       EP("ep1", 1, 1024, 3, 1, 1),
-       EP("ep2", 2, 1024, 3, 1, 1),
-       EP("ep3", 3, 1024, 2, 1, 1),
-       EP("ep4", 4, 1024, 2, 1, 1),
-       EP("ep5", 5, 1024, 2, 1, 0),
-       EP("ep6", 6, 1024, 2, 1, 0),
-       EP("ep7", 7, 1024, 2, 0, 0),
-};
-
-#undef EP
-
-/*
- * pdata doesn't have room for any endpoints, so we need to
- * append room for the ones we need right after it.
- */
-static struct {
-       struct usba_platform_data pdata;
-       struct usba_ep_data ep[8];
-} usba_udc_data;
-
-static struct platform_device at91_usba_udc_device = {
-       .name           = "atmel_usba_udc",
-       .id             = -1,
-       .dev            = {
-                               .platform_data  = &usba_udc_data.pdata,
-       },
-       .resource       = usba_udc_resources,
-       .num_resources  = ARRAY_SIZE(usba_udc_resources),
-};
-
-void __init at91_add_device_usba(struct usba_platform_data *data)
-{
-       if (cpu_is_at91cap9_revB()) {
-               irq_set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH);
-               at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS |
-                                                 AT91_MATRIX_UDPHS_BYPASS_LOCK);
-       }
-       else
-               at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS);
-
-       /*
-        * Invalid pins are 0 on AT91, but the usba driver is shared
-        * with AVR32, which use negative values instead. Once/if
-        * gpio_is_valid() is ported to AT91, revisit this code.
-        */
-       usba_udc_data.pdata.vbus_pin = -EINVAL;
-       usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
-       memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
-
-       if (data && gpio_is_valid(data->vbus_pin)) {
-               at91_set_gpio_input(data->vbus_pin, 0);
-               at91_set_deglitch(data->vbus_pin, 1);
-               usba_udc_data.pdata.vbus_pin = data->vbus_pin;
-       }
-
-       /* Pullup pin is handled internally by USB device peripheral */
-
-       platform_device_register(&at91_usba_udc_device);
-}
-#else
-void __init at91_add_device_usba(struct usba_platform_data *data) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  Ethernet
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
-static u64 eth_dmamask = DMA_BIT_MASK(32);
-static struct macb_platform_data eth_data;
-
-static struct resource eth_resources[] = {
-       [0] = {
-               .start  = AT91CAP9_BASE_EMAC,
-               .end    = AT91CAP9_BASE_EMAC + SZ_16K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = AT91CAP9_ID_EMAC,
-               .end    = AT91CAP9_ID_EMAC,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static struct platform_device at91cap9_eth_device = {
-       .name           = "macb",
-       .id             = -1,
-       .dev            = {
-                               .dma_mask               = &eth_dmamask,
-                               .coherent_dma_mask      = DMA_BIT_MASK(32),
-                               .platform_data          = &eth_data,
-       },
-       .resource       = eth_resources,
-       .num_resources  = ARRAY_SIZE(eth_resources),
-};
-
-void __init at91_add_device_eth(struct macb_platform_data *data)
-{
-       if (!data)
-               return;
-
-       if (gpio_is_valid(data->phy_irq_pin)) {
-               at91_set_gpio_input(data->phy_irq_pin, 0);
-               at91_set_deglitch(data->phy_irq_pin, 1);
-       }
-
-       /* Pins used for MII and RMII */
-       at91_set_A_periph(AT91_PIN_PB21, 0);    /* ETXCK_EREFCK */
-       at91_set_A_periph(AT91_PIN_PB22, 0);    /* ERXDV */
-       at91_set_A_periph(AT91_PIN_PB25, 0);    /* ERX0 */
-       at91_set_A_periph(AT91_PIN_PB26, 0);    /* ERX1 */
-       at91_set_A_periph(AT91_PIN_PB27, 0);    /* ERXER */
-       at91_set_A_periph(AT91_PIN_PB28, 0);    /* ETXEN */
-       at91_set_A_periph(AT91_PIN_PB23, 0);    /* ETX0 */
-       at91_set_A_periph(AT91_PIN_PB24, 0);    /* ETX1 */
-       at91_set_A_periph(AT91_PIN_PB30, 0);    /* EMDIO */
-       at91_set_A_periph(AT91_PIN_PB29, 0);    /* EMDC */
-
-       if (!data->is_rmii) {
-               at91_set_B_periph(AT91_PIN_PC25, 0);    /* ECRS */
-               at91_set_B_periph(AT91_PIN_PC26, 0);    /* ECOL */
-               at91_set_B_periph(AT91_PIN_PC22, 0);    /* ERX2 */
-               at91_set_B_periph(AT91_PIN_PC23, 0);    /* ERX3 */
-               at91_set_B_periph(AT91_PIN_PC27, 0);    /* ERXCK */
-               at91_set_B_periph(AT91_PIN_PC20, 0);    /* ETX2 */
-               at91_set_B_periph(AT91_PIN_PC21, 0);    /* ETX3 */
-               at91_set_B_periph(AT91_PIN_PC24, 0);    /* ETXER */
-       }
-
-       eth_data = *data;
-       platform_device_register(&at91cap9_eth_device);
-}
-#else
-void __init at91_add_device_eth(struct macb_platform_data *data) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  MMC / SD
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
-static u64 mmc_dmamask = DMA_BIT_MASK(32);
-static struct at91_mmc_data mmc0_data, mmc1_data;
-
-static struct resource mmc0_resources[] = {
-       [0] = {
-               .start  = AT91CAP9_BASE_MCI0,
-               .end    = AT91CAP9_BASE_MCI0 + SZ_16K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = AT91CAP9_ID_MCI0,
-               .end    = AT91CAP9_ID_MCI0,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static struct platform_device at91cap9_mmc0_device = {
-       .name           = "at91_mci",
-       .id             = 0,
-       .dev            = {
-                               .dma_mask               = &mmc_dmamask,
-                               .coherent_dma_mask      = DMA_BIT_MASK(32),
-                               .platform_data          = &mmc0_data,
-       },
-       .resource       = mmc0_resources,
-       .num_resources  = ARRAY_SIZE(mmc0_resources),
-};
-
-static struct resource mmc1_resources[] = {
-       [0] = {
-               .start  = AT91CAP9_BASE_MCI1,
-               .end    = AT91CAP9_BASE_MCI1 + SZ_16K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = AT91CAP9_ID_MCI1,
-               .end    = AT91CAP9_ID_MCI1,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static struct platform_device at91cap9_mmc1_device = {
-       .name           = "at91_mci",
-       .id             = 1,
-       .dev            = {
-                               .dma_mask               = &mmc_dmamask,
-                               .coherent_dma_mask      = DMA_BIT_MASK(32),
-                               .platform_data          = &mmc1_data,
-       },
-       .resource       = mmc1_resources,
-       .num_resources  = ARRAY_SIZE(mmc1_resources),
-};
-
-void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
-{
-       if (!data)
-               return;
-
-       /* input/irq */
-       if (gpio_is_valid(data->det_pin)) {
-               at91_set_gpio_input(data->det_pin, 1);
-               at91_set_deglitch(data->det_pin, 1);
-       }
-       if (gpio_is_valid(data->wp_pin))
-               at91_set_gpio_input(data->wp_pin, 1);
-       if (gpio_is_valid(data->vcc_pin))
-               at91_set_gpio_output(data->vcc_pin, 0);
-
-       if (mmc_id == 0) {              /* MCI0 */
-               /* CLK */
-               at91_set_A_periph(AT91_PIN_PA2, 0);
-
-               /* CMD */
-               at91_set_A_periph(AT91_PIN_PA1, 1);
-
-               /* DAT0, maybe DAT1..DAT3 */
-               at91_set_A_periph(AT91_PIN_PA0, 1);
-               if (data->wire4) {
-                       at91_set_A_periph(AT91_PIN_PA3, 1);
-                       at91_set_A_periph(AT91_PIN_PA4, 1);
-                       at91_set_A_periph(AT91_PIN_PA5, 1);
-               }
-
-               mmc0_data = *data;
-               platform_device_register(&at91cap9_mmc0_device);
-       } else {                        /* MCI1 */
-               /* CLK */
-               at91_set_A_periph(AT91_PIN_PA16, 0);
-
-               /* CMD */
-               at91_set_A_periph(AT91_PIN_PA17, 1);
-
-               /* DAT0, maybe DAT1..DAT3 */
-               at91_set_A_periph(AT91_PIN_PA18, 1);
-               if (data->wire4) {
-                       at91_set_A_periph(AT91_PIN_PA19, 1);
-                       at91_set_A_periph(AT91_PIN_PA20, 1);
-                       at91_set_A_periph(AT91_PIN_PA21, 1);
-               }
-
-               mmc1_data = *data;
-               platform_device_register(&at91cap9_mmc1_device);
-       }
-}
-#else
-void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  NAND / SmartMedia
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
-static struct atmel_nand_data nand_data;
-
-#define NAND_BASE      AT91_CHIPSELECT_3
-
-static struct resource nand_resources[] = {
-       [0] = {
-               .start  = NAND_BASE,
-               .end    = NAND_BASE + SZ_256M - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = AT91CAP9_BASE_ECC,
-               .end    = AT91CAP9_BASE_ECC + SZ_512 - 1,
-               .flags  = IORESOURCE_MEM,
-       }
-};
-
-static struct platform_device at91cap9_nand_device = {
-       .name           = "atmel_nand",
-       .id             = -1,
-       .dev            = {
-                               .platform_data  = &nand_data,
-       },
-       .resource       = nand_resources,
-       .num_resources  = ARRAY_SIZE(nand_resources),
-};
-
-void __init at91_add_device_nand(struct atmel_nand_data *data)
-{
-       unsigned long csa;
-
-       if (!data)
-               return;
-
-       csa = at91_sys_read(AT91_MATRIX_EBICSA);
-       at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
-
-       /* enable pin */
-       if (gpio_is_valid(data->enable_pin))
-               at91_set_gpio_output(data->enable_pin, 1);
-
-       /* ready/busy pin */
-       if (gpio_is_valid(data->rdy_pin))
-               at91_set_gpio_input(data->rdy_pin, 1);
-
-       /* card detect pin */
-       if (gpio_is_valid(data->det_pin))
-               at91_set_gpio_input(data->det_pin, 1);
-
-       nand_data = *data;
-       platform_device_register(&at91cap9_nand_device);
-}
-#else
-void __init at91_add_device_nand(struct atmel_nand_data *data) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  TWI (i2c)
- * -------------------------------------------------------------------- */
-
-/*
- * Prefer the GPIO code since the TWI controller isn't robust
- * (gets overruns and underruns under load) and can only issue
- * repeated STARTs in one scenario (the driver doesn't yet handle them).
- */
-#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
-
-static struct i2c_gpio_platform_data pdata = {
-       .sda_pin                = AT91_PIN_PB4,
-       .sda_is_open_drain      = 1,
-       .scl_pin                = AT91_PIN_PB5,
-       .scl_is_open_drain      = 1,
-       .udelay                 = 2,            /* ~100 kHz */
-};
-
-static struct platform_device at91cap9_twi_device = {
-       .name                   = "i2c-gpio",
-       .id                     = -1,
-       .dev.platform_data      = &pdata,
-};
-
-void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
-{
-       at91_set_GPIO_periph(AT91_PIN_PB4, 1);          /* TWD (SDA) */
-       at91_set_multi_drive(AT91_PIN_PB4, 1);
-
-       at91_set_GPIO_periph(AT91_PIN_PB5, 1);          /* TWCK (SCL) */
-       at91_set_multi_drive(AT91_PIN_PB5, 1);
-
-       i2c_register_board_info(0, devices, nr_devices);
-       platform_device_register(&at91cap9_twi_device);
-}
-
-#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
-
-static struct resource twi_resources[] = {
-       [0] = {
-               .start  = AT91CAP9_BASE_TWI,
-               .end    = AT91CAP9_BASE_TWI + SZ_16K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = AT91CAP9_ID_TWI,
-               .end    = AT91CAP9_ID_TWI,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static struct platform_device at91cap9_twi_device = {
-       .name           = "at91_i2c",
-       .id             = -1,
-       .resource       = twi_resources,
-       .num_resources  = ARRAY_SIZE(twi_resources),
-};
-
-void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
-{
-       /* pins used for TWI interface */
-       at91_set_B_periph(AT91_PIN_PB4, 0);             /* TWD */
-       at91_set_multi_drive(AT91_PIN_PB4, 1);
-
-       at91_set_B_periph(AT91_PIN_PB5, 0);             /* TWCK */
-       at91_set_multi_drive(AT91_PIN_PB5, 1);
-
-       i2c_register_board_info(0, devices, nr_devices);
-       platform_device_register(&at91cap9_twi_device);
-}
-#else
-void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
-#endif
-
-/* --------------------------------------------------------------------
- *  SPI
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
-static u64 spi_dmamask = DMA_BIT_MASK(32);
-
-static struct resource spi0_resources[] = {
-       [0] = {
-               .start  = AT91CAP9_BASE_SPI0,
-               .end    = AT91CAP9_BASE_SPI0 + SZ_16K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = AT91CAP9_ID_SPI0,
-               .end    = AT91CAP9_ID_SPI0,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static struct platform_device at91cap9_spi0_device = {
-       .name           = "atmel_spi",
-       .id             = 0,
-       .dev            = {
-                               .dma_mask               = &spi_dmamask,
-                               .coherent_dma_mask      = DMA_BIT_MASK(32),
-       },
-       .resource       = spi0_resources,
-       .num_resources  = ARRAY_SIZE(spi0_resources),
-};
-
-static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA5, AT91_PIN_PA3, AT91_PIN_PD0, AT91_PIN_PD1 };
-
-static struct resource spi1_resources[] = {
-       [0] = {
-               .start  = AT91CAP9_BASE_SPI1,
-               .end    = AT91CAP9_BASE_SPI1 + SZ_16K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = AT91CAP9_ID_SPI1,
-               .end    = AT91CAP9_ID_SPI1,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static struct platform_device at91cap9_spi1_device = {
-       .name           = "atmel_spi",
-       .id             = 1,
-       .dev            = {
-                               .dma_mask               = &spi_dmamask,
-                               .coherent_dma_mask      = DMA_BIT_MASK(32),
-       },
-       .resource       = spi1_resources,
-       .num_resources  = ARRAY_SIZE(spi1_resources),
-};
-
-static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB15, AT91_PIN_PB16, AT91_PIN_PB17, AT91_PIN_PB18 };
-
-void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
-{
-       int i;
-       unsigned long cs_pin;
-       short enable_spi0 = 0;
-       short enable_spi1 = 0;
-
-       /* Choose SPI chip-selects */
-       for (i = 0; i < nr_devices; i++) {
-               if (devices[i].controller_data)
-                       cs_pin = (unsigned long) devices[i].controller_data;
-               else if (devices[i].bus_num == 0)
-                       cs_pin = spi0_standard_cs[devices[i].chip_select];
-               else
-                       cs_pin = spi1_standard_cs[devices[i].chip_select];
-
-               if (devices[i].bus_num == 0)
-                       enable_spi0 = 1;
-               else
-                       enable_spi1 = 1;
-
-               /* enable chip-select pin */
-               at91_set_gpio_output(cs_pin, 1);
-
-               /* pass chip-select pin to driver */
-               devices[i].controller_data = (void *) cs_pin;
-       }
-
-       spi_register_board_info(devices, nr_devices);
-
-       /* Configure SPI bus(es) */
-       if (enable_spi0) {
-               at91_set_B_periph(AT91_PIN_PA0, 0);     /* SPI0_MISO */
-               at91_set_B_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
-               at91_set_B_periph(AT91_PIN_PA2, 0);     /* SPI0_SPCK */
-
-               platform_device_register(&at91cap9_spi0_device);
-       }
-       if (enable_spi1) {
-               at91_set_A_periph(AT91_PIN_PB12, 0);    /* SPI1_MISO */
-               at91_set_A_periph(AT91_PIN_PB13, 0);    /* SPI1_MOSI */
-               at91_set_A_periph(AT91_PIN_PB14, 0);    /* SPI1_SPCK */
-
-               platform_device_register(&at91cap9_spi1_device);
-       }
-}
-#else
-void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  Timer/Counter block
- * -------------------------------------------------------------------- */
-
-#ifdef CONFIG_ATMEL_TCLIB
-
-static struct resource tcb_resources[] = {
-       [0] = {
-               .start  = AT91CAP9_BASE_TCB0,
-               .end    = AT91CAP9_BASE_TCB0 + SZ_16K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = AT91CAP9_ID_TCB,
-               .end    = AT91CAP9_ID_TCB,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static struct platform_device at91cap9_tcb_device = {
-       .name           = "atmel_tcb",
-       .id             = 0,
-       .resource       = tcb_resources,
-       .num_resources  = ARRAY_SIZE(tcb_resources),
-};
-
-static void __init at91_add_device_tc(void)
-{
-       platform_device_register(&at91cap9_tcb_device);
-}
-#else
-static void __init at91_add_device_tc(void) { }
-#endif
-
-
-/* --------------------------------------------------------------------
- *  RTT
- * -------------------------------------------------------------------- */
-
-static struct resource rtt_resources[] = {
-       {
-               .start  = AT91CAP9_BASE_RTT,
-               .end    = AT91CAP9_BASE_RTT + SZ_16 - 1,
-               .flags  = IORESOURCE_MEM,
-       }
-};
-
-static struct platform_device at91cap9_rtt_device = {
-       .name           = "at91_rtt",
-       .id             = 0,
-       .resource       = rtt_resources,
-       .num_resources  = ARRAY_SIZE(rtt_resources),
-};
-
-static void __init at91_add_device_rtt(void)
-{
-       platform_device_register(&at91cap9_rtt_device);
-}
-
-
-/* --------------------------------------------------------------------
- *  Watchdog
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
-static struct resource wdt_resources[] = {
-       {
-               .start  = AT91CAP9_BASE_WDT,
-               .end    = AT91CAP9_BASE_WDT + SZ_16 - 1,
-               .flags  = IORESOURCE_MEM,
-       }
-};
-
-static struct platform_device at91cap9_wdt_device = {
-       .name           = "at91_wdt",
-       .id             = -1,
-       .resource       = wdt_resources,
-       .num_resources  = ARRAY_SIZE(wdt_resources),
-};
-
-static void __init at91_add_device_watchdog(void)
-{
-       platform_device_register(&at91cap9_wdt_device);
-}
-#else
-static void __init at91_add_device_watchdog(void) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  PWM
- * --------------------------------------------------------------------*/
-
-#if defined(CONFIG_ATMEL_PWM)
-static u32 pwm_mask;
-
-static struct resource pwm_resources[] = {
-       [0] = {
-               .start  = AT91CAP9_BASE_PWMC,
-               .end    = AT91CAP9_BASE_PWMC + SZ_16K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = AT91CAP9_ID_PWMC,
-               .end    = AT91CAP9_ID_PWMC,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static struct platform_device at91cap9_pwm0_device = {
-       .name   = "atmel_pwm",
-       .id     = -1,
-       .dev    = {
-               .platform_data          = &pwm_mask,
-       },
-       .resource       = pwm_resources,
-       .num_resources  = ARRAY_SIZE(pwm_resources),
-};
-
-void __init at91_add_device_pwm(u32 mask)
-{
-       if (mask & (1 << AT91_PWM0))
-               at91_set_A_periph(AT91_PIN_PB19, 1);    /* enable PWM0 */
-
-       if (mask & (1 << AT91_PWM1))
-               at91_set_B_periph(AT91_PIN_PB8, 1);     /* enable PWM1 */
-
-       if (mask & (1 << AT91_PWM2))
-               at91_set_B_periph(AT91_PIN_PC29, 1);    /* enable PWM2 */
-
-       if (mask & (1 << AT91_PWM3))
-               at91_set_B_periph(AT91_PIN_PA11, 1);    /* enable PWM3 */
-
-       pwm_mask = mask;
-
-       platform_device_register(&at91cap9_pwm0_device);
-}
-#else
-void __init at91_add_device_pwm(u32 mask) {}
-#endif
-
-
-
-/* --------------------------------------------------------------------
- *  AC97
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
-static u64 ac97_dmamask = DMA_BIT_MASK(32);
-static struct ac97c_platform_data ac97_data;
-
-static struct resource ac97_resources[] = {
-       [0] = {
-               .start  = AT91CAP9_BASE_AC97C,
-               .end    = AT91CAP9_BASE_AC97C + SZ_16K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = AT91CAP9_ID_AC97C,
-               .end    = AT91CAP9_ID_AC97C,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static struct platform_device at91cap9_ac97_device = {
-       .name           = "atmel_ac97c",
-       .id             = 1,
-       .dev            = {
-                               .dma_mask               = &ac97_dmamask,
-                               .coherent_dma_mask      = DMA_BIT_MASK(32),
-                               .platform_data          = &ac97_data,
-       },
-       .resource       = ac97_resources,
-       .num_resources  = ARRAY_SIZE(ac97_resources),
-};
-
-void __init at91_add_device_ac97(struct ac97c_platform_data *data)
-{
-       if (!data)
-               return;
-
-       at91_set_A_periph(AT91_PIN_PA6, 0);     /* AC97FS */
-       at91_set_A_periph(AT91_PIN_PA7, 0);     /* AC97CK */
-       at91_set_A_periph(AT91_PIN_PA8, 0);     /* AC97TX */
-       at91_set_A_periph(AT91_PIN_PA9, 0);     /* AC97RX */
-
-       /* reset */
-       if (gpio_is_valid(data->reset_pin))
-               at91_set_gpio_output(data->reset_pin, 0);
-
-       ac97_data = *data;
-       platform_device_register(&at91cap9_ac97_device);
-}
-#else
-void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  LCD Controller
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
-static u64 lcdc_dmamask = DMA_BIT_MASK(32);
-static struct atmel_lcdfb_info lcdc_data;
-
-static struct resource lcdc_resources[] = {
-       [0] = {
-               .start  = AT91CAP9_LCDC_BASE,
-               .end    = AT91CAP9_LCDC_BASE + SZ_4K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = AT91CAP9_ID_LCDC,
-               .end    = AT91CAP9_ID_LCDC,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static struct platform_device at91_lcdc_device = {
-       .name           = "atmel_lcdfb",
-       .id             = 0,
-       .dev            = {
-                               .dma_mask               = &lcdc_dmamask,
-                               .coherent_dma_mask      = DMA_BIT_MASK(32),
-                               .platform_data          = &lcdc_data,
-       },
-       .resource       = lcdc_resources,
-       .num_resources  = ARRAY_SIZE(lcdc_resources),
-};
-
-void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
-{
-       if (!data)
-               return;
-
-       if (cpu_is_at91cap9_revB())
-               irq_set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH);
-
-       at91_set_A_periph(AT91_PIN_PC1, 0);     /* LCDHSYNC */
-       at91_set_A_periph(AT91_PIN_PC2, 0);     /* LCDDOTCK */
-       at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDDEN */
-       at91_set_B_periph(AT91_PIN_PB9, 0);     /* LCDCC */
-       at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDD2 */
-       at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDD3 */
-       at91_set_A_periph(AT91_PIN_PC8, 0);     /* LCDD4 */
-       at91_set_A_periph(AT91_PIN_PC9, 0);     /* LCDD5 */
-       at91_set_A_periph(AT91_PIN_PC10, 0);    /* LCDD6 */
-       at91_set_A_periph(AT91_PIN_PC11, 0);    /* LCDD7 */
-       at91_set_A_periph(AT91_PIN_PC14, 0);    /* LCDD10 */
-       at91_set_A_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
-       at91_set_A_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
-       at91_set_A_periph(AT91_PIN_PC17, 0);    /* LCDD13 */
-       at91_set_A_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
-       at91_set_A_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
-       at91_set_A_periph(AT91_PIN_PC22, 0);    /* LCDD18 */
-       at91_set_A_periph(AT91_PIN_PC23, 0);    /* LCDD19 */
-       at91_set_A_periph(AT91_PIN_PC24, 0);    /* LCDD20 */
-       at91_set_A_periph(AT91_PIN_PC25, 0);    /* LCDD21 */
-       at91_set_A_periph(AT91_PIN_PC26, 0);    /* LCDD22 */
-       at91_set_A_periph(AT91_PIN_PC27, 0);    /* LCDD23 */
-
-       lcdc_data = *data;
-       platform_device_register(&at91_lcdc_device);
-}
-#else
-void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  SSC -- Synchronous Serial Controller
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
-static u64 ssc0_dmamask = DMA_BIT_MASK(32);
-
-static struct resource ssc0_resources[] = {
-       [0] = {
-               .start  = AT91CAP9_BASE_SSC0,
-               .end    = AT91CAP9_BASE_SSC0 + SZ_16K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = AT91CAP9_ID_SSC0,
-               .end    = AT91CAP9_ID_SSC0,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static struct platform_device at91cap9_ssc0_device = {
-       .name   = "ssc",
-       .id     = 0,
-       .dev    = {
-               .dma_mask               = &ssc0_dmamask,
-               .coherent_dma_mask      = DMA_BIT_MASK(32),
-       },
-       .resource       = ssc0_resources,
-       .num_resources  = ARRAY_SIZE(ssc0_resources),
-};
-
-static inline void configure_ssc0_pins(unsigned pins)
-{
-       if (pins & ATMEL_SSC_TF)
-               at91_set_A_periph(AT91_PIN_PB0, 1);
-       if (pins & ATMEL_SSC_TK)
-               at91_set_A_periph(AT91_PIN_PB1, 1);
-       if (pins & ATMEL_SSC_TD)
-               at91_set_A_periph(AT91_PIN_PB2, 1);
-       if (pins & ATMEL_SSC_RD)
-               at91_set_A_periph(AT91_PIN_PB3, 1);
-       if (pins & ATMEL_SSC_RK)
-               at91_set_A_periph(AT91_PIN_PB4, 1);
-       if (pins & ATMEL_SSC_RF)
-               at91_set_A_periph(AT91_PIN_PB5, 1);
-}
-
-static u64 ssc1_dmamask = DMA_BIT_MASK(32);
-
-static struct resource ssc1_resources[] = {
-       [0] = {
-               .start  = AT91CAP9_BASE_SSC1,
-               .end    = AT91CAP9_BASE_SSC1 + SZ_16K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = AT91CAP9_ID_SSC1,
-               .end    = AT91CAP9_ID_SSC1,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static struct platform_device at91cap9_ssc1_device = {
-       .name   = "ssc",
-       .id     = 1,
-       .dev    = {
-               .dma_mask               = &ssc1_dmamask,
-               .coherent_dma_mask      = DMA_BIT_MASK(32),
-       },
-       .resource       = ssc1_resources,
-       .num_resources  = ARRAY_SIZE(ssc1_resources),
-};
-
-static inline void configure_ssc1_pins(unsigned pins)
-{
-       if (pins & ATMEL_SSC_TF)
-               at91_set_A_periph(AT91_PIN_PB6, 1);
-       if (pins & ATMEL_SSC_TK)
-               at91_set_A_periph(AT91_PIN_PB7, 1);
-       if (pins & ATMEL_SSC_TD)
-               at91_set_A_periph(AT91_PIN_PB8, 1);
-       if (pins & ATMEL_SSC_RD)
-               at91_set_A_periph(AT91_PIN_PB9, 1);
-       if (pins & ATMEL_SSC_RK)
-               at91_set_A_periph(AT91_PIN_PB10, 1);
-       if (pins & ATMEL_SSC_RF)
-               at91_set_A_periph(AT91_PIN_PB11, 1);
-}
-
-/*
- * SSC controllers are accessed through library code, instead of any
- * kind of all-singing/all-dancing driver.  For example one could be
- * used by a particular I2S audio codec's driver, while another one
- * on the same system might be used by a custom data capture driver.
- */
-void __init at91_add_device_ssc(unsigned id, unsigned pins)
-{
-       struct platform_device *pdev;
-
-       /*
-        * NOTE: caller is responsible for passing information matching
-        * "pins" to whatever will be using each particular controller.
-        */
-       switch (id) {
-       case AT91CAP9_ID_SSC0:
-               pdev = &at91cap9_ssc0_device;
-               configure_ssc0_pins(pins);
-               break;
-       case AT91CAP9_ID_SSC1:
-               pdev = &at91cap9_ssc1_device;
-               configure_ssc1_pins(pins);
-               break;
-       default:
-               return;
-       }
-
-       platform_device_register(pdev);
-}
-
-#else
-void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  UART
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_SERIAL_ATMEL)
-static struct resource dbgu_resources[] = {
-       [0] = {
-               .start  = AT91CAP9_BASE_DBGU,
-               .end    = AT91CAP9_BASE_DBGU + SZ_512 - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = AT91_ID_SYS,
-               .end    = AT91_ID_SYS,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static struct atmel_uart_data dbgu_data = {
-       .use_dma_tx     = 0,
-       .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
-};
-
-static u64 dbgu_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device at91cap9_dbgu_device = {
-       .name           = "atmel_usart",
-       .id             = 0,
-       .dev            = {
-                               .dma_mask               = &dbgu_dmamask,
-                               .coherent_dma_mask      = DMA_BIT_MASK(32),
-                               .platform_data          = &dbgu_data,
-       },
-       .resource       = dbgu_resources,
-       .num_resources  = ARRAY_SIZE(dbgu_resources),
-};
-
-static inline void configure_dbgu_pins(void)
-{
-       at91_set_A_periph(AT91_PIN_PC30, 0);            /* DRXD */
-       at91_set_A_periph(AT91_PIN_PC31, 1);            /* DTXD */
-}
-
-static struct resource uart0_resources[] = {
-       [0] = {
-               .start  = AT91CAP9_BASE_US0,
-               .end    = AT91CAP9_BASE_US0 + SZ_16K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = AT91CAP9_ID_US0,
-               .end    = AT91CAP9_ID_US0,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static struct atmel_uart_data uart0_data = {
-       .use_dma_tx     = 1,
-       .use_dma_rx     = 1,
-};
-
-static u64 uart0_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device at91cap9_uart0_device = {
-       .name           = "atmel_usart",
-       .id             = 1,
-       .dev            = {
-                               .dma_mask               = &uart0_dmamask,
-                               .coherent_dma_mask      = DMA_BIT_MASK(32),
-                               .platform_data          = &uart0_data,
-       },
-       .resource       = uart0_resources,
-       .num_resources  = ARRAY_SIZE(uart0_resources),
-};
-
-static inline void configure_usart0_pins(unsigned pins)
-{
-       at91_set_A_periph(AT91_PIN_PA22, 1);            /* TXD0 */
-       at91_set_A_periph(AT91_PIN_PA23, 0);            /* RXD0 */
-
-       if (pins & ATMEL_UART_RTS)
-               at91_set_A_periph(AT91_PIN_PA24, 0);    /* RTS0 */
-       if (pins & ATMEL_UART_CTS)
-               at91_set_A_periph(AT91_PIN_PA25, 0);    /* CTS0 */
-}
-
-static struct resource uart1_resources[] = {
-       [0] = {
-               .start  = AT91CAP9_BASE_US1,
-               .end    = AT91CAP9_BASE_US1 + SZ_16K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = AT91CAP9_ID_US1,
-               .end    = AT91CAP9_ID_US1,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static struct atmel_uart_data uart1_data = {
-       .use_dma_tx     = 1,
-       .use_dma_rx     = 1,
-};
-
-static u64 uart1_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device at91cap9_uart1_device = {
-       .name           = "atmel_usart",
-       .id             = 2,
-       .dev            = {
-                               .dma_mask               = &uart1_dmamask,
-                               .coherent_dma_mask      = DMA_BIT_MASK(32),
-                               .platform_data          = &uart1_data,
-       },
-       .resource       = uart1_resources,
-       .num_resources  = ARRAY_SIZE(uart1_resources),
-};
-
-static inline void configure_usart1_pins(unsigned pins)
-{
-       at91_set_A_periph(AT91_PIN_PD0, 1);             /* TXD1 */
-       at91_set_A_periph(AT91_PIN_PD1, 0);             /* RXD1 */
-
-       if (pins & ATMEL_UART_RTS)
-               at91_set_B_periph(AT91_PIN_PD7, 0);     /* RTS1 */
-       if (pins & ATMEL_UART_CTS)
-               at91_set_B_periph(AT91_PIN_PD8, 0);     /* CTS1 */
-}
-
-static struct resource uart2_resources[] = {
-       [0] = {
-               .start  = AT91CAP9_BASE_US2,
-               .end    = AT91CAP9_BASE_US2 + SZ_16K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = AT91CAP9_ID_US2,
-               .end    = AT91CAP9_ID_US2,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static struct atmel_uart_data uart2_data = {
-       .use_dma_tx     = 1,
-       .use_dma_rx     = 1,
-};
-
-static u64 uart2_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device at91cap9_uart2_device = {
-       .name           = "atmel_usart",
-       .id             = 3,
-       .dev            = {
-                               .dma_mask               = &uart2_dmamask,
-                               .coherent_dma_mask      = DMA_BIT_MASK(32),
-                               .platform_data          = &uart2_data,
-       },
-       .resource       = uart2_resources,
-       .num_resources  = ARRAY_SIZE(uart2_resources),
-};
-
-static inline void configure_usart2_pins(unsigned pins)
-{
-       at91_set_A_periph(AT91_PIN_PD2, 1);             /* TXD2 */
-       at91_set_A_periph(AT91_PIN_PD3, 0);             /* RXD2 */
-
-       if (pins & ATMEL_UART_RTS)
-               at91_set_B_periph(AT91_PIN_PD5, 0);     /* RTS2 */
-       if (pins & ATMEL_UART_CTS)
-               at91_set_B_periph(AT91_PIN_PD6, 0);     /* CTS2 */
-}
-
-static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];  /* the UARTs to use */
-struct platform_device *atmel_default_console_device;  /* the serial console device */
-
-void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
-{
-       struct platform_device *pdev;
-       struct atmel_uart_data *pdata;
-
-       switch (id) {
-               case 0:         /* DBGU */
-                       pdev = &at91cap9_dbgu_device;
-                       configure_dbgu_pins();
-                       break;
-               case AT91CAP9_ID_US0:
-                       pdev = &at91cap9_uart0_device;
-                       configure_usart0_pins(pins);
-                       break;
-               case AT91CAP9_ID_US1:
-                       pdev = &at91cap9_uart1_device;
-                       configure_usart1_pins(pins);
-                       break;
-               case AT91CAP9_ID_US2:
-                       pdev = &at91cap9_uart2_device;
-                       configure_usart2_pins(pins);
-                       break;
-               default:
-                       return;
-       }
-       pdata = pdev->dev.platform_data;
-       pdata->num = portnr;            /* update to mapped ID */
-
-       if (portnr < ATMEL_MAX_UART)
-               at91_uarts[portnr] = pdev;
-}
-
-void __init at91_set_serial_console(unsigned portnr)
-{
-       if (portnr < ATMEL_MAX_UART) {
-               atmel_default_console_device = at91_uarts[portnr];
-               at91cap9_set_console_clock(at91_uarts[portnr]->id);
-       }
-}
-
-void __init at91_add_device_serial(void)
-{
-       int i;
-
-       for (i = 0; i < ATMEL_MAX_UART; i++) {
-               if (at91_uarts[i])
-                       platform_device_register(at91_uarts[i]);
-       }
-
-       if (!atmel_default_console_device)
-               printk(KERN_INFO "AT91: No default serial console defined.\n");
-}
-#else
-void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
-void __init at91_set_serial_console(unsigned portnr) {}
-void __init at91_add_device_serial(void) {}
-#endif
-
-
-/* -------------------------------------------------------------------- */
-/*
- * These devices are always present and don't need any board-specific
- * setup.
- */
-static int __init at91_add_standard_devices(void)
-{
-       at91_add_device_rtt();
-       at91_add_device_watchdog();
-       at91_add_device_tc();
-       return 0;
-}
-
-arch_initcall(at91_add_standard_devices);
index dd6e2de134204a5ccf5c28df3bfe41d9b8170314..0df1045311e420e2e96670e62f182f44d39f5481 100644 (file)
@@ -295,7 +295,7 @@ static void at91rm9200_idle(void)
         * Disable the processor clock.  The processor will be automatically
         * re-enabled by an interrupt or by a reset.
         */
-       at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
+       at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
 }
 
 static void at91rm9200_restart(char mode, const char *cmd)
@@ -303,8 +303,8 @@ static void at91rm9200_restart(char mode, const char *cmd)
        /*
         * Perform a hardware reset with the use of the Watchdog timer.
         */
-       at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
-       at91_sys_write(AT91_ST_CR, AT91_ST_WDRST);
+       at91_st_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
+       at91_st_write(AT91_ST_CR, AT91_ST_WDRST);
 }
 
 /* --------------------------------------------------------------------
@@ -319,6 +319,8 @@ static void __init at91rm9200_map_io(void)
 
 static void __init at91rm9200_ioremap_registers(void)
 {
+       at91rm9200_ioremap_st(AT91RM9200_BASE_ST);
+       at91_ioremap_ramc(0, AT91RM9200_BASE_MC, 256);
 }
 
 static void __init at91rm9200_initialize(void)
index 18bacec2b094c202bc9dd60be5b69be0c56a683f..640520c04c46cb80f7988bdd29ff02e3df20f6b6 100644 (file)
@@ -21,6 +21,7 @@
 #include <mach/board.h>
 #include <mach/at91rm9200.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 
 #include "generic.h"
 
@@ -241,15 +242,15 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
        data->chipselect = 4;           /* can only use EBI ChipSelect 4 */
 
        /* CF takes over CS4, CS5, CS6 */
-       csa = at91_sys_read(AT91_EBI_CSA);
-       at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
+       csa = at91_ramc_read(0, AT91_EBI_CSA);
+       at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
 
        /*
         * Static memory controller timing adjustments.
         * REVISIT:  these timings are in terms of MCK cycles, so
         * when MCK changes (cpufreq etc) so must these values...
         */
-       at91_sys_write(AT91_SMC_CSR(4),
+       at91_ramc_write(0, AT91_SMC_CSR(4),
                                  AT91_SMC_ACSS_STD
                                | AT91_SMC_DBW_16
                                | AT91_SMC_BAT
@@ -407,11 +408,11 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
                return;
 
        /* enable the address range of CS3 */
-       csa = at91_sys_read(AT91_EBI_CSA);
-       at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
+       csa = at91_ramc_read(0, AT91_EBI_CSA);
+       at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
 
        /* set the bus interface characteristics */
-       at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
+       at91_ramc_write(0, AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
                | AT91_SMC_NWS_(5)
                | AT91_SMC_TDF_(1)
                | AT91_SMC_RWSETUP_(0)  /* tDS Data Set up Time 30 - ns */
@@ -1114,7 +1115,6 @@ static inline void configure_usart3_pins(unsigned pins)
 }
 
 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];  /* the UARTs to use */
-struct platform_device *atmel_default_console_device;  /* the serial console device */
 
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
index a028cdf8f9749d8ad4da1aef23386da5850330c4..dd7f782b0b91731202c3d8e10f02597b7d89518c 100644 (file)
@@ -43,9 +43,9 @@ static inline unsigned long read_CRTR(void)
 {
        unsigned long x1, x2;
 
-       x1 = at91_sys_read(AT91_ST_CRTR);
+       x1 = at91_st_read(AT91_ST_CRTR);
        do {
-               x2 = at91_sys_read(AT91_ST_CRTR);
+               x2 = at91_st_read(AT91_ST_CRTR);
                if (x1 == x2)
                        break;
                x1 = x2;
@@ -58,7 +58,7 @@ static inline unsigned long read_CRTR(void)
  */
 static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
 {
-       u32     sr = at91_sys_read(AT91_ST_SR) & irqmask;
+       u32     sr = at91_st_read(AT91_ST_SR) & irqmask;
 
        /*
         * irqs should be disabled here, but as the irq is shared they are only
@@ -110,22 +110,22 @@ static void
 clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
 {
        /* Disable and flush pending timer interrupts */
-       at91_sys_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
-       (void) at91_sys_read(AT91_ST_SR);
+       at91_st_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
+       at91_st_read(AT91_ST_SR);
 
        last_crtr = read_CRTR();
        switch (mode) {
        case CLOCK_EVT_MODE_PERIODIC:
                /* PIT for periodic irqs; fixed rate of 1/HZ */
                irqmask = AT91_ST_PITS;
-               at91_sys_write(AT91_ST_PIMR, RM9200_TIMER_LATCH);
+               at91_st_write(AT91_ST_PIMR, RM9200_TIMER_LATCH);
                break;
        case CLOCK_EVT_MODE_ONESHOT:
                /* ALM for oneshot irqs, set by next_event()
                 * before 32 seconds have passed
                 */
                irqmask = AT91_ST_ALMS;
-               at91_sys_write(AT91_ST_RTAR, last_crtr);
+               at91_st_write(AT91_ST_RTAR, last_crtr);
                break;
        case CLOCK_EVT_MODE_SHUTDOWN:
        case CLOCK_EVT_MODE_UNUSED:
@@ -133,7 +133,7 @@ clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
                irqmask = 0;
                break;
        }
-       at91_sys_write(AT91_ST_IER, irqmask);
+       at91_st_write(AT91_ST_IER, irqmask);
 }
 
 static int
@@ -156,12 +156,12 @@ clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
        alm = read_CRTR();
 
        /* Cancel any pending alarm; flush any pending IRQ */
-       at91_sys_write(AT91_ST_RTAR, alm);
-       (void) at91_sys_read(AT91_ST_SR);
+       at91_st_write(AT91_ST_RTAR, alm);
+       at91_st_read(AT91_ST_SR);
 
        /* Schedule alarm by writing RTAR. */
        alm += delta;
-       at91_sys_write(AT91_ST_RTAR, alm);
+       at91_st_write(AT91_ST_RTAR, alm);
 
        return status;
 }
@@ -175,15 +175,24 @@ static struct clock_event_device clkevt = {
        .set_mode       = clkevt32k_mode,
 };
 
+void __iomem *at91_st_base;
+
+void __init at91rm9200_ioremap_st(u32 addr)
+{
+       at91_st_base = ioremap(addr, 256);
+       if (!at91_st_base)
+               panic("Impossible to ioremap ST\n");
+}
+
 /*
  * ST (system timer) module supports both clockevents and clocksource.
  */
 void __init at91rm9200_timer_init(void)
 {
        /* Disable all timer interrupts, and clear any pending ones */
-       at91_sys_write(AT91_ST_IDR,
+       at91_st_write(AT91_ST_IDR,
                AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
-       (void) at91_sys_read(AT91_ST_SR);
+       at91_st_read(AT91_ST_SR);
 
        /* Make IRQs happen for the system timer */
        setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq);
@@ -192,7 +201,7 @@ void __init at91rm9200_timer_init(void)
         * directly for the clocksource and all clockevents, after adjusting
         * its prescaler from the 1 Hz default.
         */
-       at91_sys_write(AT91_ST_RTMR, 1);
+       at91_st_write(AT91_ST_RTMR, 1);
 
        /* Setup timer clockevent, with minimum of two ticks (important!!) */
        clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift);
index 9ac8c6fe3363b6af723c8366108d6d863bcb9415..4ade265be805f97e6cca0c40cc8e509bbdcdeabc 100644 (file)
@@ -310,34 +310,27 @@ static void __init at91sam9xe_map_io(void)
 
 static void __init at91sam9260_map_io(void)
 {
-       if (cpu_is_at91sam9xe()) {
+       if (cpu_is_at91sam9xe())
                at91sam9xe_map_io();
-       } else if (cpu_is_at91sam9g20()) {
-               at91_init_sram(0, AT91SAM9G20_SRAM0_BASE, AT91SAM9G20_SRAM0_SIZE);
-               at91_init_sram(1, AT91SAM9G20_SRAM1_BASE, AT91SAM9G20_SRAM1_SIZE);
-       } else {
-               at91_init_sram(0, AT91SAM9260_SRAM0_BASE, AT91SAM9260_SRAM0_SIZE);
-               at91_init_sram(1, AT91SAM9260_SRAM1_BASE, AT91SAM9260_SRAM1_SIZE);
-       }
+       else if (cpu_is_at91sam9g20())
+               at91_init_sram(0, AT91SAM9G20_SRAM_BASE, AT91SAM9G20_SRAM_SIZE);
+       else
+               at91_init_sram(0, AT91SAM9260_SRAM_BASE, AT91SAM9260_SRAM_SIZE);
 }
 
 static void __init at91sam9260_ioremap_registers(void)
 {
        at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
        at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
+       at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC, 512);
        at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
        at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
-}
-
-static void at91sam9260_idle(void)
-{
-       at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
-       cpu_do_idle();
+       at91_ioremap_matrix(AT91SAM9260_BASE_MATRIX);
 }
 
 static void __init at91sam9260_initialize(void)
 {
-       arm_pm_idle = at91sam9260_idle;
+       arm_pm_idle = at91sam9_idle;
        arm_pm_restart = at91sam9_alt_restart;
        at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
                        | (1 << AT91SAM9260_ID_IRQ2);
index 642ccb6d26b256f284388080f71b68e5494e8070..df487ce83c5efc6537d8f218e5ba59f971ec8420 100644 (file)
@@ -21,6 +21,7 @@
 #include <mach/cpu.h>
 #include <mach/at91sam9260.h>
 #include <mach/at91sam9260_matrix.h>
+#include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
 
 #include "generic.h"
@@ -422,8 +423,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
        if (!data)
                return;
 
-       csa = at91_sys_read(AT91_MATRIX_EBICSA);
-       at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+       csa = at91_matrix_read(AT91_MATRIX_EBICSA);
+       at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
 
        /* enable pin */
        if (gpio_is_valid(data->enable_pin))
@@ -717,18 +718,42 @@ static struct resource rtt_resources[] = {
                .start  = AT91SAM9260_BASE_RTT,
                .end    = AT91SAM9260_BASE_RTT + SZ_16 - 1,
                .flags  = IORESOURCE_MEM,
-       }
+       }, {
+               .flags  = IORESOURCE_MEM,
+       },
 };
 
 static struct platform_device at91sam9260_rtt_device = {
        .name           = "at91_rtt",
        .id             = 0,
        .resource       = rtt_resources,
-       .num_resources  = ARRAY_SIZE(rtt_resources),
 };
 
+
+#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
+static void __init at91_add_device_rtt_rtc(void)
+{
+       at91sam9260_rtt_device.name = "rtc-at91sam9";
+       /*
+        * The second resource is needed:
+        * GPBR will serve as the storage for RTC time offset
+        */
+       at91sam9260_rtt_device.num_resources = 2;
+       rtt_resources[1].start = AT91SAM9260_BASE_GPBR +
+                                4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
+       rtt_resources[1].end = rtt_resources[1].start + 3;
+}
+#else
+static void __init at91_add_device_rtt_rtc(void)
+{
+       /* Only one resource is needed: RTT not used as RTC */
+       at91sam9260_rtt_device.num_resources = 1;
+}
+#endif
+
 static void __init at91_add_device_rtt(void)
 {
+       at91_add_device_rtt_rtc();
        platform_device_register(&at91sam9260_rtt_device);
 }
 
@@ -1139,7 +1164,6 @@ static inline void configure_usart5_pins(void)
 }
 
 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];  /* the UARTs to use */
-struct platform_device *atmel_default_console_device;  /* the serial console device */
 
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
@@ -1265,7 +1289,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
        if (!data)
                return;
 
-       csa = at91_sys_read(AT91_MATRIX_EBICSA);
+       csa = at91_matrix_read(AT91_MATRIX_EBICSA);
 
        switch (data->chipselect) {
        case 4:
@@ -1288,7 +1312,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
                return;
        }
 
-       at91_sys_write(AT91_MATRIX_EBICSA, csa);
+       at91_matrix_write(AT91_MATRIX_EBICSA, csa);
 
        if (gpio_is_valid(data->rst_pin)) {
                at91_set_multi_drive(data->rst_pin, 0);
index ab76868f01f5ee8e48b80359d3064e531ae3c86d..684c5dfd92ac5a00eaf736ed5d5949769f4bdbd4 100644 (file)
@@ -283,19 +283,15 @@ static void __init at91sam9261_ioremap_registers(void)
 {
        at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
        at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
+       at91_ioremap_ramc(0, AT91SAM9261_BASE_SDRAMC, 512);
        at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
        at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
-}
-
-static void at91sam9261_idle(void)
-{
-       at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
-       cpu_do_idle();
+       at91_ioremap_matrix(AT91SAM9261_BASE_MATRIX);
 }
 
 static void __init at91sam9261_initialize(void)
 {
-       arm_pm_idle = at91sam9261_idle;
+       arm_pm_idle = at91sam9_idle;
        arm_pm_restart = at91sam9_alt_restart;
        at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
                        | (1 << AT91SAM9261_ID_IRQ2);
index fc59cbdb0e3cfcc777e3fe231bf8c525c2457198..3bd10ce4854e8bdc1890c1f4de723c9ec7b9efaa 100644 (file)
@@ -24,6 +24,7 @@
 #include <mach/board.h>
 #include <mach/at91sam9261.h>
 #include <mach/at91sam9261_matrix.h>
+#include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
 
 #include "generic.h"
@@ -236,8 +237,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
        if (!data)
                return;
 
-       csa = at91_sys_read(AT91_MATRIX_EBICSA);
-       at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+       csa = at91_matrix_read(AT91_MATRIX_EBICSA);
+       at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
 
        /* enable pin */
        if (gpio_is_valid(data->enable_pin))
@@ -603,6 +604,8 @@ static struct resource rtt_resources[] = {
                .start  = AT91SAM9261_BASE_RTT,
                .end    = AT91SAM9261_BASE_RTT + SZ_16 - 1,
                .flags  = IORESOURCE_MEM,
+       }, {
+               .flags  = IORESOURCE_MEM,
        }
 };
 
@@ -610,11 +613,32 @@ static struct platform_device at91sam9261_rtt_device = {
        .name           = "at91_rtt",
        .id             = 0,
        .resource       = rtt_resources,
-       .num_resources  = ARRAY_SIZE(rtt_resources),
 };
 
+#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
+static void __init at91_add_device_rtt_rtc(void)
+{
+       at91sam9261_rtt_device.name = "rtc-at91sam9";
+       /*
+        * The second resource is needed:
+        * GPBR will serve as the storage for RTC time offset
+        */
+       at91sam9261_rtt_device.num_resources = 2;
+       rtt_resources[1].start = AT91SAM9261_BASE_GPBR +
+                                4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
+       rtt_resources[1].end = rtt_resources[1].start + 3;
+}
+#else
+static void __init at91_add_device_rtt_rtc(void)
+{
+       /* Only one resource is needed: RTT not used as RTC */
+       at91sam9261_rtt_device.num_resources = 1;
+}
+#endif
+
 static void __init at91_add_device_rtt(void)
 {
+       at91_add_device_rtt_rtc();
        platform_device_register(&at91sam9261_rtt_device);
 }
 
@@ -991,7 +1015,6 @@ static inline void configure_usart2_pins(unsigned pins)
 }
 
 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];  /* the UARTs to use */
-struct platform_device *atmel_default_console_device;  /* the serial console device */
 
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
index 247ab633abccc72918d0e23be60c7e937deb5b61..0b4fa5a7f685907d03aa4efc89a758e0e26d4230 100644 (file)
@@ -303,20 +303,17 @@ static void __init at91sam9263_ioremap_registers(void)
 {
        at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
        at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
+       at91_ioremap_ramc(0, AT91SAM9263_BASE_SDRAMC0, 512);
+       at91_ioremap_ramc(1, AT91SAM9263_BASE_SDRAMC1, 512);
        at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
        at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
        at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
-}
-
-static void at91sam9263_idle(void)
-{
-       at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
-       cpu_do_idle();
+       at91_ioremap_matrix(AT91SAM9263_BASE_MATRIX);
 }
 
 static void __init at91sam9263_initialize(void)
 {
-       arm_pm_idle = at91sam9263_idle;
+       arm_pm_idle = at91sam9_idle;
        arm_pm_restart = at91sam9_alt_restart;
        at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
 
index 7b46b2787022e85729e4d39ade77d667c5110e66..7792de5b83d475140564a5bab2b52beee17266db 100644 (file)
@@ -23,6 +23,7 @@
 #include <mach/board.h>
 #include <mach/at91sam9263.h>
 #include <mach/at91sam9263_matrix.h>
+#include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
 
 #include "generic.h"
@@ -409,7 +410,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
         * we assume SMC timings are configured by board code,
         * except True IDE where timings are controlled by driver
         */
-       ebi0_csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
+       ebi0_csa = at91_matrix_read(AT91_MATRIX_EBI0CSA);
        switch (data->chipselect) {
        case 4:
                at91_set_A_periph(AT91_PIN_PD6, 0);  /* EBI0_NCS4/CFCS0 */
@@ -428,7 +429,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
                       data->chipselect);
                return;
        }
-       at91_sys_write(AT91_MATRIX_EBI0CSA, ebi0_csa);
+       at91_matrix_write(AT91_MATRIX_EBI0CSA, ebi0_csa);
 
        if (gpio_is_valid(data->det_pin)) {
                at91_set_gpio_input(data->det_pin, 1);
@@ -496,8 +497,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
        if (!data)
                return;
 
-       csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
-       at91_sys_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
+       csa = at91_matrix_read(AT91_MATRIX_EBI0CSA);
+       at91_matrix_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
 
        /* enable pin */
        if (gpio_is_valid(data->enable_pin))
@@ -891,7 +892,8 @@ static struct platform_device at91sam9263_isi_device = {
        .num_resources  = ARRAY_SIZE(isi_resources),
 };
 
-void __init at91_add_device_isi(void)
+void __init at91_add_device_isi(struct isi_platform_data *data,
+               bool use_pck_as_mck)
 {
        at91_set_A_periph(AT91_PIN_PE0, 0);     /* ISI_D0 */
        at91_set_A_periph(AT91_PIN_PE1, 0);     /* ISI_D1 */
@@ -904,14 +906,20 @@ void __init at91_add_device_isi(void)
        at91_set_A_periph(AT91_PIN_PE8, 0);     /* ISI_PCK */
        at91_set_A_periph(AT91_PIN_PE9, 0);     /* ISI_HSYNC */
        at91_set_A_periph(AT91_PIN_PE10, 0);    /* ISI_VSYNC */
-       at91_set_B_periph(AT91_PIN_PE11, 0);    /* ISI_MCK (PCK3) */
        at91_set_B_periph(AT91_PIN_PE12, 0);    /* ISI_PD8 */
        at91_set_B_periph(AT91_PIN_PE13, 0);    /* ISI_PD9 */
        at91_set_B_periph(AT91_PIN_PE14, 0);    /* ISI_PD10 */
        at91_set_B_periph(AT91_PIN_PE15, 0);    /* ISI_PD11 */
+
+       if (use_pck_as_mck) {
+               at91_set_B_periph(AT91_PIN_PE11, 0);    /* ISI_MCK (PCK3) */
+
+               /* TODO: register the PCK for ISI_MCK and set its parent */
+       }
 }
 #else
-void __init at91_add_device_isi(void) {}
+void __init at91_add_device_isi(struct isi_platform_data *data,
+               bool use_pck_as_mck) {}
 #endif
 
 
@@ -959,6 +967,8 @@ static struct resource rtt0_resources[] = {
                .start  = AT91SAM9263_BASE_RTT0,
                .end    = AT91SAM9263_BASE_RTT0 + SZ_16 - 1,
                .flags  = IORESOURCE_MEM,
+       }, {
+               .flags  = IORESOURCE_MEM,
        }
 };
 
@@ -966,7 +976,6 @@ static struct platform_device at91sam9263_rtt0_device = {
        .name           = "at91_rtt",
        .id             = 0,
        .resource       = rtt0_resources,
-       .num_resources  = ARRAY_SIZE(rtt0_resources),
 };
 
 static struct resource rtt1_resources[] = {
@@ -974,6 +983,8 @@ static struct resource rtt1_resources[] = {
                .start  = AT91SAM9263_BASE_RTT1,
                .end    = AT91SAM9263_BASE_RTT1 + SZ_16 - 1,
                .flags  = IORESOURCE_MEM,
+       }, {
+               .flags  = IORESOURCE_MEM,
        }
 };
 
@@ -981,11 +992,53 @@ static struct platform_device at91sam9263_rtt1_device = {
        .name           = "at91_rtt",
        .id             = 1,
        .resource       = rtt1_resources,
-       .num_resources  = ARRAY_SIZE(rtt1_resources),
 };
 
+#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
+static void __init at91_add_device_rtt_rtc(void)
+{
+       struct platform_device *pdev;
+       struct resource *r;
+
+       switch (CONFIG_RTC_DRV_AT91SAM9_RTT) {
+       case 0:
+               /*
+                * The second resource is needed only for the chosen RTT:
+                * GPBR will serve as the storage for RTC time offset
+                */
+               at91sam9263_rtt0_device.num_resources = 2;
+               at91sam9263_rtt1_device.num_resources = 1;
+               pdev = &at91sam9263_rtt0_device;
+               r = rtt0_resources;
+               break;
+       case 1:
+               at91sam9263_rtt0_device.num_resources = 1;
+               at91sam9263_rtt1_device.num_resources = 2;
+               pdev = &at91sam9263_rtt1_device;
+               r = rtt1_resources;
+               break;
+       default:
+               pr_err("at91sam9263: only supports 2 RTT (%d)\n",
+                      CONFIG_RTC_DRV_AT91SAM9_RTT);
+               return;
+       }
+
+       pdev->name = "rtc-at91sam9";
+       r[1].start = AT91SAM9263_BASE_GPBR + 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
+       r[1].end = r[1].start + 3;
+}
+#else
+static void __init at91_add_device_rtt_rtc(void)
+{
+       /* Only one resource is needed: RTT not used as RTC */
+       at91sam9263_rtt0_device.num_resources = 1;
+       at91sam9263_rtt1_device.num_resources = 1;
+}
+#endif
+
 static void __init at91_add_device_rtt(void)
 {
+       at91_add_device_rtt_rtc();
        platform_device_register(&at91sam9263_rtt0_device);
        platform_device_register(&at91sam9263_rtt1_device);
 }
@@ -1371,7 +1424,6 @@ static inline void configure_usart2_pins(unsigned pins)
 }
 
 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];  /* the UARTs to use */
-struct platform_device *atmel_default_console_device;  /* the serial console device */
 
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
index 518e42377171c8fb25e5888c8863f7b363721a99..7af2e108b8a057d65deb5b49a725b3881e9b00cd 100644 (file)
 
 #include <linux/linkage.h>
 #include <mach/hardware.h>
-#include <mach/at91sam9_sdramc.h>
+#include <mach/at91_ramc.h>
 #include <mach/at91_rstc.h>
 
                        .arm
 
                        .globl  at91sam9_alt_restart
 
-at91sam9_alt_restart:  ldr     r0, .at91_va_base_sdramc        @ preload constants
-                       ldr     r1, =at91_rstc_base
-                       ldr     r1, [r1]
+at91sam9_alt_restart:  ldr     r0, =at91_ramc_base             @ preload constants
+                       ldr     r0, [r0]
+                       ldr     r4, =at91_rstc_base
+                       ldr     r1, [r4]
 
                        mov     r2, #1
                        mov     r3, #AT91_SDRAMC_LPCB_POWER_DOWN
@@ -37,6 +38,3 @@ at91sam9_alt_restart: ldr     r0, .at91_va_base_sdramc        @ preload constants
                        str     r4, [r1, #AT91_RSTC_CR]         @ reset processor
 
                        b       .
-
-.at91_va_base_sdramc:
-       .word AT91_VA_BASE_SYS + AT91_SDRAMC0
index 5b12192e52ecc59e8fde425146f8811469149179..a41622ea61b848676d59ae2f388111a648c0d9d6 100644 (file)
@@ -317,12 +317,6 @@ static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
        }
 };
 
-static void at91sam9g45_idle(void)
-{
-       at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
-       cpu_do_idle();
-}
-
 /* --------------------------------------------------------------------
  *  AT91SAM9G45 processor initialization
  * -------------------------------------------------------------------- */
@@ -337,13 +331,16 @@ static void __init at91sam9g45_ioremap_registers(void)
 {
        at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
        at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC);
+       at91_ioremap_ramc(0, AT91SAM9G45_BASE_DDRSDRC1, 512);
+       at91_ioremap_ramc(1, AT91SAM9G45_BASE_DDRSDRC0, 512);
        at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
        at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
+       at91_ioremap_matrix(AT91SAM9G45_BASE_MATRIX);
 }
 
 static void __init at91sam9g45_initialize(void)
 {
-       arm_pm_idle = at91sam9g45_idle;
+       arm_pm_idle = at91sam9_idle;
        arm_pm_restart = at91sam9g45_restart;
        at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
 
index b7582dd10dc3bd86c577a59b5ef3c1be3269dd23..410829532aabdb99722f0ad5155affa6d3020703 100644 (file)
@@ -14,6 +14,7 @@
 
 #include <linux/dma-mapping.h>
 #include <linux/gpio.h>
+#include <linux/clk.h>
 #include <linux/platform_device.h>
 #include <linux/i2c-gpio.h>
 #include <linux/atmel-mci.h>
 #include <mach/board.h>
 #include <mach/at91sam9g45.h>
 #include <mach/at91sam9g45_matrix.h>
+#include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at_hdmac.h>
 #include <mach/atmel-mci.h>
 
+#include <media/atmel-isi.h>
+
 #include "generic.h"
+#include "clock.h"
 
 
 /* --------------------------------------------------------------------
 #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
 static u64 hdmac_dmamask = DMA_BIT_MASK(32);
 
-static struct at_dma_platform_data atdma_pdata = {
-       .nr_channels    = 8,
-};
-
 static struct resource hdmac_resources[] = {
        [0] = {
                .start  = AT91SAM9G45_BASE_DMA,
@@ -56,12 +57,11 @@ static struct resource hdmac_resources[] = {
 };
 
 static struct platform_device at_hdmac_device = {
-       .name           = "at_hdmac",
+       .name           = "at91sam9g45_dma",
        .id             = -1,
        .dev            = {
                                .dma_mask               = &hdmac_dmamask,
                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                               .platform_data          = &atdma_pdata,
        },
        .resource       = hdmac_resources,
        .num_resources  = ARRAY_SIZE(hdmac_resources),
@@ -69,9 +69,15 @@ static struct platform_device at_hdmac_device = {
 
 void __init at91_add_device_hdmac(void)
 {
-       dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask);
-       dma_cap_set(DMA_SLAVE, atdma_pdata.cap_mask);
-       platform_device_register(&at_hdmac_device);
+#if defined(CONFIG_OF)
+       struct device_node *of_node =
+               of_find_node_by_name(NULL, "dma-controller");
+
+       if (of_node)
+               of_node_put(of_node);
+       else
+#endif
+               platform_device_register(&at_hdmac_device);
 }
 #else
 void __init at91_add_device_hdmac(void) {}
@@ -552,8 +558,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
        if (!data)
                return;
 
-       csa = at91_sys_read(AT91_MATRIX_EBICSA);
-       at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
+       csa = at91_matrix_read(AT91_MATRIX_EBICSA);
+       at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
 
        /* enable pin */
        if (gpio_is_valid(data->enable_pin))
@@ -869,6 +875,96 @@ void __init at91_add_device_ac97(struct ac97c_platform_data *data)
 void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
 #endif
 
+/* --------------------------------------------------------------------
+ *  Image Sensor Interface
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_VIDEO_ATMEL_ISI) || defined(CONFIG_VIDEO_ATMEL_ISI_MODULE)
+static u64 isi_dmamask = DMA_BIT_MASK(32);
+static struct isi_platform_data isi_data;
+
+struct resource isi_resources[] = {
+       [0] = {
+               .start  = AT91SAM9G45_BASE_ISI,
+               .end    = AT91SAM9G45_BASE_ISI + SZ_16K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AT91SAM9G45_ID_ISI,
+               .end    = AT91SAM9G45_ID_ISI,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device at91sam9g45_isi_device = {
+       .name           = "atmel_isi",
+       .id             = 0,
+       .dev            = {
+                       .dma_mask               = &isi_dmamask,
+                       .coherent_dma_mask      = DMA_BIT_MASK(32),
+                       .platform_data          = &isi_data,
+       },
+       .resource       = isi_resources,
+       .num_resources  = ARRAY_SIZE(isi_resources),
+};
+
+static struct clk_lookup isi_mck_lookups[] = {
+       CLKDEV_CON_DEV_ID("isi_mck", "atmel_isi.0", NULL),
+};
+
+void __init at91_add_device_isi(struct isi_platform_data *data,
+               bool use_pck_as_mck)
+{
+       struct clk *pck;
+       struct clk *parent;
+
+       if (!data)
+               return;
+       isi_data = *data;
+
+       at91_set_A_periph(AT91_PIN_PB20, 0);    /* ISI_D0 */
+       at91_set_A_periph(AT91_PIN_PB21, 0);    /* ISI_D1 */
+       at91_set_A_periph(AT91_PIN_PB22, 0);    /* ISI_D2 */
+       at91_set_A_periph(AT91_PIN_PB23, 0);    /* ISI_D3 */
+       at91_set_A_periph(AT91_PIN_PB24, 0);    /* ISI_D4 */
+       at91_set_A_periph(AT91_PIN_PB25, 0);    /* ISI_D5 */
+       at91_set_A_periph(AT91_PIN_PB26, 0);    /* ISI_D6 */
+       at91_set_A_periph(AT91_PIN_PB27, 0);    /* ISI_D7 */
+       at91_set_A_periph(AT91_PIN_PB28, 0);    /* ISI_PCK */
+       at91_set_A_periph(AT91_PIN_PB30, 0);    /* ISI_HSYNC */
+       at91_set_A_periph(AT91_PIN_PB29, 0);    /* ISI_VSYNC */
+       at91_set_B_periph(AT91_PIN_PB8, 0);     /* ISI_PD8 */
+       at91_set_B_periph(AT91_PIN_PB9, 0);     /* ISI_PD9 */
+       at91_set_B_periph(AT91_PIN_PB10, 0);    /* ISI_PD10 */
+       at91_set_B_periph(AT91_PIN_PB11, 0);    /* ISI_PD11 */
+
+       platform_device_register(&at91sam9g45_isi_device);
+
+       if (use_pck_as_mck) {
+               at91_set_B_periph(AT91_PIN_PB31, 0);    /* ISI_MCK (PCK1) */
+
+               pck = clk_get(NULL, "pck1");
+               parent = clk_get(NULL, "plla");
+
+               BUG_ON(IS_ERR(pck) || IS_ERR(parent));
+
+               if (clk_set_parent(pck, parent)) {
+                       pr_err("Failed to set PCK's parent\n");
+               } else {
+                       /* Register PCK as ISI_MCK */
+                       isi_mck_lookups[0].clk = pck;
+                       clkdev_add_table(isi_mck_lookups,
+                                       ARRAY_SIZE(isi_mck_lookups));
+               }
+
+               clk_put(pck);
+               clk_put(parent);
+       }
+}
+#else
+void __init at91_add_device_isi(struct isi_platform_data *data,
+               bool use_pck_as_mck) {}
+#endif
+
 
 /* --------------------------------------------------------------------
  *  LCD Controller
@@ -1098,6 +1194,8 @@ static struct resource rtt_resources[] = {
                .start  = AT91SAM9G45_BASE_RTT,
                .end    = AT91SAM9G45_BASE_RTT + SZ_16 - 1,
                .flags  = IORESOURCE_MEM,
+       }, {
+               .flags  = IORESOURCE_MEM,
        }
 };
 
@@ -1105,11 +1203,32 @@ static struct platform_device at91sam9g45_rtt_device = {
        .name           = "at91_rtt",
        .id             = 0,
        .resource       = rtt_resources,
-       .num_resources  = ARRAY_SIZE(rtt_resources),
 };
 
+#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
+static void __init at91_add_device_rtt_rtc(void)
+{
+       at91sam9g45_rtt_device.name = "rtc-at91sam9";
+       /*
+        * The second resource is needed:
+        * GPBR will serve as the storage for RTC time offset
+        */
+       at91sam9g45_rtt_device.num_resources = 2;
+       rtt_resources[1].start = AT91SAM9G45_BASE_GPBR +
+                                4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
+       rtt_resources[1].end = rtt_resources[1].start + 3;
+}
+#else
+static void __init at91_add_device_rtt_rtc(void)
+{
+       /* Only one resource is needed: RTT not used as RTC */
+       at91sam9g45_rtt_device.num_resources = 1;
+}
+#endif
+
 static void __init at91_add_device_rtt(void)
 {
+       at91_add_device_rtt_rtc();
        platform_device_register(&at91sam9g45_rtt_device);
 }
 
@@ -1564,7 +1683,6 @@ static inline void configure_usart3_pins(unsigned pins)
 }
 
 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];  /* the UARTs to use */
-struct platform_device *atmel_default_console_device;  /* the serial console device */
 
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
index 0468be10980b57dce18e057817cf3879fb39a545..9d457182c86c73f7ab5d3a0daef884781a518bbb 100644 (file)
@@ -12,7 +12,7 @@
 
 #include <linux/linkage.h>
 #include <mach/hardware.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ramc.h>
 #include <mach/at91_rstc.h>
 
                        .arm
                        .globl  at91sam9g45_restart
 
 at91sam9g45_restart:
-                       ldr     r0, .at91_va_base_sdramc0       @ preload constants
-                       ldr     r1, =at91_rstc_base
-                       ldr     r1, [r1]
+                       ldr     r5, =at91_ramc_base             @ preload constants
+                       ldr     r0, [r5]
+                       ldr     r4, =at91_rstc_base
+                       ldr     r1, [r4]
 
                        mov     r2, #1
                        mov     r3, #AT91_DDRSDRC_LPCB_POWER_DOWN
@@ -35,6 +36,3 @@ at91sam9g45_restart:
                        str     r4, [r1, #AT91_RSTC_CR]         @ reset processor
 
                        b       .
-
-.at91_va_base_sdramc0:
-       .word AT91_VA_BASE_SYS + AT91_DDRSDRC0
index fd60e226a987d1533504327dfe22e17a6a08b9d2..63d9372eb18efe2f9d476aa85c7d9e4f724ef4b7 100644 (file)
@@ -288,19 +288,15 @@ static void __init at91sam9rl_ioremap_registers(void)
 {
        at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
        at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
+       at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
        at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
        at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
-}
-
-static void at91sam9rl_idle(void)
-{
-       at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
-       cpu_do_idle();
+       at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
 }
 
 static void __init at91sam9rl_initialize(void)
 {
-       arm_pm_idle = at91sam9rl_idle;
+       arm_pm_idle = at91sam9_idle;
        arm_pm_restart = at91sam9_alt_restart;
        at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
 
index 61908dce978447156f557866055fe93da689fe52..eda72e83037dc7dd176c859e7f4ad874a9506a75 100644 (file)
@@ -20,6 +20,7 @@
 #include <mach/board.h>
 #include <mach/at91sam9rl.h>
 #include <mach/at91sam9rl_matrix.h>
+#include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at_hdmac.h>
 
 #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
 static u64 hdmac_dmamask = DMA_BIT_MASK(32);
 
-static struct at_dma_platform_data atdma_pdata = {
-       .nr_channels    = 2,
-};
-
 static struct resource hdmac_resources[] = {
        [0] = {
                .start  = AT91SAM9RL_BASE_DMA,
@@ -51,12 +48,11 @@ static struct resource hdmac_resources[] = {
 };
 
 static struct platform_device at_hdmac_device = {
-       .name           = "at_hdmac",
+       .name           = "at91sam9rl_dma",
        .id             = -1,
        .dev            = {
                                .dma_mask               = &hdmac_dmamask,
                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                               .platform_data          = &atdma_pdata,
        },
        .resource       = hdmac_resources,
        .num_resources  = ARRAY_SIZE(hdmac_resources),
@@ -64,7 +60,6 @@ static struct platform_device at_hdmac_device = {
 
 void __init at91_add_device_hdmac(void)
 {
-       dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask);
        platform_device_register(&at_hdmac_device);
 }
 #else
@@ -271,8 +266,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
        if (!data)
                return;
 
-       csa = at91_sys_read(AT91_MATRIX_EBICSA);
-       at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+       csa = at91_matrix_read(AT91_MATRIX_EBICSA);
+       at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
 
        /* enable pin */
        if (gpio_is_valid(data->enable_pin))
@@ -688,6 +683,8 @@ static struct resource rtt_resources[] = {
                .start  = AT91SAM9RL_BASE_RTT,
                .end    = AT91SAM9RL_BASE_RTT + SZ_16 - 1,
                .flags  = IORESOURCE_MEM,
+       }, {
+               .flags  = IORESOURCE_MEM,
        }
 };
 
@@ -695,11 +692,32 @@ static struct platform_device at91sam9rl_rtt_device = {
        .name           = "at91_rtt",
        .id             = 0,
        .resource       = rtt_resources,
-       .num_resources  = ARRAY_SIZE(rtt_resources),
 };
 
+#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
+static void __init at91_add_device_rtt_rtc(void)
+{
+       at91sam9rl_rtt_device.name = "rtc-at91sam9";
+       /*
+        * The second resource is needed:
+        * GPBR will serve as the storage for RTC time offset
+        */
+       at91sam9rl_rtt_device.num_resources = 2;
+       rtt_resources[1].start = AT91SAM9RL_BASE_GPBR +
+                                4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
+       rtt_resources[1].end = rtt_resources[1].start + 3;
+}
+#else
+static void __init at91_add_device_rtt_rtc(void)
+{
+       /* Only one resource is needed: RTT not used as RTC */
+       at91sam9rl_rtt_device.num_resources = 1;
+}
+#endif
+
 static void __init at91_add_device_rtt(void)
 {
+       at91_add_device_rtt_rtc();
        platform_device_register(&at91sam9rl_rtt_device);
 }
 
@@ -1134,7 +1152,6 @@ static inline void configure_usart3_pins(unsigned pins)
 }
 
 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];  /* the UARTs to use */
-struct platform_device *atmel_default_console_device;  /* the serial console device */
 
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
new file mode 100644 (file)
index 0000000..d17d426
--- /dev/null
@@ -0,0 +1,370 @@
+/*
+ *  Chip-specific setup code for the AT91SAM9x5 family
+ *
+ *  Copyright (C) 2010-2012 Atmel Corporation.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/module.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/at91sam9x5.h>
+#include <mach/at91_pmc.h>
+#include <mach/cpu.h>
+#include <mach/board.h>
+
+#include "soc.h"
+#include "generic.h"
+#include "clock.h"
+#include "sam9_smc.h"
+
+/* --------------------------------------------------------------------
+ *  Clocks
+ * -------------------------------------------------------------------- */
+
+/*
+ * The peripheral clocks.
+ */
+static struct clk pioAB_clk = {
+       .name           = "pioAB_clk",
+       .pmc_mask       = 1 << AT91SAM9X5_ID_PIOAB,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioCD_clk = {
+       .name           = "pioCD_clk",
+       .pmc_mask       = 1 << AT91SAM9X5_ID_PIOCD,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk smd_clk = {
+       .name           = "smd_clk",
+       .pmc_mask       = 1 << AT91SAM9X5_ID_SMD,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart0_clk = {
+       .name           = "usart0_clk",
+       .pmc_mask       = 1 << AT91SAM9X5_ID_USART0,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart1_clk = {
+       .name           = "usart1_clk",
+       .pmc_mask       = 1 << AT91SAM9X5_ID_USART1,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart2_clk = {
+       .name           = "usart2_clk",
+       .pmc_mask       = 1 << AT91SAM9X5_ID_USART2,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+/* USART3 clock - Only for sam9g25/sam9x25 */
+static struct clk usart3_clk = {
+       .name           = "usart3_clk",
+       .pmc_mask       = 1 << AT91SAM9X5_ID_USART3,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk twi0_clk = {
+       .name           = "twi0_clk",
+       .pmc_mask       = 1 << AT91SAM9X5_ID_TWI0,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk twi1_clk = {
+       .name           = "twi1_clk",
+       .pmc_mask       = 1 << AT91SAM9X5_ID_TWI1,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk twi2_clk = {
+       .name           = "twi2_clk",
+       .pmc_mask       = 1 << AT91SAM9X5_ID_TWI2,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk mmc0_clk = {
+       .name           = "mci0_clk",
+       .pmc_mask       = 1 << AT91SAM9X5_ID_MCI0,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi0_clk = {
+       .name           = "spi0_clk",
+       .pmc_mask       = 1 << AT91SAM9X5_ID_SPI0,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi1_clk = {
+       .name           = "spi1_clk",
+       .pmc_mask       = 1 << AT91SAM9X5_ID_SPI1,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk uart0_clk = {
+       .name           = "uart0_clk",
+       .pmc_mask       = 1 << AT91SAM9X5_ID_UART0,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk uart1_clk = {
+       .name           = "uart1_clk",
+       .pmc_mask       = 1 << AT91SAM9X5_ID_UART1,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tcb0_clk = {
+       .name           = "tcb0_clk",
+       .pmc_mask       = 1 << AT91SAM9X5_ID_TCB,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pwm_clk = {
+       .name           = "pwm_clk",
+       .pmc_mask       = 1 << AT91SAM9X5_ID_PWM,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk adc_clk = {
+       .name           = "adc_clk",
+       .pmc_mask       = 1 << AT91SAM9X5_ID_ADC,
+       .type   = CLK_TYPE_PERIPHERAL,
+};
+static struct clk dma0_clk = {
+       .name           = "dma0_clk",
+       .pmc_mask       = 1 << AT91SAM9X5_ID_DMA0,
+       .type   = CLK_TYPE_PERIPHERAL,
+};
+static struct clk dma1_clk = {
+       .name           = "dma1_clk",
+       .pmc_mask       = 1 << AT91SAM9X5_ID_DMA1,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk uhphs_clk = {
+       .name           = "uhphs_clk",
+       .pmc_mask       = 1 << AT91SAM9X5_ID_UHPHS,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk udphs_clk = {
+       .name           = "udphs_clk",
+       .pmc_mask       = 1 << AT91SAM9X5_ID_UDPHS,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+/* emac0 clock - Only for sam9g25/sam9x25/sam9g35/sam9x35 */
+static struct clk macb0_clk = {
+       .name           = "pclk",
+       .pmc_mask       = 1 << AT91SAM9X5_ID_EMAC0,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+/* lcd clock - Only for sam9g15/sam9g35/sam9x35 */
+static struct clk lcdc_clk = {
+       .name           = "lcdc_clk",
+       .pmc_mask       = 1 << AT91SAM9X5_ID_LCDC,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+/* isi clock - Only for sam9g25 */
+static struct clk isi_clk = {
+       .name           = "isi_clk",
+       .pmc_mask       = 1 << AT91SAM9X5_ID_ISI,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk mmc1_clk = {
+       .name           = "mci1_clk",
+       .pmc_mask       = 1 << AT91SAM9X5_ID_MCI1,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+/* emac1 clock - Only for sam9x25 */
+static struct clk macb1_clk = {
+       .name           = "pclk",
+       .pmc_mask       = 1 << AT91SAM9X5_ID_EMAC1,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc_clk = {
+       .name           = "ssc_clk",
+       .pmc_mask       = 1 << AT91SAM9X5_ID_SSC,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+/* can0 clock - Only for sam9x35 */
+static struct clk can0_clk = {
+       .name           = "can0_clk",
+       .pmc_mask       = 1 << AT91SAM9X5_ID_CAN0,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+/* can1 clock - Only for sam9x35 */
+static struct clk can1_clk = {
+       .name           = "can1_clk",
+       .pmc_mask       = 1 << AT91SAM9X5_ID_CAN1,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+
+static struct clk *periph_clocks[] __initdata = {
+       &pioAB_clk,
+       &pioCD_clk,
+       &smd_clk,
+       &usart0_clk,
+       &usart1_clk,
+       &usart2_clk,
+       &twi0_clk,
+       &twi1_clk,
+       &twi2_clk,
+       &mmc0_clk,
+       &spi0_clk,
+       &spi1_clk,
+       &uart0_clk,
+       &uart1_clk,
+       &tcb0_clk,
+       &pwm_clk,
+       &adc_clk,
+       &dma0_clk,
+       &dma1_clk,
+       &uhphs_clk,
+       &udphs_clk,
+       &mmc1_clk,
+       &ssc_clk,
+       // irq0
+};
+
+static struct clk_lookup periph_clocks_lookups[] = {
+       /* lookup table for DT entries */
+       CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
+       CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
+       CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
+       CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
+       CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
+       CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb0_clk),
+       CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
+       CLKDEV_CON_ID("pioA", &pioAB_clk),
+       CLKDEV_CON_ID("pioB", &pioAB_clk),
+       CLKDEV_CON_ID("pioC", &pioCD_clk),
+       CLKDEV_CON_ID("pioD", &pioCD_clk),
+       /* additional fake clock for macb_hclk */
+       CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb0_clk),
+       CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk),
+};
+
+/*
+ * The two programmable clocks.
+ * You must configure pin multiplexing to bring these signals out.
+ */
+static struct clk pck0 = {
+       .name           = "pck0",
+       .pmc_mask       = AT91_PMC_PCK0,
+       .type           = CLK_TYPE_PROGRAMMABLE,
+       .id             = 0,
+};
+static struct clk pck1 = {
+       .name           = "pck1",
+       .pmc_mask       = AT91_PMC_PCK1,
+       .type           = CLK_TYPE_PROGRAMMABLE,
+       .id             = 1,
+};
+
+static void __init at91sam9x5_register_clocks(void)
+{
+       int i;
+
+       for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
+               clk_register(periph_clocks[i]);
+
+       clkdev_add_table(periph_clocks_lookups,
+                        ARRAY_SIZE(periph_clocks_lookups));
+
+       if (cpu_is_at91sam9g25()
+       || cpu_is_at91sam9x25())
+               clk_register(&usart3_clk);
+
+       if (cpu_is_at91sam9g25()
+       || cpu_is_at91sam9x25()
+       || cpu_is_at91sam9g35()
+       || cpu_is_at91sam9x35())
+               clk_register(&macb0_clk);
+
+       if (cpu_is_at91sam9g15()
+       || cpu_is_at91sam9g35()
+       || cpu_is_at91sam9x35())
+               clk_register(&lcdc_clk);
+
+       if (cpu_is_at91sam9g25())
+               clk_register(&isi_clk);
+
+       if (cpu_is_at91sam9x25())
+               clk_register(&macb1_clk);
+
+       if (cpu_is_at91sam9x25()
+       || cpu_is_at91sam9x35()) {
+               clk_register(&can0_clk);
+               clk_register(&can1_clk);
+       }
+
+       clk_register(&pck0);
+       clk_register(&pck1);
+}
+
+/* --------------------------------------------------------------------
+ *  AT91SAM9x5 processor initialization
+ * -------------------------------------------------------------------- */
+
+static void __init at91sam9x5_map_io(void)
+{
+       at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
+}
+
+static void __init at91sam9x5_ioremap_registers(void)
+{
+       if (of_at91sam926x_pit_init() < 0)
+               panic("Impossible to find PIT\n");
+       at91_ioremap_ramc(0, AT91SAM9X5_BASE_DDRSDRC0, 512);
+}
+
+void __init at91sam9x5_initialize(void)
+{
+       arm_pm_restart = at91sam9g45_restart;
+       at91_extern_irq = (1 << AT91SAM9X5_ID_IRQ0);
+
+       /* Register GPIO subsystem (using DT) */
+       at91_gpio_init(NULL, 0);
+}
+
+/* --------------------------------------------------------------------
+ *  AT91SAM9x5 devices (temporary before modification of code)
+ * -------------------------------------------------------------------- */
+void __init at91_add_device_nand(struct atmel_nand_data *data) {}
+
+/* --------------------------------------------------------------------
+ *  Interrupt initialization
+ * -------------------------------------------------------------------- */
+/*
+ * The default interrupt priority levels (0 = lowest, 7 = highest).
+ */
+static unsigned int at91sam9x5_default_irq_priority[NR_AIC_IRQS] __initdata = {
+       7,      /* Advanced Interrupt Controller (FIQ) */
+       7,      /* System Peripherals */
+       1,      /* Parallel IO Controller A and B */
+       1,      /* Parallel IO Controller C and D */
+       4,      /* Soft Modem */
+       5,      /* USART 0 */
+       5,      /* USART 1 */
+       5,      /* USART 2 */
+       5,      /* USART 3 */
+       6,      /* Two-Wire Interface 0 */
+       6,      /* Two-Wire Interface 1 */
+       6,      /* Two-Wire Interface 2 */
+       0,      /* Multimedia Card Interface 0 */
+       5,      /* Serial Peripheral Interface 0 */
+       5,      /* Serial Peripheral Interface 1 */
+       5,      /* UART 0 */
+       5,      /* UART 1 */
+       0,      /* Timer Counter 0, 1, 2, 3, 4 and 5 */
+       0,      /* Pulse Width Modulation Controller */
+       0,      /* ADC Controller */
+       0,      /* DMA Controller 0 */
+       0,      /* DMA Controller 1 */
+       2,      /* USB Host High Speed port */
+       2,      /* USB Device High speed port */
+       3,      /* Ethernet MAC 0 */
+       3,      /* LDC Controller or Image Sensor Interface */
+       0,      /* Multimedia Card Interface 1 */
+       3,      /* Ethernet MAC 1 */
+       4,      /* Synchronous Serial Interface */
+       4,      /* CAN Controller 0 */
+       4,      /* CAN Controller 1 */
+       0,      /* Advanced Interrupt Controller (IRQ0) */
+};
+
+struct at91_init_soc __initdata at91sam9x5_soc = {
+       .map_io = at91sam9x5_map_io,
+       .default_irq_priority = at91sam9x5_default_irq_priority,
+       .ioremap_registers = at91sam9x5_ioremap_registers,
+       .register_clocks = at91sam9x5_register_clocks,
+       .init = at91sam9x5_initialize,
+};
index 0154b7f44ff199a72483c70a94dcffe11bfb60cf..5400a1d6503566d7258a801e6b8aca3e6c636021 100644 (file)
@@ -44,7 +44,7 @@ static void at91x40_idle(void)
         * Disable the processor clock.  The processor will be automatically
         * re-enabled by an interrupt or by a reset.
         */
-       at91_sys_write(AT91_PS_CR, AT91_PS_CR_CPU);
+       __raw_writel(AT91_PS_CR_CPU, AT91_PS_CR);
        cpu_do_idle();
 }
 
index dfff2895f4b286c4134a2a9f6425c90ce27e76ca..6ca680a1d5d112bb32cfa347c08c845f4d24ff6f 100644 (file)
 #include <asm/mach/time.h>
 #include <mach/at91_tc.h>
 
+#define at91_tc_read(field) \
+       __raw_readl(AT91_TC + field)
+
+#define at91_tc_write(field, value) \
+       __raw_writel(value, AT91_TC + field);
+
 /*
  *     3 counter/timer units present.
  */
 
 static unsigned long at91x40_gettimeoffset(void)
 {
-       return (at91_sys_read(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 / (AT91X40_MASTER_CLOCK / 128));
+       return (at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 / (AT91X40_MASTER_CLOCK / 128));
 }
 
 static irqreturn_t at91x40_timer_interrupt(int irq, void *dev_id)
 {
-       at91_sys_read(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_SR);
+       at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_SR);
        timer_tick();
        return IRQ_HANDLED;
 }
@@ -57,20 +63,20 @@ void __init at91x40_timer_init(void)
 {
        unsigned int v;
 
-       at91_sys_write(AT91_TC + AT91_TC_BCR, 0);
-       v = at91_sys_read(AT91_TC + AT91_TC_BMR);
+       at91_tc_write(AT91_TC_BCR, 0);
+       v = at91_tc_read(AT91_TC_BMR);
        v = (v & ~AT91_TC_TC1XC1S) | AT91_TC_TC1XC1S_NONE;
-       at91_sys_write(AT91_TC + AT91_TC_BMR, v);
+       at91_tc_write(AT91_TC_BMR, v);
 
-       at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CCR, AT91_TC_CLKDIS);
-       at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CMR, (AT91_TC_TIMER_CLOCK4 | AT91_TC_CPCTRG));
-       at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_IDR, 0xffffffff);
-       at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_RC, (AT91X40_MASTER_CLOCK / 128) / HZ - 1);
-       at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_IER, (1<<4));
+       at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, AT91_TC_CLKDIS);
+       at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CMR, (AT91_TC_TIMER_CLOCK4 | AT91_TC_CPCTRG));
+       at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IDR, 0xffffffff);
+       at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_RC, (AT91X40_MASTER_CLOCK / 128) / HZ - 1);
+       at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IER, (1<<4));
 
        setup_irq(AT91X40_ID_TC1, &at91x40_timer_irq);
 
-       at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN));
+       at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN));
 }
 
 struct sys_timer at91x40_timer = {
diff --git a/arch/arm/mach-at91/board-cap9adk.c b/arch/arm/mach-at91/board-cap9adk.c
deleted file mode 100644 (file)
index ac3de4f..0000000
+++ /dev/null
@@ -1,396 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/board-cap9adk.c
- *
- *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
- *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
- *  Copyright (C) 2005 SAN People
- *  Copyright (C) 2007 Atmel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/types.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
-#include <linux/fb.h>
-#include <linux/mtd/physmap.h>
-
-#include <video/atmel_lcdc.h>
-
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include <mach/board.h>
-#include <mach/at91cap9_matrix.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/system_rev.h>
-
-#include "sam9_smc.h"
-#include "generic.h"
-
-
-static void __init cap9adk_init_early(void)
-{
-       /* Initialize processor: 12 MHz crystal */
-       at91_initialize(12000000);
-
-       /* Setup the LEDs: USER1 and USER2 LED for cpu/timer... */
-       at91_init_leds(AT91_PIN_PA10, AT91_PIN_PA11);
-       /* ... POWER LED always on */
-       at91_set_gpio_output(AT91_PIN_PC29, 1);
-
-       /* Setup the serial ports and console */
-       at91_register_uart(0, 0, 0);            /* DBGU = ttyS0 */
-       at91_set_serial_console(0);
-}
-
-/*
- * USB Host port
- */
-static struct at91_usbh_data __initdata cap9adk_usbh_data = {
-       .ports          = 2,
-       .vbus_pin       = {-EINVAL, -EINVAL},
-       .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-
-/*
- * USB HS Device port
- */
-static struct usba_platform_data __initdata cap9adk_usba_udc_data = {
-       .vbus_pin       = AT91_PIN_PB31,
-};
-
-/*
- * ADS7846 Touchscreen
- */
-#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
-static int ads7843_pendown_state(void)
-{
-       return !at91_get_gpio_value(AT91_PIN_PC4);      /* Touchscreen PENIRQ */
-}
-
-static struct ads7846_platform_data ads_info = {
-       .model                  = 7843,
-       .x_min                  = 150,
-       .x_max                  = 3830,
-       .y_min                  = 190,
-       .y_max                  = 3830,
-       .vref_delay_usecs       = 100,
-       .x_plate_ohms           = 450,
-       .y_plate_ohms           = 250,
-       .pressure_max           = 15000,
-       .debounce_max           = 1,
-       .debounce_rep           = 0,
-       .debounce_tol           = (~0),
-       .get_pendown_state      = ads7843_pendown_state,
-};
-
-static void __init cap9adk_add_device_ts(void)
-{
-       at91_set_gpio_input(AT91_PIN_PC4, 1);   /* Touchscreen PENIRQ */
-       at91_set_gpio_input(AT91_PIN_PC5, 1);   /* Touchscreen BUSY */
-}
-#else
-static void __init cap9adk_add_device_ts(void) {}
-#endif
-
-
-/*
- * SPI devices.
- */
-static struct spi_board_info cap9adk_spi_devices[] = {
-#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
-       {       /* DataFlash card */
-               .modalias       = "mtd_dataflash",
-               .chip_select    = 0,
-               .max_speed_hz   = 15 * 1000 * 1000,
-               .bus_num        = 0,
-       },
-#endif
-#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
-       {
-               .modalias       = "ads7846",
-               .chip_select    = 3,            /* can be 2 or 3, depending on J2 jumper */
-               .max_speed_hz   = 125000 * 26,  /* (max sample rate @ 3V) * (cmd + data + overhead) */
-               .bus_num        = 0,
-               .platform_data  = &ads_info,
-               .irq            = AT91_PIN_PC4,
-       },
-#endif
-};
-
-
-/*
- * MCI (SD/MMC)
- */
-static struct at91_mmc_data __initdata cap9adk_mmc_data = {
-       .wire4          = 1,
-       .det_pin        = -EINVAL,
-       .wp_pin         = -EINVAL,
-       .vcc_pin        = -EINVAL,
-};
-
-
-/*
- * MACB Ethernet device
- */
-static struct macb_platform_data __initdata cap9adk_macb_data = {
-       .phy_irq_pin    = -EINVAL,
-       .is_rmii        = 1,
-};
-
-
-/*
- * NAND flash
- */
-static struct mtd_partition __initdata cap9adk_nand_partitions[] = {
-       {
-               .name   = "NAND partition",
-               .offset = 0,
-               .size   = MTDPART_SIZ_FULL,
-       },
-};
-
-static struct atmel_nand_data __initdata cap9adk_nand_data = {
-       .ale            = 21,
-       .cle            = 22,
-       .det_pin        = -EINVAL,
-       .rdy_pin        = -EINVAL,
-       .enable_pin     = AT91_PIN_PD15,
-       .parts          = cap9adk_nand_partitions,
-       .num_parts      = ARRAY_SIZE(cap9adk_nand_partitions),
-};
-
-static struct sam9_smc_config __initdata cap9adk_nand_smc_config = {
-       .ncs_read_setup         = 1,
-       .nrd_setup              = 2,
-       .ncs_write_setup        = 1,
-       .nwe_setup              = 2,
-
-       .ncs_read_pulse         = 6,
-       .nrd_pulse              = 4,
-       .ncs_write_pulse        = 6,
-       .nwe_pulse              = 4,
-
-       .read_cycle             = 8,
-       .write_cycle            = 8,
-
-       .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
-       .tdf_cycles             = 1,
-};
-
-static void __init cap9adk_add_device_nand(void)
-{
-       unsigned long csa;
-
-       csa = at91_sys_read(AT91_MATRIX_EBICSA);
-       at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
-
-       cap9adk_nand_data.bus_width_16 = board_have_nand_16bit();
-       /* setup bus-width (8 or 16) */
-       if (cap9adk_nand_data.bus_width_16)
-               cap9adk_nand_smc_config.mode |= AT91_SMC_DBW_16;
-       else
-               cap9adk_nand_smc_config.mode |= AT91_SMC_DBW_8;
-
-       /* configure chip-select 3 (NAND) */
-       sam9_smc_configure(0, 3, &cap9adk_nand_smc_config);
-
-       at91_add_device_nand(&cap9adk_nand_data);
-}
-
-
-/*
- * NOR flash
- */
-static struct mtd_partition cap9adk_nor_partitions[] = {
-       {
-               .name           = "NOR partition",
-               .offset         = 0,
-               .size           = MTDPART_SIZ_FULL,
-       },
-};
-
-static struct physmap_flash_data cap9adk_nor_data = {
-       .width          = 2,
-       .parts          = cap9adk_nor_partitions,
-       .nr_parts       = ARRAY_SIZE(cap9adk_nor_partitions),
-};
-
-#define NOR_BASE       AT91_CHIPSELECT_0
-#define NOR_SIZE       SZ_8M
-
-static struct resource nor_flash_resources[] = {
-       {
-               .start  = NOR_BASE,
-               .end    = NOR_BASE + NOR_SIZE - 1,
-               .flags  = IORESOURCE_MEM,
-       }
-};
-
-static struct platform_device cap9adk_nor_flash = {
-       .name           = "physmap-flash",
-       .id             = 0,
-       .dev            = {
-                               .platform_data  = &cap9adk_nor_data,
-       },
-       .resource       = nor_flash_resources,
-       .num_resources  = ARRAY_SIZE(nor_flash_resources),
-};
-
-static struct sam9_smc_config __initdata cap9adk_nor_smc_config = {
-       .ncs_read_setup         = 2,
-       .nrd_setup              = 4,
-       .ncs_write_setup        = 2,
-       .nwe_setup              = 4,
-
-       .ncs_read_pulse         = 10,
-       .nrd_pulse              = 8,
-       .ncs_write_pulse        = 10,
-       .nwe_pulse              = 8,
-
-       .read_cycle             = 16,
-       .write_cycle            = 16,
-
-       .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16,
-       .tdf_cycles             = 1,
-};
-
-static __init void cap9adk_add_device_nor(void)
-{
-       unsigned long csa;
-
-       csa = at91_sys_read(AT91_MATRIX_EBICSA);
-       at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
-
-       /* configure chip-select 0 (NOR) */
-       sam9_smc_configure(0, 0, &cap9adk_nor_smc_config);
-
-       platform_device_register(&cap9adk_nor_flash);
-}
-
-
-/*
- * LCD Controller
- */
-#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
-static struct fb_videomode at91_tft_vga_modes[] = {
-       {
-               .name           = "TX09D50VM1CCA @ 60",
-               .refresh        = 60,
-               .xres           = 240,          .yres           = 320,
-               .pixclock       = KHZ2PICOS(4965),
-
-               .left_margin    = 1,            .right_margin   = 33,
-               .upper_margin   = 1,            .lower_margin   = 0,
-               .hsync_len      = 5,            .vsync_len      = 1,
-
-               .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-               .vmode          = FB_VMODE_NONINTERLACED,
-       },
-};
-
-static struct fb_monspecs at91fb_default_monspecs = {
-       .manufacturer   = "HIT",
-       .monitor        = "TX09D70VM1CCA",
-
-       .modedb         = at91_tft_vga_modes,
-       .modedb_len     = ARRAY_SIZE(at91_tft_vga_modes),
-       .hfmin          = 15000,
-       .hfmax          = 64000,
-       .vfmin          = 50,
-       .vfmax          = 150,
-};
-
-#define AT91CAP9_DEFAULT_LCDCON2       (ATMEL_LCDC_MEMOR_LITTLE \
-                                       | ATMEL_LCDC_DISTYPE_TFT    \
-                                       | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
-
-static void at91_lcdc_power_control(int on)
-{
-       if (on)
-               at91_set_gpio_value(AT91_PIN_PC0, 0);   /* power up */
-       else
-               at91_set_gpio_value(AT91_PIN_PC0, 1);   /* power down */
-}
-
-/* Driver datas */
-static struct atmel_lcdfb_info __initdata cap9adk_lcdc_data = {
-       .default_bpp                    = 16,
-       .default_dmacon                 = ATMEL_LCDC_DMAEN,
-       .default_lcdcon2                = AT91CAP9_DEFAULT_LCDCON2,
-       .default_monspecs               = &at91fb_default_monspecs,
-       .atmel_lcdfb_power_control      = at91_lcdc_power_control,
-       .guard_time                     = 1,
-};
-
-#else
-static struct atmel_lcdfb_info __initdata cap9adk_lcdc_data;
-#endif
-
-
-/*
- * AC97
- */
-static struct ac97c_platform_data cap9adk_ac97_data = {
-       .reset_pin      = -EINVAL,
-};
-
-
-static void __init cap9adk_board_init(void)
-{
-       /* Serial */
-       at91_add_device_serial();
-       /* USB Host */
-       at91_add_device_usbh(&cap9adk_usbh_data);
-       /* USB HS */
-       at91_add_device_usba(&cap9adk_usba_udc_data);
-       /* SPI */
-       at91_add_device_spi(cap9adk_spi_devices, ARRAY_SIZE(cap9adk_spi_devices));
-       /* Touchscreen */
-       cap9adk_add_device_ts();
-       /* MMC */
-       at91_add_device_mmc(1, &cap9adk_mmc_data);
-       /* Ethernet */
-       at91_add_device_eth(&cap9adk_macb_data);
-       /* NAND */
-       cap9adk_add_device_nand();
-       /* NOR Flash */
-       cap9adk_add_device_nor();
-       /* I2C */
-       at91_add_device_i2c(NULL, 0);
-       /* LCD Controller */
-       at91_add_device_lcdc(&cap9adk_lcdc_data);
-       /* AC97 */
-       at91_add_device_ac97(&cap9adk_ac97_data);
-}
-
-MACHINE_START(AT91CAP9ADK, "Atmel AT91CAP9A-DK")
-       /* Maintainer: Stelian Pop <stelian.pop@leadtechdesign.com> */
-       .timer          = &at91sam926x_timer,
-       .map_io         = at91_map_io,
-       .init_early     = cap9adk_init_early,
-       .init_irq       = at91_init_irq_default,
-       .init_machine   = cap9adk_board_init,
-MACHINE_END
index 9ab3d1ea326d445bfe36bda16e37e47119a94f7a..989e1c5a9ca0428a8caca37bc18625bf3278502b 100644 (file)
@@ -43,6 +43,7 @@
 #include <mach/board.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91sam9260_matrix.h>
+#include <mach/at91_matrix.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
@@ -238,8 +239,8 @@ static __init void cpu9krea_add_device_nor(void)
 {
        unsigned long csa;
 
-       csa = at91_sys_read(AT91_MATRIX_EBICSA);
-       at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_VDDIOMSEL_3_3V);
+       csa = at91_matrix_read(AT91_MATRIX_EBICSA);
+       at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_VDDIOMSEL_3_3V);
 
        /* configure chip-select 0 (NOR) */
        sam9_smc_configure(0, 0, &cpu9krea_nor_smc_config);
index 368e1427ad998af7be547ed2689c6b5a0d0aacf4..e094cc81fe251d099fc31ceef5af8d9d2bfe1dd0 100644 (file)
@@ -38,6 +38,7 @@
 
 #include <mach/board.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 #include <mach/cpu.h>
 
 #include "generic.h"
index bb6b434ec0c1c6c868be388603f7b63cfe37b01b..08c8ad8609b701e4a9d4220495e29e71114d2d20 100644 (file)
@@ -38,12 +38,6 @@ static void __init ek_init_early(void)
 {
        /* Initialize processor: 12.000 MHz crystal */
        at91_initialize(12000000);
-
-       /* DGBU on ttyS0. (Rx & Tx only) */
-       at91_register_uart(0, 0, 0);
-
-       /* set serial console to ttyS0 (ie, DBGU) */
-       at91_set_serial_console(0);
 }
 
 /* det_pin is not connected */
@@ -109,6 +103,7 @@ static void __init at91_dt_device_init(void)
 
 static const char *at91_dt_board_compat[] __initdata = {
        "atmel,at91sam9m10g45ek",
+       "atmel,at91sam9x5ek",
        "calao,usb-a9g20",
        NULL
 };
index 07ef35b0ec2cdceecf7e124e705cb842c31b1b62..f23aabef8551d69fc395dcf88b5eabdf152fe2f8 100644 (file)
@@ -26,6 +26,7 @@
 
 #include <mach/board.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 #include <mach/cpu.h>
 
 #include "generic.h"
@@ -110,7 +111,7 @@ static void __init eco920_board_init(void)
        at91_add_device_mmc(0, &eco920_mmc_data);
        platform_device_register(&eco920_flash);
 
-       at91_sys_write(AT91_SMC_CSR(7), AT91_SMC_RWHOLD_(1)
+       at91_ramc_write(0, AT91_SMC_CSR(7),     AT91_SMC_RWHOLD_(1)
                                | AT91_SMC_RWSETUP_(1)
                                | AT91_SMC_DBW_8
                                | AT91_SMC_WSEN
@@ -122,7 +123,7 @@ static void __init eco920_board_init(void)
        at91_set_deglitch(AT91_PIN_PA23, 1);
 
 /* Initialization of the Static Memory Controller for Chip Select 3 */
-       at91_sys_write(AT91_SMC_CSR(3),
+       at91_ramc_write(0, AT91_SMC_CSR(3),
                AT91_SMC_DBW_16  |      /* 16 bit */
                AT91_SMC_WSEN    |
                AT91_SMC_NWS_(5) |      /* wait states */
index eec02cd57ced7fe60291f8938a64259f61b0f22a..1815152001f74c62d3d4dd409252a2c81aa197b0 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * linux/arch/arm/mach-at91/board-flexibity.c
  *
- *  Copyright (C) 2010 Flexibity
+ *  Copyright (C) 2010-2011 Flexibity
  *  Copyright (C) 2005 SAN People
  *  Copyright (C) 2006 Atmel
  *
@@ -62,6 +62,13 @@ static struct at91_udc_data __initdata flexibity_udc_data = {
        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
 };
 
+/* I2C devices */
+static struct i2c_board_info __initdata flexibity_i2c_devices[] = {
+       {
+               I2C_BOARD_INFO("ds1307", 0x68),
+       },
+};
+
 /* SPI devices */
 static struct spi_board_info flexibity_spi_devices[] = {
        {       /* DataFlash chip */
@@ -141,6 +148,9 @@ static void __init flexibity_board_init(void)
        at91_add_device_usbh(&flexibity_usbh_data);
        /* USB Device */
        at91_add_device_udc(&flexibity_udc_data);
+       /* I2C */
+       at91_add_device_i2c(flexibity_i2c_devices,
+               ARRAY_SIZE(flexibity_i2c_devices));
        /* SPI */
        at91_add_device_spi(flexibity_spi_devices,
                ARRAY_SIZE(flexibity_spi_devices));
index d75a4a2ad9c20bc9d1e13067c5f6db4d689bbc9c..bb9914582013684336c958e8a3ca53f8f3f7a942 100644 (file)
@@ -38,6 +38,7 @@
 #include <mach/board.h>
 #include <mach/cpu.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 
 #include "generic.h"
 
index ab024fa11d5c7d1011086070178b1e7dc3f04ca6..59e35dd1486301b556f20befed659a5bea9525b2 100644 (file)
@@ -39,6 +39,7 @@
 
 #include <mach/board.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 
 #include "generic.h"
 
index 782f37946af5b561ea066d491ce51f4cd645c44e..9083df04e7edb669b6f2fc1de5344964b47e94be 100644 (file)
@@ -41,6 +41,7 @@
 #include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 
 #include "generic.h"
 
index ef7c12a922464d3accbd06e263a2e548115906ac..11cbaa8946fe0e269877104aac08da9fe03818e9 100644 (file)
@@ -41,6 +41,7 @@
 #include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 
 #include "generic.h"
 
index ea0d1b9c2b7bd0327326a227509f7d4f1c896263..57497e2b8878cc11e34e95f4245674a81aa9b45f 100644 (file)
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
 #include <linux/leds.h>
-#include <linux/clk.h>
 #include <linux/atmel-mci.h>
+#include <linux/delay.h>
 
 #include <mach/hardware.h>
 #include <video/atmel_lcdc.h>
+#include <media/soc_camera.h>
+#include <media/atmel-isi.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -184,6 +186,71 @@ static void __init ek_add_device_nand(void)
 }
 
 
+/*
+ *  ISI
+ */
+static struct isi_platform_data __initdata isi_data = {
+       .frate                  = ISI_CFG1_FRATE_CAPTURE_ALL,
+       /* to use codec and preview path simultaneously */
+       .full_mode              = 1,
+       .data_width_flags       = ISI_DATAWIDTH_8 | ISI_DATAWIDTH_10,
+       /* ISI_MCK is provided by programmable clock or external clock */
+       .mck_hz                 = 25000000,
+};
+
+
+/*
+ * soc-camera OV2640
+ */
+#if defined(CONFIG_SOC_CAMERA_OV2640) || \
+       defined(CONFIG_SOC_CAMERA_OV2640_MODULE)
+static unsigned long isi_camera_query_bus_param(struct soc_camera_link *link)
+{
+       /* ISI board for ek using default 8-bits connection */
+       return SOCAM_DATAWIDTH_8;
+}
+
+static int i2c_camera_power(struct device *dev, int on)
+{
+       /* enable or disable the camera */
+       pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
+       at91_set_gpio_output(AT91_PIN_PD13, !on);
+
+       if (!on)
+               goto out;
+
+       /* If enabled, give a reset impulse */
+       at91_set_gpio_output(AT91_PIN_PD12, 0);
+       msleep(20);
+       at91_set_gpio_output(AT91_PIN_PD12, 1);
+       msleep(100);
+
+out:
+       return 0;
+}
+
+static struct i2c_board_info i2c_camera = {
+       I2C_BOARD_INFO("ov2640", 0x30),
+};
+
+static struct soc_camera_link iclink_ov2640 = {
+       .bus_id                 = 0,
+       .board_info             = &i2c_camera,
+       .i2c_adapter_id         = 0,
+       .power                  = i2c_camera_power,
+       .query_bus_param        = isi_camera_query_bus_param,
+};
+
+static struct platform_device isi_ov2640 = {
+       .name   = "soc-camera-pdrv",
+       .id     = 0,
+       .dev    = {
+               .platform_data = &iclink_ov2640,
+       },
+};
+#endif
+
+
 /*
  * LCD Controller
  */
@@ -377,7 +444,12 @@ static struct gpio_led ek_pwm_led[] = {
 #endif
 };
 
-
+static struct platform_device *devices[] __initdata = {
+#if defined(CONFIG_SOC_CAMERA_OV2640) || \
+       defined(CONFIG_SOC_CAMERA_OV2640_MODULE)
+       &isi_ov2640,
+#endif
+};
 
 static void __init ek_board_init(void)
 {
@@ -399,6 +471,8 @@ static void __init ek_board_init(void)
        ek_add_device_nand();
        /* I2C */
        at91_add_device_i2c(0, NULL, 0);
+       /* ISI, using programmable clock as ISI_MCK */
+       at91_add_device_isi(&isi_data, true);
        /* LCD Controller */
        at91_add_device_lcdc(&ek_lcdc_data);
        /* Touch Screen */
@@ -410,6 +484,8 @@ static void __init ek_board_init(void)
        /* LEDs */
        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
        at91_pwm_leds(ek_pwm_led, ARRAY_SIZE(ek_pwm_led));
+       /* Other platform devices */
+       platform_add_devices(devices, ARRAY_SIZE(devices));
 }
 
 MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK")
index bbd553e1cd93d024cc4b8c5931f989c3a5becbfa..52f460768f71ef758bb541c85735b722acc6be6e 100644 (file)
@@ -45,6 +45,7 @@
 #include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 #include <mach/cpu.h>
 
 #include "generic.h"
@@ -393,7 +394,7 @@ static void yl9200_init_video(void)
        at91_set_A_periph(AT91_PIN_PC6, 0);
 
        /* Initialization of the Static Memory Controller for Chip Select 2 */
-       at91_sys_write(AT91_SMC_CSR(2), AT91_SMC_DBW_16         /* 16 bit */
+       at91_ramc_write(0, AT91_SMC_CSR(2), AT91_SMC_DBW_16             /* 16 bit */
                        | AT91_SMC_WSEN | AT91_SMC_NWS_(0x4)    /* wait states */
                        | AT91_SMC_TDF_(0x100)                  /* float time */
        );
index 61873f3aa92d74f2aaa327a4f0e7d0021f502d02..be51ca7f694d1a0515ddd9d5ecf0c4a9253dc078 100644 (file)
 #include <mach/at91_pmc.h>
 #include <mach/cpu.h>
 
+#include <asm/proc-fns.h>
+
 #include "clock.h"
 #include "generic.h"
 
+void __iomem *at91_pmc_base;
 
 /*
  * There's a lot more which can be done with clocks, including cpufreq
 /*
  * Chips have some kind of clocks : group them by functionality
  */
-#define cpu_has_utmi()         (  cpu_is_at91cap9() \
-                               || cpu_is_at91sam9rl() \
-                               || cpu_is_at91sam9g45())
+#define cpu_has_utmi()         (  cpu_is_at91sam9rl() \
+                               || cpu_is_at91sam9g45() \
+                               || cpu_is_at91sam9x5())
 
 #define cpu_has_800M_plla()    (  cpu_is_at91sam9g20() \
-                               || cpu_is_at91sam9g45())
+                               || cpu_is_at91sam9g45() \
+                               || cpu_is_at91sam9x5())
 
 #define cpu_has_300M_plla()    (cpu_is_at91sam9g10())
 
 #define cpu_has_pllb()         (!(cpu_is_at91sam9rl() \
-                               || cpu_is_at91sam9g45()))
+                               || cpu_is_at91sam9g45() \
+                               || cpu_is_at91sam9x5()))
 
-#define cpu_has_upll()         (cpu_is_at91sam9g45())
+#define cpu_has_upll()         (cpu_is_at91sam9g45() \
+                               || cpu_is_at91sam9x5())
 
 /* USB host HS & FS */
 #define cpu_has_uhp()          (!cpu_is_at91sam9rl())
 
 /* USB device FS only */
 #define cpu_has_udpfs()                (!(cpu_is_at91sam9rl() \
-                               || cpu_is_at91sam9g45()))
+                               || cpu_is_at91sam9g45() \
+                               || cpu_is_at91sam9x5()))
+
+#define cpu_has_plladiv2()     (cpu_is_at91sam9g45() \
+                               || cpu_is_at91sam9x5())
+
+#define cpu_has_mdiv3()                (cpu_is_at91sam9g45() \
+                               || cpu_is_at91sam9x5())
+
+#define cpu_has_alt_prescaler()        (cpu_is_at91sam9x5())
 
 static LIST_HEAD(clocks);
 static DEFINE_SPINLOCK(clk_lock);
@@ -111,11 +126,11 @@ static void pllb_mode(struct clk *clk, int is_on)
                value = 0;
 
        // REVISIT: Add work-around for AT91RM9200 Errata #26 ?
-       at91_sys_write(AT91_CKGR_PLLBR, value);
+       at91_pmc_write(AT91_CKGR_PLLBR, value);
 
        do {
                cpu_relax();
-       } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
+       } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
 }
 
 static struct clk pllb = {
@@ -130,31 +145,24 @@ static struct clk pllb = {
 static void pmc_sys_mode(struct clk *clk, int is_on)
 {
        if (is_on)
-               at91_sys_write(AT91_PMC_SCER, clk->pmc_mask);
+               at91_pmc_write(AT91_PMC_SCER, clk->pmc_mask);
        else
-               at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
+               at91_pmc_write(AT91_PMC_SCDR, clk->pmc_mask);
 }
 
 static void pmc_uckr_mode(struct clk *clk, int is_on)
 {
-       unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
-
-       if (cpu_is_at91sam9g45()) {
-               if (is_on)
-                       uckr |= AT91_PMC_BIASEN;
-               else
-                       uckr &= ~AT91_PMC_BIASEN;
-       }
+       unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR);
 
        if (is_on) {
                is_on = AT91_PMC_LOCKU;
-               at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
+               at91_pmc_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
        } else
-               at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
+               at91_pmc_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
 
        do {
                cpu_relax();
-       } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
+       } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
 }
 
 /* USB function clocks (PLLB must be 48 MHz) */
@@ -190,9 +198,9 @@ struct clk mck = {
 static void pmc_periph_mode(struct clk *clk, int is_on)
 {
        if (is_on)
-               at91_sys_write(AT91_PMC_PCER, clk->pmc_mask);
+               at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask);
        else
-               at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask);
+               at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask);
 }
 
 static struct clk __init *at91_css_to_clk(unsigned long css)
@@ -210,11 +218,24 @@ static struct clk __init *at91_css_to_clk(unsigned long css)
                                return &utmi_clk;
                        else if (cpu_has_pllb())
                                return &pllb;
+                       break;
+               /* alternate PMC: can use master clock */
+               case AT91_PMC_CSS_MASTER:
+                       return &mck;
        }
 
        return NULL;
 }
 
+static int pmc_prescaler_divider(u32 reg)
+{
+       if (cpu_has_alt_prescaler()) {
+               return 1 << ((reg & AT91_PMC_ALT_PRES) >> PMC_ALT_PRES_OFFSET);
+       } else {
+               return 1 << ((reg & AT91_PMC_PRES) >> PMC_PRES_OFFSET);
+       }
+}
+
 static void __clk_enable(struct clk *clk)
 {
        if (clk->parent)
@@ -316,12 +337,22 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
 {
        unsigned long   flags;
        unsigned        prescale;
+       unsigned long   prescale_offset, css_mask;
        unsigned long   actual;
 
        if (!clk_is_programmable(clk))
                return -EINVAL;
        if (clk->users)
                return -EBUSY;
+
+       if (cpu_has_alt_prescaler()) {
+               prescale_offset = PMC_ALT_PRES_OFFSET;
+               css_mask = AT91_PMC_ALT_PCKR_CSS;
+       } else {
+               prescale_offset = PMC_PRES_OFFSET;
+               css_mask = AT91_PMC_CSS;
+       }
+
        spin_lock_irqsave(&clk_lock, flags);
 
        actual = clk->parent->rate_hz;
@@ -329,10 +360,10 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
                if (actual && actual <= rate) {
                        u32     pckr;
 
-                       pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
-                       pckr &= AT91_PMC_CSS;   /* clock selection */
-                       pckr |= prescale << 2;
-                       at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
+                       pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
+                       pckr &= css_mask;       /* keep clock selection */
+                       pckr |= prescale << prescale_offset;
+                       at91_pmc_write(AT91_PMC_PCKR(clk->id), pckr);
                        clk->rate_hz = actual;
                        break;
                }
@@ -366,7 +397,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
 
        clk->rate_hz = parent->rate_hz;
        clk->parent = parent;
-       at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id);
+       at91_pmc_write(AT91_PMC_PCKR(clk->id), parent->id);
 
        spin_unlock_irqrestore(&clk_lock, flags);
        return 0;
@@ -378,11 +409,17 @@ static void __init init_programmable_clock(struct clk *clk)
 {
        struct clk      *parent;
        u32             pckr;
+       unsigned int    css_mask;
+
+       if (cpu_has_alt_prescaler())
+               css_mask = AT91_PMC_ALT_PCKR_CSS;
+       else
+               css_mask = AT91_PMC_CSS;
 
-       pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
-       parent = at91_css_to_clk(pckr & AT91_PMC_CSS);
+       pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
+       parent = at91_css_to_clk(pckr & css_mask);
        clk->parent = parent;
-       clk->rate_hz = parent->rate_hz / (1 << ((pckr & AT91_PMC_PRES) >> 2));
+       clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr);
 }
 
 #endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
@@ -396,19 +433,24 @@ static int at91_clk_show(struct seq_file *s, void *unused)
        u32             scsr, pcsr, uckr = 0, sr;
        struct clk      *clk;
 
-       seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
-       seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR));
-       seq_printf(s, "MOR  = %8x\n", at91_sys_read(AT91_CKGR_MOR));
-       seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
-       seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
+       scsr = at91_pmc_read(AT91_PMC_SCSR);
+       pcsr = at91_pmc_read(AT91_PMC_PCSR);
+       sr = at91_pmc_read(AT91_PMC_SR);
+       seq_printf(s, "SCSR = %8x\n", scsr);
+       seq_printf(s, "PCSR = %8x\n", pcsr);
+       seq_printf(s, "MOR  = %8x\n", at91_pmc_read(AT91_CKGR_MOR));
+       seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR));
+       seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR));
        if (cpu_has_pllb())
-               seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
-       if (cpu_has_utmi())
-               seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR));
-       seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
+               seq_printf(s, "PLLB = %8x\n", at91_pmc_read(AT91_CKGR_PLLBR));
+       if (cpu_has_utmi()) {
+               uckr = at91_pmc_read(AT91_CKGR_UCKR);
+               seq_printf(s, "UCKR = %8x\n", uckr);
+       }
+       seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR));
        if (cpu_has_upll())
-               seq_printf(s, "USB  = %8x\n", at91_sys_read(AT91_PMC_USB));
-       seq_printf(s, "SR   = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
+               seq_printf(s, "USB  = %8x\n", at91_pmc_read(AT91_PMC_USB));
+       seq_printf(s, "SR   = %8x\n", sr);
 
        seq_printf(s, "\n");
 
@@ -596,16 +638,14 @@ static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
        if (cpu_is_at91rm9200()) {
                uhpck.pmc_mask = AT91RM9200_PMC_UHP;
                udpck.pmc_mask = AT91RM9200_PMC_UDP;
-               at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
+               at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
        } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
                   cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
                   cpu_is_at91sam9g10()) {
                uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
                udpck.pmc_mask = AT91SAM926x_PMC_UDP;
-       } else if (cpu_is_at91cap9()) {
-               uhpck.pmc_mask = AT91CAP9_PMC_UHP;
        }
-       at91_sys_write(AT91_CKGR_PLLBR, 0);
+       at91_pmc_write(AT91_CKGR_PLLBR, 0);
 
        udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
        uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
@@ -622,13 +662,13 @@ static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
        /* Setup divider by 10 to reach 48 MHz */
        usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
 
-       at91_sys_write(AT91_PMC_USB, usbr);
+       at91_pmc_write(AT91_PMC_USB, usbr);
 
        /* Now set uhpck values */
        uhpck.parent = &utmi_clk;
        uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
        uhpck.rate_hz = utmi_clk.rate_hz;
-       uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
+       uhpck.rate_hz /= 1 + ((at91_pmc_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
 }
 
 int __init at91_clock_init(unsigned long main_clock)
@@ -637,6 +677,10 @@ int __init at91_clock_init(unsigned long main_clock)
        int i;
        int pll_overclock = false;
 
+       at91_pmc_base = ioremap(AT91_PMC, 256);
+       if (!at91_pmc_base)
+               panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC);
+
        /*
         * When the bootloader initialized the main oscillator correctly,
         * there's no problem using the cycle counter.  But if it didn't,
@@ -645,14 +689,14 @@ int __init at91_clock_init(unsigned long main_clock)
         */
        if (!main_clock) {
                do {
-                       tmp = at91_sys_read(AT91_CKGR_MCFR);
+                       tmp = at91_pmc_read(AT91_CKGR_MCFR);
                } while (!(tmp & AT91_PMC_MAINRDY));
                main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
        }
        main_clk.rate_hz = main_clock;
 
        /* report if PLLA is more than mildly overclocked */
-       plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
+       plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR));
        if (cpu_has_300M_plla()) {
                if (plla.rate_hz > 300000000)
                        pll_overclock = true;
@@ -666,8 +710,8 @@ int __init at91_clock_init(unsigned long main_clock)
        if (pll_overclock)
                pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
 
-       if (cpu_is_at91sam9g45()) {
-               mckr = at91_sys_read(AT91_PMC_MCKR);
+       if (cpu_has_plladiv2()) {
+               mckr = at91_pmc_read(AT91_PMC_MCKR);
                plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12));      /* plla divisor by 2 */
        }
 
@@ -688,6 +732,10 @@ int __init at91_clock_init(unsigned long main_clock)
                 * (obtain the USB High Speed 480 MHz when input is 12 MHz)
                 */
                utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
+
+               /* UTMI bias and PLL are managed at the same time */
+               if (cpu_has_upll())
+                       utmi_clk.pmc_mask |= AT91_PMC_BIASEN;
        }
 
        /*
@@ -703,10 +751,10 @@ int __init at91_clock_init(unsigned long main_clock)
         * MCK and CPU derive from one of those primary clocks.
         * For now, assume this parentage won't change.
         */
-       mckr = at91_sys_read(AT91_PMC_MCKR);
+       mckr = at91_pmc_read(AT91_PMC_MCKR);
        mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
        freq = mck.parent->rate_hz;
-       freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2));                           /* prescale */
+       freq /= pmc_prescaler_divider(mckr);                                    /* prescale */
        if (cpu_is_at91rm9200()) {
                mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8));       /* mdiv */
        } else if (cpu_is_at91sam9g20()) {
@@ -714,13 +762,19 @@ int __init at91_clock_init(unsigned long main_clock)
                        freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq;    /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
                if (mckr & AT91_PMC_PDIV)
                        freq /= 2;              /* processor clock division */
-       } else if (cpu_is_at91sam9g45()) {
+       } else if (cpu_has_mdiv3()) {
                mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
                        freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
        } else {
                mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));              /* mdiv */
        }
 
+       if (cpu_has_alt_prescaler()) {
+               /* Programmable clocks can use MCK */
+               mck.type |= CLK_TYPE_PRIMARY;
+               mck.id = 4;
+       }
+
        /* Register the PMC's standard clocks */
        for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
                at91_clk_add(standard_pmc_clocks[i]);
@@ -770,9 +824,15 @@ static int __init at91_clock_reset(void)
                pr_debug("Clocks: disable unused %s\n", clk->name);
        }
 
-       at91_sys_write(AT91_PMC_PCDR, pcdr);
-       at91_sys_write(AT91_PMC_SCDR, scdr);
+       at91_pmc_write(AT91_PMC_PCDR, pcdr);
+       at91_pmc_write(AT91_PMC_SCDR, scdr);
 
        return 0;
 }
 late_initcall(at91_clock_reset);
+
+void at91sam9_idle(void)
+{
+       at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
+       cpu_do_idle();
+}
index a851e6c984218d14533fd5157c7e58fc76c5fc81..555d956b3a574b3a4d96be46c199c087d991080d 100644 (file)
@@ -39,20 +39,15 @@ static int at91_enter_idle(struct cpuidle_device *dev,
 {
        struct timeval before, after;
        int idle_time;
-       u32 saved_lpr;
 
        local_irq_disable();
        do_gettimeofday(&before);
        if (index == 0)
                /* Wait for interrupt state */
                cpu_do_idle();
-       else if (index == 1) {
-               asm("b 1f; .align 5; 1:");
-               asm("mcr p15, 0, r0, c7, c10, 4");      /* drain write buffer */
-               saved_lpr = sdram_selfrefresh_enable();
-               cpu_do_idle();
-               sdram_selfrefresh_disable(saved_lpr);
-       }
+       else if (index == 1)
+               at91_standby();
+
        do_gettimeofday(&after);
        local_irq_enable();
        idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
index 594133451c0c88498d50d30b223f22341c132cb2..4cad85e574701904b1b40b4584722896097c074b 100644 (file)
@@ -28,6 +28,7 @@ extern void __init at91_aic_init(unsigned int priority[]);
 
  /* Timer */
 struct sys_timer;
+extern void at91rm9200_ioremap_st(u32 addr);
 extern struct sys_timer at91rm9200_timer;
 extern void at91sam926x_ioremap_pit(u32 addr);
 extern struct sys_timer at91sam926x_timer;
@@ -45,7 +46,6 @@ extern void __init at91sam9261_set_console_clock(int id);
 extern void __init at91sam9263_set_console_clock(int id);
 extern void __init at91sam9rl_set_console_clock(int id);
 extern void __init at91sam9g45_set_console_clock(int id);
-extern void __init at91cap9_set_console_clock(int id);
 #ifdef CONFIG_AT91_PMC_UNIT
 extern int __init at91_clock_init(unsigned long main_clock);
 #else
@@ -57,6 +57,9 @@ struct device;
 extern void at91_irq_suspend(void);
 extern void at91_irq_resume(void);
 
+/* idle */
+extern void at91sam9_idle(void);
+
 /* reset */
 extern void at91_ioremap_rstc(u32 base_addr);
 extern void at91sam9_alt_restart(char, const char *);
@@ -65,6 +68,12 @@ extern void at91sam9g45_restart(char, const char *);
 /* shutdown */
 extern void at91_ioremap_shdwc(u32 base_addr);
 
+/* Matrix */
+extern void at91_ioremap_matrix(u32 base_addr);
+
+/* Ram Controler */
+extern void at91_ioremap_ramc(int id, u32 addr, u32 size);
+
  /* GPIO */
 #define AT91RM9200_PQFP                3       /* AT91RM9200 PQFP package has 3 banks */
 #define AT91RM9200_BGA         4       /* AT91RM9200 BGA package has 4 banks */
diff --git a/arch/arm/mach-at91/include/mach/at91_matrix.h b/arch/arm/mach-at91/include/mach/at91_matrix.h
new file mode 100644 (file)
index 0000000..02fae9d
--- /dev/null
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Under GPLv2
+ */
+
+#ifndef __MACH_AT91_MATRIX_H__
+#define __MACH_AT91_MATRIX_H__
+
+#ifndef __ASSEMBLY__
+extern void __iomem *at91_matrix_base;
+
+#define at91_matrix_read(field) \
+       __raw_readl(at91_matrix_base + field)
+
+#define at91_matrix_write(field, value) \
+       __raw_writel(value, at91_matrix_base + field);
+
+#else
+.extern at91_matrix_base
+#endif
+
+#endif /* __MACH_AT91_MATRIX_H__ */
index e46f93e34aab4666b14932a9c6c451847b2c8b54..36604782a78f0e52d4bed0d6af21c787dacf418f 100644 (file)
 #ifndef AT91_PMC_H
 #define AT91_PMC_H
 
-#define        AT91_PMC_SCER           (AT91_PMC + 0x00)       /* System Clock Enable Register */
-#define        AT91_PMC_SCDR           (AT91_PMC + 0x04)       /* System Clock Disable Register */
+#ifndef __ASSEMBLY__
+extern void __iomem *at91_pmc_base;
 
-#define        AT91_PMC_SCSR           (AT91_PMC + 0x08)       /* System Clock Status Register */
+#define at91_pmc_read(field) \
+       __raw_readl(at91_pmc_base + field)
+
+#define at91_pmc_write(field, value) \
+       __raw_writel(value, at91_pmc_base + field)
+#else
+.extern at91_aic_base
+#endif
+
+#define        AT91_PMC_SCER           0x00                    /* System Clock Enable Register */
+#define        AT91_PMC_SCDR           0x04                    /* System Clock Disable Register */
+
+#define        AT91_PMC_SCSR           0x08                    /* System Clock Status Register */
 #define                AT91_PMC_PCK            (1 <<  0)               /* Processor Clock */
 #define                AT91RM9200_PMC_UDP      (1 <<  1)               /* USB Devcice Port Clock [AT91RM9200 only] */
 #define                AT91RM9200_PMC_MCKUDP   (1 <<  2)               /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
-#define                AT91CAP9_PMC_DDR        (1 <<  2)               /* DDR Clock [CAP9 revC & some SAM9 only] */
 #define                AT91RM9200_PMC_UHP      (1 <<  4)               /* USB Host Port Clock [AT91RM9200 only] */
 #define                AT91SAM926x_PMC_UHP     (1 <<  6)               /* USB Host Port Clock [AT91SAM926x only] */
-#define                AT91CAP9_PMC_UHP        (1 <<  6)               /* USB Host Port Clock [AT91CAP9 only] */
 #define                AT91SAM926x_PMC_UDP     (1 <<  7)               /* USB Devcice Port Clock [AT91SAM926x only] */
 #define                AT91_PMC_PCK0           (1 <<  8)               /* Programmable Clock 0 */
 #define                AT91_PMC_PCK1           (1 <<  9)               /* Programmable Clock 1 */
 #define                AT91_PMC_HCK0           (1 << 16)               /* AHB Clock (USB host) [AT91SAM9261 only] */
 #define                AT91_PMC_HCK1           (1 << 17)               /* AHB Clock (LCD) [AT91SAM9261 only] */
 
-#define        AT91_PMC_PCER           (AT91_PMC + 0x10)       /* Peripheral Clock Enable Register */
-#define        AT91_PMC_PCDR           (AT91_PMC + 0x14)       /* Peripheral Clock Disable Register */
-#define        AT91_PMC_PCSR           (AT91_PMC + 0x18)       /* Peripheral Clock Status Register */
+#define        AT91_PMC_PCER           0x10                    /* Peripheral Clock Enable Register */
+#define        AT91_PMC_PCDR           0x14                    /* Peripheral Clock Disable Register */
+#define        AT91_PMC_PCSR           0x18                    /* Peripheral Clock Status Register */
 
-#define        AT91_CKGR_UCKR          (AT91_PMC + 0x1C)       /* UTMI Clock Register [some SAM9, CAP9] */
+#define        AT91_CKGR_UCKR          0x1C                    /* UTMI Clock Register [some SAM9] */
 #define                AT91_PMC_UPLLEN         (1   << 16)             /* UTMI PLL Enable */
 #define                AT91_PMC_UPLLCOUNT      (0xf << 20)             /* UTMI PLL Start-up Time */
 #define                AT91_PMC_BIASEN         (1   << 24)             /* UTMI BIAS Enable */
 #define                AT91_PMC_BIASCOUNT      (0xf << 28)             /* UTMI BIAS Start-up Time */
 
-#define        AT91_CKGR_MOR           (AT91_PMC + 0x20)       /* Main Oscillator Register [not on SAM9RL] */
-#define                AT91_PMC_MOSCEN         (1    << 0)             /* Main Oscillator Enable */
-#define                AT91_PMC_OSCBYPASS      (1    << 1)             /* Oscillator Bypass [SAM9x, CAP9] */
-#define                AT91_PMC_OSCOUNT        (0xff << 8)             /* Main Oscillator Start-up Time */
+#define        AT91_CKGR_MOR           0x20                    /* Main Oscillator Register [not on SAM9RL] */
+#define                AT91_PMC_MOSCEN         (1    <<  0)            /* Main Oscillator Enable */
+#define                AT91_PMC_OSCBYPASS      (1    <<  1)            /* Oscillator Bypass */
+#define                AT91_PMC_MOSCRCEN       (1    <<  3)            /* Main On-Chip RC Oscillator Enable [some SAM9] */
+#define                AT91_PMC_OSCOUNT        (0xff <<  8)            /* Main Oscillator Start-up Time */
+#define                AT91_PMC_KEY            (0x37 << 16)            /* MOR Writing Key */
+#define                AT91_PMC_MOSCSEL        (1    << 24)            /* Main Oscillator Selection [some SAM9] */
+#define                AT91_PMC_CFDEN          (1    << 25)            /* Clock Failure Detector Enable [some SAM9] */
 
-#define        AT91_CKGR_MCFR          (AT91_PMC + 0x24)       /* Main Clock Frequency Register */
+#define        AT91_CKGR_MCFR          0x24                    /* Main Clock Frequency Register */
 #define                AT91_PMC_MAINF          (0xffff <<  0)          /* Main Clock Frequency */
 #define                AT91_PMC_MAINRDY        (1      << 16)          /* Main Clock Ready */
 
-#define        AT91_CKGR_PLLAR         (AT91_PMC + 0x28)       /* PLL A Register */
-#define        AT91_CKGR_PLLBR         (AT91_PMC + 0x2c)       /* PLL B Register */
+#define        AT91_CKGR_PLLAR         0x28                    /* PLL A Register */
+#define        AT91_CKGR_PLLBR         0x2c                    /* PLL B Register */
 #define                AT91_PMC_DIV            (0xff  <<  0)           /* Divider */
 #define                AT91_PMC_PLLCOUNT       (0x3f  <<  8)           /* PLL Counter */
 #define                AT91_PMC_OUT            (3     << 14)           /* PLL Clock Frequency Range */
 #define                        AT91_PMC_USBDIV_4               (2 << 28)
 #define                AT91_PMC_USB96M         (1     << 28)           /* Divider by 2 Enable (PLLB only) */
 
-#define        AT91_PMC_MCKR           (AT91_PMC + 0x30)       /* Master Clock Register */
+#define        AT91_PMC_MCKR           0x30                    /* Master Clock Register */
 #define                AT91_PMC_CSS            (3 <<  0)               /* Master Clock Selection */
 #define                        AT91_PMC_CSS_SLOW               (0 << 0)
 #define                        AT91_PMC_CSS_MAIN               (1 << 0)
 #define                        AT91_PMC_CSS_PLLA               (2 << 0)
 #define                        AT91_PMC_CSS_PLLB               (3 << 0)
 #define                        AT91_PMC_CSS_UPLL               (3 << 0)        /* [some SAM9 only] */
-#define                AT91_PMC_PRES           (7 <<  2)               /* Master Clock Prescaler */
-#define                        AT91_PMC_PRES_1                 (0 << 2)
-#define                        AT91_PMC_PRES_2                 (1 << 2)
-#define                        AT91_PMC_PRES_4                 (2 << 2)
-#define                        AT91_PMC_PRES_8                 (3 << 2)
-#define                        AT91_PMC_PRES_16                (4 << 2)
-#define                        AT91_PMC_PRES_32                (5 << 2)
-#define                        AT91_PMC_PRES_64                (6 << 2)
+#define                PMC_PRES_OFFSET         2
+#define                AT91_PMC_PRES           (7 <<  PMC_PRES_OFFSET)         /* Master Clock Prescaler */
+#define                        AT91_PMC_PRES_1                 (0 << PMC_PRES_OFFSET)
+#define                        AT91_PMC_PRES_2                 (1 << PMC_PRES_OFFSET)
+#define                        AT91_PMC_PRES_4                 (2 << PMC_PRES_OFFSET)
+#define                        AT91_PMC_PRES_8                 (3 << PMC_PRES_OFFSET)
+#define                        AT91_PMC_PRES_16                (4 << PMC_PRES_OFFSET)
+#define                        AT91_PMC_PRES_32                (5 << PMC_PRES_OFFSET)
+#define                        AT91_PMC_PRES_64                (6 << PMC_PRES_OFFSET)
+#define                PMC_ALT_PRES_OFFSET     4
+#define                AT91_PMC_ALT_PRES       (7 <<  PMC_ALT_PRES_OFFSET)             /* Master Clock Prescaler [alternate location] */
+#define                        AT91_PMC_ALT_PRES_1             (0 << PMC_ALT_PRES_OFFSET)
+#define                        AT91_PMC_ALT_PRES_2             (1 << PMC_ALT_PRES_OFFSET)
+#define                        AT91_PMC_ALT_PRES_4             (2 << PMC_ALT_PRES_OFFSET)
+#define                        AT91_PMC_ALT_PRES_8             (3 << PMC_ALT_PRES_OFFSET)
+#define                        AT91_PMC_ALT_PRES_16            (4 << PMC_ALT_PRES_OFFSET)
+#define                        AT91_PMC_ALT_PRES_32            (5 << PMC_ALT_PRES_OFFSET)
+#define                        AT91_PMC_ALT_PRES_64            (6 << PMC_ALT_PRES_OFFSET)
 #define                AT91_PMC_MDIV           (3 <<  8)               /* Master Clock Division */
 #define                        AT91RM9200_PMC_MDIV_1           (0 << 8)        /* [AT91RM9200 only] */
 #define                        AT91RM9200_PMC_MDIV_2           (1 << 8)
 #define                        AT91RM9200_PMC_MDIV_3           (2 << 8)
 #define                        AT91RM9200_PMC_MDIV_4           (3 << 8)
-#define                        AT91SAM9_PMC_MDIV_1             (0 << 8)        /* [SAM9,CAP9 only] */
+#define                        AT91SAM9_PMC_MDIV_1             (0 << 8)        /* [SAM9 only] */
 #define                        AT91SAM9_PMC_MDIV_2             (1 << 8)
 #define                        AT91SAM9_PMC_MDIV_4             (2 << 8)
 #define                        AT91SAM9_PMC_MDIV_6             (3 << 8)        /* [some SAM9 only] */
 #define                        AT91_PMC_PLLADIV2_OFF           (0 << 12)
 #define                        AT91_PMC_PLLADIV2_ON            (1 << 12)
 
-#define        AT91_PMC_USB            (AT91_PMC + 0x38)       /* USB Clock Register [some SAM9 only] */
+#define        AT91_PMC_USB            0x38                    /* USB Clock Register [some SAM9 only] */
 #define                AT91_PMC_USBS           (0x1 <<  0)             /* USB OHCI Input clock selection */
 #define                        AT91_PMC_USBS_PLLA              (0 << 0)
 #define                        AT91_PMC_USBS_UPLL              (1 << 0)
 #define                AT91_PMC_OHCIUSBDIV     (0xF <<  8)             /* Divider for USB OHCI Clock */
 
-#define        AT91_PMC_PCKR(n)        (AT91_PMC + 0x40 + ((n) * 4))   /* Programmable Clock 0-N Registers */
+#define        AT91_PMC_SMD            0x3c                    /* Soft Modem Clock Register [some SAM9 only] */
+#define                AT91_PMC_SMDS           (0x1  <<  0)            /* SMD input clock selection */
+#define                AT91_PMC_SMD_DIV        (0x1f <<  8)            /* SMD input clock divider */
+#define                AT91_PMC_SMDDIV(n)      (((n) <<  8) & AT91_PMC_SMD_DIV)
+
+#define        AT91_PMC_PCKR(n)        (0x40 + ((n) * 4))      /* Programmable Clock 0-N Registers */
+#define                AT91_PMC_ALT_PCKR_CSS   (0x7 <<  0)             /* Programmable Clock Source Selection [alternate length] */
+#define                        AT91_PMC_CSS_MASTER             (4 << 0)        /* [some SAM9 only] */
 #define                AT91_PMC_CSSMCK         (0x1 <<  8)             /* CSS or Master Clock Selection */
 #define                        AT91_PMC_CSSMCK_CSS             (0 << 8)
 #define                        AT91_PMC_CSSMCK_MCK             (1 << 8)
 
-#define        AT91_PMC_IER            (AT91_PMC + 0x60)       /* Interrupt Enable Register */
-#define        AT91_PMC_IDR            (AT91_PMC + 0x64)       /* Interrupt Disable Register */
-#define        AT91_PMC_SR             (AT91_PMC + 0x68)       /* Status Register */
+#define        AT91_PMC_IER            0x60                    /* Interrupt Enable Register */
+#define        AT91_PMC_IDR            0x64                    /* Interrupt Disable Register */
+#define        AT91_PMC_SR             0x68                    /* Status Register */
 #define                AT91_PMC_MOSCS          (1 <<  0)               /* MOSCS Flag */
 #define                AT91_PMC_LOCKA          (1 <<  1)               /* PLLA Lock */
 #define                AT91_PMC_LOCKB          (1 <<  2)               /* PLLB Lock */
 #define                AT91_PMC_MCKRDY         (1 <<  3)               /* Master Clock */
-#define                AT91_PMC_LOCKU          (1 <<  6)               /* UPLL Lock [some SAM9, AT91CAP9 only] */
-#define                AT91_PMC_OSCSEL         (1 <<  7)               /* Slow Clock Oscillator [AT91CAP9 revC only] */
+#define                AT91_PMC_LOCKU          (1 <<  6)               /* UPLL Lock [some SAM9] */
 #define                AT91_PMC_PCK0RDY        (1 <<  8)               /* Programmable Clock 0 */
 #define                AT91_PMC_PCK1RDY        (1 <<  9)               /* Programmable Clock 1 */
 #define                AT91_PMC_PCK2RDY        (1 << 10)               /* Programmable Clock 2 */
 #define                AT91_PMC_PCK3RDY        (1 << 11)               /* Programmable Clock 3 */
-#define        AT91_PMC_IMR            (AT91_PMC + 0x6c)       /* Interrupt Mask Register */
+#define                AT91_PMC_MOSCSELS       (1 << 16)               /* Main Oscillator Selection [some SAM9] */
+#define                AT91_PMC_MOSCRCS        (1 << 17)               /* Main On-Chip RC [some SAM9] */
+#define                AT91_PMC_CFDEV          (1 << 18)               /* Clock Failure Detector Event [some SAM9] */
+#define        AT91_PMC_IMR            0x6c                    /* Interrupt Mask Register */
+
+#define AT91_PMC_PROT          0xe4                    /* Write Protect Mode Register [some SAM9] */
+#define                AT91_PMC_WPEN           (0x1  <<  0)            /* Write Protect Enable */
+#define                AT91_PMC_WPKEY          (0xffffff << 8)         /* Write Protect Key */
+#define                AT91_PMC_PROTKEY        (0x504d43 << 8)         /* Activation Code */
 
-#define AT91_PMC_PROT          (AT91_PMC + 0xe4)       /* Protect Register [AT91CAP9 revC only] */
-#define                AT91_PMC_PROTKEY        0x504d4301      /* Activation Code */
+#define AT91_PMC_WPSR          0xe8                    /* Write Protect Status Register [some SAM9] */
+#define                AT91_PMC_WPVS           (0x1  <<  0)            /* Write Protect Violation Status */
+#define                AT91_PMC_WPVSRC         (0xffff  <<  8)         /* Write Protect Violation Source */
 
-#define AT91_PMC_VER           (AT91_PMC + 0xfc)       /* PMC Module Version [AT91CAP9 only] */
+#define AT91_PMC_PCR           0x10c                   /* Peripheral Control Register [some SAM9] */
+#define                AT91_PMC_PCR_PID        (0x3f  <<  0)           /* Peripheral ID */
+#define                AT91_PMC_PCR_CMD        (0x1  <<  12)           /* Command */
+#define                AT91_PMC_PCR_DIV        (0x3  <<  16)           /* Divisor Value */
+#define                AT91_PMC_PCRDIV(n)      (((n) <<  16) & AT91_PMC_PCR_DIV)
+#define                AT91_PMC_PCR_EN         (0x1  <<  28)           /* Enable */
 
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91_ramc.h b/arch/arm/mach-at91/include/mach/at91_ramc.h
new file mode 100644 (file)
index 0000000..d8aeb27
--- /dev/null
@@ -0,0 +1,32 @@
+/*
+ * Header file for the Atmel RAM Controller
+ *
+ * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Under GPLv2 only
+ */
+
+#ifndef __AT91_RAMC_H__
+#define __AT91_RAMC_H__
+
+#ifndef __ASSEMBLY__
+extern void __iomem *at91_ramc_base[];
+
+#define at91_ramc_read(id, field) \
+       __raw_readl(at91_ramc_base[id] + field)
+
+#define at91_ramc_write(id, field, value) \
+       __raw_writel(value, at91_ramc_base[id] + field)
+#else
+.extern at91_ramc_base
+#endif
+
+#define AT91_MEMCTRL_MC                0
+#define AT91_MEMCTRL_SDRAMC    1
+#define AT91_MEMCTRL_DDRSDR    2
+
+#include <mach/at91rm9200_sdramc.h>
+#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91sam9_sdramc.h>
+
+#endif /* __AT91_RAMC_H__ */
index 8847173e4101b1977c78752eafc40560a0bc6046..969aac27109fbabe5bd991f2990cae6a4e4666a2 100644 (file)
 #ifndef AT91_ST_H
 #define AT91_ST_H
 
-#define        AT91_ST_CR              (AT91_ST + 0x00)        /* Control Register */
+#ifndef __ASSEMBLY__
+extern void __iomem *at91_st_base;
+
+#define at91_st_read(field) \
+       __raw_readl(at91_st_base + field)
+
+#define at91_st_write(field, value) \
+       __raw_writel(value, at91_st_base + field);
+#else
+.extern at91_st_base
+#endif
+
+#define        AT91_ST_CR              0x00                    /* Control Register */
 #define        AT91_ST_WDRST           (1 << 0)                /* Watchdog Timer Restart */
 
-#define        AT91_ST_PIMR            (AT91_ST + 0x04)        /* Period Interval Mode Register */
+#define        AT91_ST_PIMR            0x04                    /* Period Interval Mode Register */
 #define                AT91_ST_PIV             (0xffff <<  0)          /* Period Interval Value */
 
-#define        AT91_ST_WDMR            (AT91_ST + 0x08)        /* Watchdog Mode Register */
+#define        AT91_ST_WDMR            0x08                    /* Watchdog Mode Register */
 #define                AT91_ST_WDV             (0xffff <<  0)          /* Watchdog Counter Value */
 #define                AT91_ST_RSTEN           (1      << 16)          /* Reset Enable */
 #define                AT91_ST_EXTEN           (1      << 17)          /* External Signal Assertion Enable */
 
-#define        AT91_ST_RTMR            (AT91_ST + 0x0c)        /* Real-time Mode Register */
+#define        AT91_ST_RTMR            0x0c                    /* Real-time Mode Register */
 #define                AT91_ST_RTPRES          (0xffff <<  0)          /* Real-time Prescalar Value */
 
-#define        AT91_ST_SR              (AT91_ST + 0x10)        /* Status Register */
+#define        AT91_ST_SR              0x10                    /* Status Register */
 #define                AT91_ST_PITS            (1 << 0)                /* Period Interval Timer Status */
 #define                AT91_ST_WDOVF           (1 << 1)                /* Watchdog Overflow */
 #define                AT91_ST_RTTINC          (1 << 2)                /* Real-time Timer Increment */
 #define                AT91_ST_ALMS            (1 << 3)                /* Alarm Status */
 
-#define        AT91_ST_IER             (AT91_ST + 0x14)        /* Interrupt Enable Register */
-#define        AT91_ST_IDR             (AT91_ST + 0x18)        /* Interrupt Disable Register */
-#define        AT91_ST_IMR             (AT91_ST + 0x1c)        /* Interrupt Mask Register */
+#define        AT91_ST_IER             0x14                    /* Interrupt Enable Register */
+#define        AT91_ST_IDR             0x18                    /* Interrupt Disable Register */
+#define        AT91_ST_IMR             0x1c                    /* Interrupt Mask Register */
 
-#define        AT91_ST_RTAR            (AT91_ST + 0x20)        /* Real-time Alarm Register */
+#define        AT91_ST_RTAR            0x20                    /* Real-time Alarm Register */
 #define                AT91_ST_ALMV            (0xfffff << 0)          /* Alarm Value */
 
-#define        AT91_ST_CRTR            (AT91_ST + 0x24)        /* Current Real-time Register */
+#define        AT91_ST_CRTR            0x24                    /* Current Real-time Register */
 #define                AT91_ST_CRTV            (0xfffff << 0)          /* Current Real-Time Value */
 
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h
deleted file mode 100644 (file)
index 61d9529..0000000
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91cap9.h
- *
- *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
- *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
- *  Copyright (C) 2007 Atmel Corporation.
- *
- * Common definitions.
- * Based on AT91CAP9 datasheet revision B (Preliminary).
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91CAP9_H
-#define AT91CAP9_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91CAP9_ID_PIOABCD    2       /* Parallel IO Controller A, B, C and D */
-#define AT91CAP9_ID_MPB0       3       /* MP Block Peripheral 0 */
-#define AT91CAP9_ID_MPB1       4       /* MP Block Peripheral 1 */
-#define AT91CAP9_ID_MPB2       5       /* MP Block Peripheral 2 */
-#define AT91CAP9_ID_MPB3       6       /* MP Block Peripheral 3 */
-#define AT91CAP9_ID_MPB4       7       /* MP Block Peripheral 4 */
-#define AT91CAP9_ID_US0                8       /* USART 0 */
-#define AT91CAP9_ID_US1                9       /* USART 1 */
-#define AT91CAP9_ID_US2                10      /* USART 2 */
-#define AT91CAP9_ID_MCI0       11      /* Multimedia Card Interface 0 */
-#define AT91CAP9_ID_MCI1       12      /* Multimedia Card Interface 1 */
-#define AT91CAP9_ID_CAN                13      /* CAN */
-#define AT91CAP9_ID_TWI                14      /* Two-Wire Interface */
-#define AT91CAP9_ID_SPI0       15      /* Serial Peripheral Interface 0 */
-#define AT91CAP9_ID_SPI1       16      /* Serial Peripheral Interface 0 */
-#define AT91CAP9_ID_SSC0       17      /* Serial Synchronous Controller 0 */
-#define AT91CAP9_ID_SSC1       18      /* Serial Synchronous Controller 1 */
-#define AT91CAP9_ID_AC97C      19      /* AC97 Controller */
-#define AT91CAP9_ID_TCB                20      /* Timer Counter 0, 1 and 2 */
-#define AT91CAP9_ID_PWMC       21      /* Pulse Width Modulation Controller */
-#define AT91CAP9_ID_EMAC       22      /* Ethernet */
-#define AT91CAP9_ID_AESTDES    23      /* Advanced Encryption Standard, Triple DES */
-#define AT91CAP9_ID_ADC                24      /* Analog-to-Digital Converter */
-#define AT91CAP9_ID_ISI                25      /* Image Sensor Interface */
-#define AT91CAP9_ID_LCDC       26      /* LCD Controller */
-#define AT91CAP9_ID_DMA                27      /* DMA Controller */
-#define AT91CAP9_ID_UDPHS      28      /* USB High Speed Device Port */
-#define AT91CAP9_ID_UHP                29      /* USB Host Port */
-#define AT91CAP9_ID_IRQ0       30      /* Advanced Interrupt Controller (IRQ0) */
-#define AT91CAP9_ID_IRQ1       31      /* Advanced Interrupt Controller (IRQ1) */
-
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91CAP9_BASE_UDPHS            0xfff78000
-#define AT91CAP9_BASE_TCB0             0xfff7c000
-#define AT91CAP9_BASE_TC0              0xfff7c000
-#define AT91CAP9_BASE_TC1              0xfff7c040
-#define AT91CAP9_BASE_TC2              0xfff7c080
-#define AT91CAP9_BASE_MCI0             0xfff80000
-#define AT91CAP9_BASE_MCI1             0xfff84000
-#define AT91CAP9_BASE_TWI              0xfff88000
-#define AT91CAP9_BASE_US0              0xfff8c000
-#define AT91CAP9_BASE_US1              0xfff90000
-#define AT91CAP9_BASE_US2              0xfff94000
-#define AT91CAP9_BASE_SSC0             0xfff98000
-#define AT91CAP9_BASE_SSC1             0xfff9c000
-#define AT91CAP9_BASE_AC97C            0xfffa0000
-#define AT91CAP9_BASE_SPI0             0xfffa4000
-#define AT91CAP9_BASE_SPI1             0xfffa8000
-#define AT91CAP9_BASE_CAN              0xfffac000
-#define AT91CAP9_BASE_PWMC             0xfffb8000
-#define AT91CAP9_BASE_EMAC             0xfffbc000
-#define AT91CAP9_BASE_ADC              0xfffc0000
-#define AT91CAP9_BASE_ISI              0xfffc4000
-
-/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_BCRAMC    (0xffffe400 - AT91_BASE_SYS)
-#define AT91_DDRSDRC0  (0xffffe600 - AT91_BASE_SYS)
-#define AT91_MATRIX    (0xffffea00 - AT91_BASE_SYS)
-#define AT91_PMC       (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_GPBR      (cpu_is_at91cap9_revB() ?       \
-                       (0xfffffd50 - AT91_BASE_SYS) :  \
-                       (0xfffffd60 - AT91_BASE_SYS))
-
-#define AT91CAP9_BASE_ECC      0xffffe200
-#define AT91CAP9_BASE_DMA      0xffffec00
-#define AT91CAP9_BASE_SMC      0xffffe800
-#define AT91CAP9_BASE_DBGU     AT91_BASE_DBGU1
-#define AT91CAP9_BASE_PIOA     0xfffff200
-#define AT91CAP9_BASE_PIOB     0xfffff400
-#define AT91CAP9_BASE_PIOC     0xfffff600
-#define AT91CAP9_BASE_PIOD     0xfffff800
-#define AT91CAP9_BASE_RSTC     0xfffffd00
-#define AT91CAP9_BASE_SHDWC    0xfffffd10
-#define AT91CAP9_BASE_RTT      0xfffffd20
-#define AT91CAP9_BASE_PIT      0xfffffd30
-#define AT91CAP9_BASE_WDT      0xfffffd40
-
-#define AT91_USART0    AT91CAP9_BASE_US0
-#define AT91_USART1    AT91CAP9_BASE_US1
-#define AT91_USART2    AT91CAP9_BASE_US2
-
-
-/*
- * Internal Memory.
- */
-#define AT91CAP9_SRAM_BASE     0x00100000      /* Internal SRAM base address */
-#define AT91CAP9_SRAM_SIZE     (32 * SZ_1K)    /* Internal SRAM size (32Kb) */
-
-#define AT91CAP9_ROM_BASE      0x00400000      /* Internal ROM base address */
-#define AT91CAP9_ROM_SIZE      (32 * SZ_1K)    /* Internal ROM size (32Kb) */
-
-#define AT91CAP9_LCDC_BASE     0x00500000      /* LCD Controller */
-#define AT91CAP9_UDPHS_FIFO    0x00600000      /* USB High Speed Device Port */
-#define AT91CAP9_UHP_BASE      0x00700000      /* USB Host controller */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91cap9_matrix.h b/arch/arm/mach-at91/include/mach/at91cap9_matrix.h
deleted file mode 100644 (file)
index 4b9d4af..0000000
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91cap9_matrix.h
- *
- *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
- *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
- *  Copyright (C) 2006 Atmel Corporation.
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91CAP9 datasheet revision B (Preliminary).
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91CAP9_MATRIX_H
-#define AT91CAP9_MATRIX_H
-
-#define AT91_MATRIX_MCFG0      (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1      (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2      (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3      (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4      (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5      (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
-#define AT91_MATRIX_MCFG6      (AT91_MATRIX + 0x18)    /* Master Configuration Register 6 */
-#define AT91_MATRIX_MCFG7      (AT91_MATRIX + 0x1C)    /* Master Configuration Register 7 */
-#define AT91_MATRIX_MCFG8      (AT91_MATRIX + 0x20)    /* Master Configuration Register 8 */
-#define AT91_MATRIX_MCFG9      (AT91_MATRIX + 0x24)    /* Master Configuration Register 9 */
-#define AT91_MATRIX_MCFG10     (AT91_MATRIX + 0x28)    /* Master Configuration Register 10 */
-#define AT91_MATRIX_MCFG11     (AT91_MATRIX + 0x2C)    /* Master Configuration Register 11 */
-#define                AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
-#define                        AT91_MATRIX_ULBT_INFINITE       (0 << 0)
-#define                        AT91_MATRIX_ULBT_SINGLE         (1 << 0)
-#define                        AT91_MATRIX_ULBT_FOUR           (2 << 0)
-#define                        AT91_MATRIX_ULBT_EIGHT          (3 << 0)
-#define                        AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
-
-#define AT91_MATRIX_SCFG0      (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1      (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2      (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3      (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4      (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5      (AT91_MATRIX + 0x54)    /* Slave Configuration Register 5 */
-#define AT91_MATRIX_SCFG6      (AT91_MATRIX + 0x58)    /* Slave Configuration Register 6 */
-#define AT91_MATRIX_SCFG7      (AT91_MATRIX + 0x5C)    /* Slave Configuration Register 7 */
-#define AT91_MATRIX_SCFG8      (AT91_MATRIX + 0x60)    /* Slave Configuration Register 8 */
-#define AT91_MATRIX_SCFG9      (AT91_MATRIX + 0x64)    /* Slave Configuration Register 9 */
-#define                AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
-#define                AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
-#define                        AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
-#define                        AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
-#define                        AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
-#define                AT91_MATRIX_FIXED_DEFMSTR       (0xf  << 18)    /* Fixed Index of Default Master */
-#define                AT91_MATRIX_ARBT                (3    << 24)    /* Arbitration Type */
-#define                        AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
-#define                        AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
-
-#define AT91_MATRIX_PRAS0      (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRBS0      (AT91_MATRIX + 0x84)    /* Priority Register B for Slave 0 */
-#define AT91_MATRIX_PRAS1      (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRBS1      (AT91_MATRIX + 0x8C)    /* Priority Register B for Slave 1 */
-#define AT91_MATRIX_PRAS2      (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRBS2      (AT91_MATRIX + 0x94)    /* Priority Register B for Slave 2 */
-#define AT91_MATRIX_PRAS3      (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRBS3      (AT91_MATRIX + 0x9C)    /* Priority Register B for Slave 3 */
-#define AT91_MATRIX_PRAS4      (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRBS4      (AT91_MATRIX + 0xA4)    /* Priority Register B for Slave 4 */
-#define AT91_MATRIX_PRAS5      (AT91_MATRIX + 0xA8)    /*&n