Merge tag 'drivers2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
authorLinus Torvalds <torvalds@linux-foundation.org>
Wed, 28 Mar 2012 19:17:06 +0000 (12:17 -0700)
committerLinus Torvalds <torvalds@linux-foundation.org>
Wed, 28 Mar 2012 19:17:06 +0000 (12:17 -0700)
Pull "ARM: More SoC driver updates" from Olof Johansson:
 "This branch contains a handful of driver updates, mostly to the
  LPC32xx platform but also for Samsung EXYNOS and Davinci.

  It had a few context conflicts against patches already merged through
  fixes-non-critical.  We should have resolved this early during the
  development cycle by pulling them in as a dependency, instead I did it
  after the fact this time."

* tag 'drivers2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  gpio/samsung: use ioremap() for EXYNOS4 GPIOlib
  gpio/samsung: add support GPIOlib for EXYNOS5250
  ARM: EXYNOS: add support GPIO for EXYNOS5250
  ARM: LPC32xx: Ethernet support
  ARM: LPC32xx: USB Support
  ARM: davinci: dm644x evm: add support for VPBE display
  ARM: davinci: dm644x: add support for v4l2 video display
  ARM: EXYNOS: Hook up JPEG PD to generic PD infrastructure
  ARM: EXYNOS: Hook up G2D PD to generic PD infrastructure
  arm: lpc32xx: phy3250: add rtc & touch device
  ARM: LPC32xx: clock.c: Clock registration fixes
  ARM: LPC32xx: clock.c: jiffies wrapping
  ARM: LPC32xx: clock.c: Missing header file
  ARM: LPC32XX: Remove broken non-static declaration
  ARM: LPC32xx: clock.c: Fix mutex lock issues
  ARM: LPC32xx: clock.c: warning fix
  ARM: LPC32xx: Added lpc32xx_defconfig

1  2 
arch/arm/mach-exynos/common.c
arch/arm/mach-exynos/include/mach/map.h

index 97ca2592ce8383788d7aad4ba775f6f69d80d17e,85f0e24427a5243eaf094eaf9ecbfd729fcde786..d67e21e526e622b324a2685a7dc1fa93d080b425
  #include <asm/hardware/gic.h>
  #include <asm/mach/map.h>
  #include <asm/mach/irq.h>
 +#include <asm/cacheflush.h>
  
  #include <mach/regs-irq.h>
  #include <mach/regs-pmu.h>
  #include <mach/regs-gpio.h>
 +#include <mach/pmu.h>
  
  #include <plat/cpu.h>
  #include <plat/clock.h>
@@@ -47,8 -45,6 +47,8 @@@
  #include <plat/regs-serial.h>
  
  #include "common.h"
 +#define L2_AUX_VAL 0x7C470001
 +#define L2_AUX_MASK 0xC200ffff
  
  static const char name_exynos4210[] = "EXYNOS4210";
  static const char name_exynos4212[] = "EXYNOS4212";
@@@ -159,30 -155,10 +159,15 @@@ static struct map_desc exynos4_iodesc[
                .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
                .length         = SZ_4K,
                .type           = MT_DEVICE,
-       }, {
-               .virtual        = (unsigned long)S5P_VA_GPIO1,
-               .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO1),
-               .length         = SZ_4K,
-               .type           = MT_DEVICE,
-       }, {
-               .virtual        = (unsigned long)S5P_VA_GPIO2,
-               .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO2),
-               .length         = SZ_4K,
-               .type           = MT_DEVICE,
-       }, {
-               .virtual        = (unsigned long)S5P_VA_GPIO3,
-               .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO3),
-               .length         = SZ_256,
-               .type           = MT_DEVICE,
        }, {
                .virtual        = (unsigned long)S5P_VA_DMC0,
                .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
 -              .length         = SZ_4K,
 +              .length         = SZ_64K,
 +              .type           = MT_DEVICE,
 +      }, {
 +              .virtual        = (unsigned long)S5P_VA_DMC1,
 +              .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC1),
 +              .length         = SZ_64K,
                .type           = MT_DEVICE,
        }, {
                .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
@@@ -442,48 -418,23 +427,48 @@@ core_initcall(exynos4_core_init)
  #ifdef CONFIG_CACHE_L2X0
  static int __init exynos4_l2x0_cache_init(void)
  {
 -      /* TAG, Data Latency Control: 2cycle */
 -      __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 +      int ret;
 +      ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
 +      if (!ret) {
 +              l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 +              clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 +              return 0;
 +      }
  
 -      if (soc_is_exynos4210())
 -              __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 -      else if (soc_is_exynos4212() || soc_is_exynos4412())
 -              __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 +      if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
 +              l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
 +              /* TAG, Data Latency Control: 2 cycles */
 +              l2x0_saved_regs.tag_latency = 0x110;
 +
 +              if (soc_is_exynos4212() || soc_is_exynos4412())
 +                      l2x0_saved_regs.data_latency = 0x120;
 +              else
 +                      l2x0_saved_regs.data_latency = 0x110;
 +
 +              l2x0_saved_regs.prefetch_ctrl = 0x30000007;
 +              l2x0_saved_regs.pwr_ctrl =
 +                      (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
  
 -      /* L2X0 Prefetch Control */
 -      __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 +              l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
  
 -      /* L2X0 Power Control */
 -      __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
 -                   S5P_VA_L2CC + L2X0_POWER_CTRL);
 +              __raw_writel(l2x0_saved_regs.tag_latency,
 +                              S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 +              __raw_writel(l2x0_saved_regs.data_latency,
 +                              S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
  
 -      l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
 +              /* L2X0 Prefetch Control */
 +              __raw_writel(l2x0_saved_regs.prefetch_ctrl,
 +                              S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 +
 +              /* L2X0 Power Control */
 +              __raw_writel(l2x0_saved_regs.pwr_ctrl,
 +                              S5P_VA_L2CC + L2X0_POWER_CTRL);
 +
 +              clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 +              clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
 +      }
  
 +      l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
        return 0;
  }
  
index 609127df9b02f3fe0aedce427ecf14a166c5dcb3,07c79c980a8cc57a9ec7f63f192cdae8aceed609..54307b09813a8b8e8f51fd4a40a87b874bf82607
  #define EXYNOS4_PA_FIMC2              0x11820000
  #define EXYNOS4_PA_FIMC3              0x11830000
  
 +#define EXYNOS4_PA_JPEG                       0x11840000
 +
 +#define EXYNOS4_PA_G2D                        0x12800000
 +
  #define EXYNOS4_PA_I2S0                       0x03830000
  #define EXYNOS4_PA_I2S1                       0xE3100000
  #define EXYNOS4_PA_I2S2                       0xE2A00000
@@@ -61,7 -57,6 +61,7 @@@
  #define EXYNOS4_PA_KEYPAD             0x100A0000
  
  #define EXYNOS4_PA_DMC0                       0x10400000
 +#define EXYNOS4_PA_DMC1                       0x10410000
  
  #define EXYNOS4_PA_COMBINER           0x10440000
  
  #define EXYNOS4_PA_GPIO1              0x11400000
  #define EXYNOS4_PA_GPIO2              0x11000000
  #define EXYNOS4_PA_GPIO3              0x03860000
+ #define EXYNOS5_PA_GPIO1              0x11400000
+ #define EXYNOS5_PA_GPIO2              0x13400000
+ #define EXYNOS5_PA_GPIO3              0x10D10000
+ #define EXYNOS5_PA_GPIO4              0x03860000
  
  #define EXYNOS4_PA_MIPI_CSIS0         0x11880000
  #define EXYNOS4_PA_MIPI_CSIS1         0x11890000
  #define S5P_PA_FIMC1                  EXYNOS4_PA_FIMC1
  #define S5P_PA_FIMC2                  EXYNOS4_PA_FIMC2
  #define S5P_PA_FIMC3                  EXYNOS4_PA_FIMC3
 +#define S5P_PA_JPEG                   EXYNOS4_PA_JPEG
 +#define S5P_PA_G2D                    EXYNOS4_PA_G2D
  #define S5P_PA_FIMD0                  EXYNOS4_PA_FIMD0
  #define S5P_PA_HDMI                   EXYNOS4_PA_HDMI
  #define S5P_PA_IIC_HDMIPHY            EXYNOS4_PA_IIC_HDMIPHY